/[gxemul]/trunk/src/include/cpu_arm.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 10 by dpavlin, Mon Oct 8 16:18:27 2007 UTC revision 28 by dpavlin, Mon Oct 8 16:20:26 2007 UTC
# Line 2  Line 2 
2  #define CPU_ARM_H  #define CPU_ARM_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_arm.h,v 1.10 2005/06/26 22:23:43 debug Exp $   *  $Id: cpu_arm.h,v 1.68 2006/07/16 13:32:27 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 36  Line 36 
36    
37  struct cpu_family;  struct cpu_family;
38    
39    /*  ARM CPU types:  */
40    struct arm_cpu_type_def {
41            char            *name;
42            uint32_t        cpu_id;
43            int             flags;
44            int             icache_shift;
45            int             iway;
46            int             dcache_shift;
47            int             dway;
48    };
49    
50    
51  #define ARM_SL                  10  #define ARM_SL                  10
52  #define ARM_FP                  11  #define ARM_FP                  11
53  #define ARM_IP                  12  #define ARM_IP                  12
# Line 44  struct cpu_family; Line 56  struct cpu_family;
56  #define ARM_PC                  15  #define ARM_PC                  15
57  #define N_ARM_REGS              16  #define N_ARM_REGS              16
58    
59  /*  #define ARM_REG_NAMES           {                               \
60   *  Translated instruction calls:          "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",         \
61   *          "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"  }
62   *  The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets  
63   *  to arm_tc_physpage structs.  #define ARM_CONDITION_STRINGS   {                               \
64   */          "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",         \
65  #define N_IC_ARGS                       3          "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
66  #define IC_ENTRIES_SHIFT                10  
67  #define IC_ENTRIES_PER_PAGE             (1 << IC_ENTRIES_SHIFT)  /*  Names of Data Processing Instructions:  */
68  #define PC_TO_IC_ENTRY(a)               (((a) >> 2) & (IC_ENTRIES_PER_PAGE-1))  #define ARM_DPI_NAMES           {                               \
69  #define ADDR_TO_PAGENR(a)               ((a) >> (IC_ENTRIES_SHIFT+2))          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70  #define N_BASE_TABLE_ENTRIES            32768          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71  #define PAGENR_TO_TABLE_INDEX(a)        ((a) & (N_BASE_TABLE_ENTRIES-1))  
72  #define ARM_TRANSLATION_CACHE_SIZE      (1048576 * 16)  #ifdef ONEKPAGE
73  #define ARM_TRANSLATION_CACHE_MARGIN    65536  #define ARM_IC_ENTRIES_SHIFT            8
74    #else
75  struct arm_instr_call {  #define ARM_IC_ENTRIES_SHIFT            10
76          void    (*f)(struct cpu *, struct arm_instr_call *);  #endif
77          size_t  arg[N_IC_ARGS];  
78  };  #define ARM_N_IC_ARGS                   3
79    #define ARM_INSTR_ALIGNMENT_SHIFT       2
80  struct arm_tc_physpage {  #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)
81          uint32_t        next_ofs;       /*  or 0 for end of chain  */  #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82          uint32_t        physaddr;                                          & (ARM_IC_ENTRIES_PER_PAGE-1))
83          int             flags;  #define ARM_ADDR_TO_PAGENR(a)           ((a) >> (ARM_IC_ENTRIES_SHIFT \
84          struct arm_instr_call ics[IC_ENTRIES_PER_PAGE + 1];                                          + ARM_INSTR_ALIGNMENT_SHIFT))
85  };  
86    #define ARM_F_N         8       /*  Same as ARM_FLAG_*, but        */
87  #define ARM_COMBINATIONS                1  #define ARM_F_Z         4       /*  for the 'flags' field instead  */
88    #define ARM_F_C         2       /*  of cpsr.                       */
89    #define ARM_F_V         1
90    
91  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */
92  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */
93  #define ARM_FLAG_C      0x20000000      /*  Carry flag  */  #define ARM_FLAG_C      0x20000000      /*  Carry flag  */
94  #define ARM_FLAG_V      0x10000000      /*  Overflow flag  */  #define ARM_FLAG_V      0x10000000      /*  Overflow flag  */
95    #define ARM_FLAG_Q      0x08000000      /*  DSP saturation overflow  */
96  #define ARM_FLAG_I      0x00000080      /*  Interrupt disable  */  #define ARM_FLAG_I      0x00000080      /*  Interrupt disable  */
97  #define ARM_FLAG_F      0x00000040      /*  Fast Interrupt disable  */  #define ARM_FLAG_F      0x00000040      /*  Fast Interrupt disable  */
98    #define ARM_FLAG_T      0x00000020      /*  Thumb mode  */
99    
100  #define ARM_FLAG_MODE   0x0000001f  #define ARM_FLAG_MODE   0x0000001f
101  #define ARM_MODE_USR26        0x00  #define ARM_MODE_USR26        0x00
# Line 92  struct arm_tc_physpage { Line 108  struct arm_tc_physpage {
108  #define ARM_MODE_SVC32        0x13  #define ARM_MODE_SVC32        0x13
109  #define ARM_MODE_ABT32        0x17  #define ARM_MODE_ABT32        0x17
110  #define ARM_MODE_UND32        0x1b  #define ARM_MODE_UND32        0x1b
111    #define ARM_MODE_SYS32        0x1f
112    
113    #define ARM_EXCEPTION_TO_MODE   {       \
114            ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
115            ARM_MODE_ABT32, 0,              ARM_MODE_IRQ32, ARM_MODE_FIQ32  }
116    
117    #define N_ARM_EXCEPTIONS        8
118    
119    #define ARM_EXCEPTION_RESET     0
120    #define ARM_EXCEPTION_UND       1
121    #define ARM_EXCEPTION_SWI       2
122    #define ARM_EXCEPTION_PREF_ABT  3
123    #define ARM_EXCEPTION_DATA_ABT  4
124    /*  5 was address exception in 26-bit ARM  */
125    #define ARM_EXCEPTION_IRQ       6
126    #define ARM_EXCEPTION_FIQ       7
127    
128    DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t)
129    
130    #define ARM_MAX_VPH_TLB_ENTRIES         128
131    
132    
133  struct arm_cpu {  struct arm_cpu {
134          uint32_t                flags;          /*
135             *  Misc.:
136             */
137            struct arm_cpu_type_def cpu_type;
138            uint32_t                of_emul_addr;
139    
140            void                    (*coproc[16])(struct cpu *, int opcode1,
141                                        int opcode2, int l_bit, int crn, int crm,
142                                        int rd);
143    
144          /*          /*
145           *  General Purpose Registers (including the program counter):           *  General Purpose Registers (including the program counter):
# Line 103  struct arm_cpu { Line 148  struct arm_cpu {
148           *  only used to swap to/from when changing modes. (An exception is           *  only used to swap to/from when changing modes. (An exception is
149           *  r[0..7], which are never swapped out, they are always present.)           *  r[0..7], which are never swapped out, they are always present.)
150           */           */
151    
152          uint32_t                r[N_ARM_REGS];          uint32_t                r[N_ARM_REGS];
153          uint32_t                usr_r8_r14[7];  
154            uint32_t                default_r8_r14[7];      /*  usr and sys  */
155          uint32_t                fiq_r8_r14[7];          uint32_t                fiq_r8_r14[7];
156          uint32_t                irq_r13_r14[2];          uint32_t                irq_r13_r14[2];
157          uint32_t                svc_r13_r14[2];          uint32_t                svc_r13_r14[2];
158          uint32_t                abt_r13_r14[2];          uint32_t                abt_r13_r14[2];
159          uint32_t                und_r13_r14[2];          uint32_t                und_r13_r14[2];
160    
161            uint32_t                tmp_pc;         /*  Used for load/stores  */
162    
163          /*          /*
164           *  Instruction translation cache:           *  Flag/status registers:
165             *
166             *  NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
167             *  the flags should be copied from 'flags', and when cpsr is written
168             *  to, 'flags' should be updated as well.
169           */           */
170          unsigned char           *translation_cache;          size_t                  flags;
171          size_t                  translation_cache_cur_ofs;          uint32_t                cpsr;
172            uint32_t                spsr_svc;
173            uint32_t                spsr_abt;
174            uint32_t                spsr_und;
175            uint32_t                spsr_irq;
176            uint32_t                spsr_fiq;
177    
178    
179          /*  cur_ic_page is a pointer to an array of IC_ENTRIES_PER_PAGE          /*
180              instruction call entries. next_ic points to the next such           *  System Control Coprocessor registers:
181              call to be executed.  */           */
182          struct arm_tc_physpage  *cur_physpage;          uint32_t                cachetype;      /*  Cache Type Register  */
183          struct arm_instr_call   *cur_ic_page;          uint32_t                control;        /*  Control Register  */
184          struct arm_instr_call   *next_ic;          uint32_t                auxctrl;        /*  Aux. Control Register  */
185            uint32_t                ttb;            /*  Translation Table Base  */
186            uint32_t                dacr;           /*  Domain Access Control  */
187            uint32_t                fsr;            /*  Fault Status Register  */
188            uint32_t                far;            /*  Fault Address Register  */
189            uint32_t                pid;            /*  Process Id Register  */
190            uint32_t                cpar;           /*  CoProcessor Access Reg.  */
191    
192            /*  i80321 Coprocessor 6: ICU (Interrupt controller)  */
193            uint32_t                i80321_inten;   /*  enable  */
194            uint32_t                i80321_isteer;
195            uint32_t                i80321_isrc;    /*  current assertions  */
196            uint32_t                tmr0;
197            uint32_t                tmr1;
198            uint32_t                tcr0;
199            uint32_t                tcr1;
200            uint32_t                trr0;
201            uint32_t                trr1;
202            uint32_t                tisr;
203            uint32_t                wdtcr;
204    
205            /*  XScale Coprocessor 14: (Performance Monitoring Unit)  */
206            /*  XSC1 access style:  */
207            uint32_t                xsc1_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
208            uint32_t                xsc1_ccnt;      /*  Clock Counter  */
209            uint32_t                xsc1_pmn0;      /*  Perf. Counter Reg. 0  */
210            uint32_t                xsc1_pmn1;      /*  Perf. Counter Reg. 1  */
211            /*  XSC2 access style:  */
212            uint32_t                xsc2_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
213            uint32_t                xsc2_ccnt;      /*  Clock Counter  */
214            uint32_t                xsc2_inten;     /*  Interrupt Enable  */
215            uint32_t                xsc2_flag;      /*  Overflow Flag Register  */
216            uint32_t                xsc2_evtsel;    /*  Event Selection Register  */
217            uint32_t                xsc2_pmn0;      /*  Perf. Counter Reg. 0  */
218            uint32_t                xsc2_pmn1;      /*  Perf. Counter Reg. 1  */
219            uint32_t                xsc2_pmn2;      /*  Perf. Counter Reg. 2  */
220            uint32_t                xsc2_pmn3;      /*  Perf. Counter Reg. 3  */
221    
222            /*  For caching the host address of the L1 translation table:  */
223            unsigned char           *translation_table;
224            uint32_t                last_ttb;
225    
226          int                     running_translated;          /*
227          int32_t                 n_translated_instrs;           *  Interrupts:
228             */
229            int                     irq_asserted;
230    
231    
232            /*
233             *  Instruction translation cache, and 32-bit virtual -> physical ->
234             *  host address translation:
235             */
236            DYNTRANS_ITC(arm)
237            VPH_TLBS(arm,ARM)
238            VPH32(arm,ARM,uint32_t,uint8_t)
239    
240            /*  ARM specific: */
241            uint32_t                        is_userpage[N_VPH32_ENTRIES/32];
242  };  };
243    
244    
245    /*  System Control Coprocessor, control bits:  */
246    #define ARM_CONTROL_MMU         0x0001
247    #define ARM_CONTROL_ALIGN       0x0002
248    #define ARM_CONTROL_CACHE       0x0004
249    #define ARM_CONTROL_WBUFFER     0x0008
250    #define ARM_CONTROL_PROG32      0x0010
251    #define ARM_CONTROL_DATA32      0x0020
252    #define ARM_CONTROL_BIG         0x0080
253    #define ARM_CONTROL_S           0x0100
254    #define ARM_CONTROL_R           0x0200
255    #define ARM_CONTROL_F           0x0400
256    #define ARM_CONTROL_Z           0x0800
257    #define ARM_CONTROL_ICACHE      0x1000
258    #define ARM_CONTROL_V           0x2000
259    #define ARM_CONTROL_RR          0x4000
260    #define ARM_CONTROL_L4          0x8000
261    
262    /*  Auxiliary Control Register bits:  */
263    #define ARM_AUXCTRL_MD          0x30    /*  MiniData Cache Attribute  */
264    #define ARM_AUXCTRL_MD_SHIFT    4
265    #define ARM_AUXCTRL_P           0x02    /*  Page Table Memory Attribute  */
266    #define ARM_AUXCTRL_K           0x01    /*  Write Buffer Coalescing Disable  */
267    
268    /*  Cache Type register bits:  */
269    #define ARM_CACHETYPE_CLASS             0x1e000000
270    #define ARM_CACHETYPE_CLASS_SHIFT       25
271    #define ARM_CACHETYPE_HARVARD           0x01000000
272    #define ARM_CACHETYPE_HARVARD_SHIFT     24
273    #define ARM_CACHETYPE_DSIZE             0x001c0000
274    #define ARM_CACHETYPE_DSIZE_SHIFT       18
275    #define ARM_CACHETYPE_DASSOC            0x00038000
276    #define ARM_CACHETYPE_DASSOC_SHIFT      15
277    #define ARM_CACHETYPE_DLINE             0x00003000
278    #define ARM_CACHETYPE_DLINE_SHIFT       12
279    #define ARM_CACHETYPE_ISIZE             0x000001c0
280    #define ARM_CACHETYPE_ISIZE_SHIFT       6
281    #define ARM_CACHETYPE_IASSOC            0x00000038
282    #define ARM_CACHETYPE_IASSOC_SHIFT      3
283    #define ARM_CACHETYPE_ILINE             0x00000003
284    #define ARM_CACHETYPE_ILINE_SHIFT       0
285    
286  /*  cpu_arm.c:  */  /*  cpu_arm.c:  */
287    void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
288    void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
289            uint32_t paddr);
290    void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
291            uint32_t paddr);
292    void arm_exception(struct cpu *, int);
293    int arm_run_instr(struct cpu *cpu);
294    void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
295            unsigned char *host_page, int writeflag, uint64_t paddr_page);
296    void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
297    void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
298    void arm_load_register_bank(struct cpu *cpu);
299    void arm_save_register_bank(struct cpu *cpu);
300  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
301          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
302  int arm_cpu_family_init(struct cpu_family *);  int arm_cpu_family_init(struct cpu_family *);
303    
304    /*  cpu_arm_coproc.c:  */
305    void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
306            int crn, int crm, int rd);
307    void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
308            int crn, int crm, int rd);
309    void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
310            int crn, int crm, int rd);
311    
312    /*  memory_arm.c:  */
313    int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
314            uint64_t *return_addr, int flags);
315    int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
316            uint64_t *return_addr, int flags);
317    
318  #endif  /*  CPU_ARM_H  */  #endif  /*  CPU_ARM_H  */
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