/[gxemul]/trunk/src/include/cpu_arm.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 20 by dpavlin, Mon Oct 8 16:19:23 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define CPU_ARM_H  #define CPU_ARM_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_arm.h,v 1.57 2005/11/16 21:15:19 debug Exp $   *  $Id: cpu_arm.h,v 1.65 2006/02/17 18:38:30 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 69  struct arm_cpu_type_def { Line 69  struct arm_cpu_type_def {
69          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71    
72    #ifdef ONEKPAGE
73    #define ARM_IC_ENTRIES_SHIFT            8
74    #else
75    #define ARM_IC_ENTRIES_SHIFT            10
76    #endif
77    
78  #define ARM_N_IC_ARGS                   3  #define ARM_N_IC_ARGS                   3
79  #define ARM_INSTR_ALIGNMENT_SHIFT       2  #define ARM_INSTR_ALIGNMENT_SHIFT       2
 #define ARM_IC_ENTRIES_SHIFT            10  
80  #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)  #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)
81  #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \  #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82                                          & (ARM_IC_ENTRIES_PER_PAGE-1))                                          & (ARM_IC_ENTRIES_PER_PAGE-1))
# Line 135  struct arm_tc_physpage { Line 140  struct arm_tc_physpage {
140  #define ARM_EXCEPTION_FIQ       7  #define ARM_EXCEPTION_FIQ       7
141    
142    
 #define ARM_N_VPH_ENTRIES       1048576  
   
143  #define ARM_MAX_VPH_TLB_ENTRIES         128  #define ARM_MAX_VPH_TLB_ENTRIES         128
144  struct arm_vpg_tlb_entry {  struct arm_vpg_tlb_entry {
145          unsigned char   valid;          unsigned char   valid;
# Line 196  struct arm_cpu { Line 199  struct arm_cpu {
199          /*          /*
200           *  System Control Coprocessor registers:           *  System Control Coprocessor registers:
201           */           */
202          uint32_t                control;          uint32_t                cachetype;      /*  Cache Type Register  */
203            uint32_t                control;        /*  Control Register  */
204            uint32_t                auxctrl;        /*  Aux. Control Register  */
205          uint32_t                ttb;            /*  Translation Table Base  */          uint32_t                ttb;            /*  Translation Table Base  */
206          uint32_t                dacr;           /*  Domain Access Control  */          uint32_t                dacr;           /*  Domain Access Control  */
207          uint32_t                fsr;            /*  Fault Status Register  */          uint32_t                fsr;            /*  Fault Status Register  */
208          uint32_t                far;            /*  Fault Address Register  */          uint32_t                far;            /*  Fault Address Register  */
209          uint32_t                pid;            /*  Process Id Register  */          uint32_t                pid;            /*  Process Id Register  */
210            uint32_t                cpar;           /*  CoProcessor Access Reg.  */
211    
212            /*  i80321 Coprocessor 6: ICU (Interrupt controller)  */
213            uint32_t                i80321_inten;   /*  enable  */
214            uint32_t                i80321_isteer;
215            uint32_t                i80321_isrc;    /*  current assertions  */
216            uint32_t                tmr0;
217            uint32_t                tmr1;
218            uint32_t                tcr0;
219            uint32_t                tcr1;
220            uint32_t                trr0;
221            uint32_t                trr1;
222            uint32_t                tisr;
223            uint32_t                wdtcr;
224    
225            /*  XScale Coprocessor 14: (Performance Monitoring Unit)  */
226            /*  XSC1 access style:  */
227            uint32_t                xsc1_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
228            uint32_t                xsc1_ccnt;      /*  Clock Counter  */
229            uint32_t                xsc1_pmn0;      /*  Perf. Counter Reg. 0  */
230            uint32_t                xsc1_pmn1;      /*  Perf. Counter Reg. 1  */
231            /*  XSC2 access style:  */
232            uint32_t                xsc2_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
233            uint32_t                xsc2_ccnt;      /*  Clock Counter  */
234            uint32_t                xsc2_inten;     /*  Interrupt Enable  */
235            uint32_t                xsc2_flag;      /*  Overflow Flag Register  */
236            uint32_t                xsc2_evtsel;    /*  Event Selection Register  */
237            uint32_t                xsc2_pmn0;      /*  Perf. Counter Reg. 0  */
238            uint32_t                xsc2_pmn1;      /*  Perf. Counter Reg. 1  */
239            uint32_t                xsc2_pmn2;      /*  Perf. Counter Reg. 2  */
240            uint32_t                xsc2_pmn3;      /*  Perf. Counter Reg. 3  */
241    
242          /*  For caching the host address of the L1 translation table:  */          /*  For caching the host address of the L1 translation table:  */
243          unsigned char           *translation_table;          unsigned char           *translation_table;
244          uint32_t                last_ttb;          uint32_t                last_ttb;
245    
   
246          /*          /*
247           *  Interrupts:           *  Interrupts:
248           */           */
# Line 215  struct arm_cpu { Line 250  struct arm_cpu {
250    
251    
252          /*          /*
253           *  Instruction translation cache:           *  Instruction translation cache, and 32-bit virtual -> physical ->
254             *  host address translation:
255           */           */
256            DYNTRANS_ITC(arm)
257          /*  cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE          VPH_TLBS(arm,ARM)
258              instruction call entries. next_ic points to the next such          VPH32(arm,ARM,uint32_t,uint8_t)
             call to be executed.  */  
         struct arm_tc_physpage  *cur_physpage;  
         struct arm_instr_call   *cur_ic_page;  
         struct arm_instr_call   *next_ic;  
   
         void                    (*combination_check)(struct cpu *,  
                                     struct arm_instr_call *, int low_addr);  
   
         /*  
          *  Virtual -> physical -> host address translation:  
          *  
          *  host_load and host_store point to arrays of ARM_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  ARM_N_VPH_ENTRIES uint32_t.  
          */  
   
         struct arm_vpg_tlb_entry        vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];  
         unsigned char                   *host_load[ARM_N_VPH_ENTRIES];  
         unsigned char                   *host_store[ARM_N_VPH_ENTRIES];  
         uint32_t                        phys_addr[ARM_N_VPH_ENTRIES];  
         struct arm_tc_physpage          *phys_page[ARM_N_VPH_ENTRIES];  
   
         uint32_t                        phystranslation[ARM_N_VPH_ENTRIES/32];  
         uint8_t                         vaddr_to_tlbindex[ARM_N_VPH_ENTRIES];  
259    
260          /*  ARM specific: */          /*  ARM specific: */
261          uint32_t                        is_userpage[ARM_N_VPH_ENTRIES/32];          uint32_t                        is_userpage[N_VPH32_ENTRIES/32];
262  };  };
263    
264    
# Line 267  struct arm_cpu { Line 279  struct arm_cpu {
279  #define ARM_CONTROL_RR          0x4000  #define ARM_CONTROL_RR          0x4000
280  #define ARM_CONTROL_L4          0x8000  #define ARM_CONTROL_L4          0x8000
281    
282    /*  Auxiliary Control Register bits:  */
283    #define ARM_AUXCTRL_MD          0x30    /*  MiniData Cache Attribute  */
284    #define ARM_AUXCTRL_MD_SHIFT    4
285    #define ARM_AUXCTRL_P           0x02    /*  Page Table Memory Attribute  */
286    #define ARM_AUXCTRL_K           0x01    /*  Write Buffer Coalescing Disable  */
287    
288    /*  Cache Type register bits:  */
289    #define ARM_CACHETYPE_CLASS             0x1e000000
290    #define ARM_CACHETYPE_CLASS_SHIFT       25
291    #define ARM_CACHETYPE_HARVARD           0x01000000
292    #define ARM_CACHETYPE_HARVARD_SHIFT     24
293    #define ARM_CACHETYPE_DSIZE             0x001c0000
294    #define ARM_CACHETYPE_DSIZE_SHIFT       18
295    #define ARM_CACHETYPE_DASSOC            0x00038000
296    #define ARM_CACHETYPE_DASSOC_SHIFT      15
297    #define ARM_CACHETYPE_DLINE             0x00003000
298    #define ARM_CACHETYPE_DLINE_SHIFT       12
299    #define ARM_CACHETYPE_ISIZE             0x000001c0
300    #define ARM_CACHETYPE_ISIZE_SHIFT       6
301    #define ARM_CACHETYPE_IASSOC            0x00000038
302    #define ARM_CACHETYPE_IASSOC_SHIFT      3
303    #define ARM_CACHETYPE_ILINE             0x00000003
304    #define ARM_CACHETYPE_ILINE_SHIFT       0
305    
306  /*  cpu_arm.c:  */  /*  cpu_arm.c:  */
307  void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);  void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
308  void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,  void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
# Line 287  int arm_cpu_family_init(struct cpu_famil Line 323  int arm_cpu_family_init(struct cpu_famil
323  /*  cpu_arm_coproc.c:  */  /*  cpu_arm_coproc.c:  */
324  void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,  void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
325          int crn, int crm, int rd);          int crn, int crm, int rd);
326  void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,  void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
327          int crn, int crm, int rd);          int crn, int crm, int rd);
328  void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,  void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
329          int crn, int crm, int rd);          int crn, int crm, int rd);
330    
331  /*  memory_arm.c:  */  /*  memory_arm.c:  */
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