/[gxemul]/trunk/src/include/cpu_arm.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 16 by dpavlin, Mon Oct 8 16:19:01 2007 UTC revision 18 by dpavlin, Mon Oct 8 16:19:11 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_arm.h,v 1.44 2005/10/10 18:43:37 debug Exp $   *  $Id: cpu_arm.h,v 1.53 2005/10/27 14:01:15 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 85  struct arm_instr_call { Line 85  struct arm_instr_call {
85    
86  /*  Translation cache struct for each physical page:  */  /*  Translation cache struct for each physical page:  */
87  struct arm_tc_physpage {  struct arm_tc_physpage {
88            struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
89          uint32_t        next_ofs;       /*  or 0 for end of chain  */          uint32_t        next_ofs;       /*  or 0 for end of chain  */
90          uint32_t        physaddr;          uint32_t        physaddr;
91          int             flags;          int             flags;
         struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];  
92  };  };
93    
94    
# Line 132  struct arm_tc_physpage { Line 132  struct arm_tc_physpage {
132    
133  #define ARM_N_VPH_ENTRIES       1048576  #define ARM_N_VPH_ENTRIES       1048576
134    
135  #define ARM_MAX_VPH_TLB_ENTRIES         32  #define ARM_MAX_VPH_TLB_ENTRIES         128
136  struct arm_vpg_tlb_entry {  struct arm_vpg_tlb_entry {
137          int             valid;          int             valid;
138          int             writeflag;          int             writeflag;
# Line 192  struct arm_cpu { Line 192  struct arm_cpu {
192          uint32_t                far;            /*  Fault Address Register  */          uint32_t                far;            /*  Fault Address Register  */
193          uint32_t                pid;            /*  Process Id Register  */          uint32_t                pid;            /*  Process Id Register  */
194    
195            /*  For caching the host address of the L1 translation table:  */
196            unsigned char           *translation_table;
197            uint32_t                last_ttb;
198    
199    
200          /*          /*
201           *  Interrupts:           *  Interrupts:
# Line 224  struct arm_cpu { Line 228  struct arm_cpu {
228          unsigned char                   *host_store[ARM_N_VPH_ENTRIES];          unsigned char                   *host_store[ARM_N_VPH_ENTRIES];
229          uint32_t                        phys_addr[ARM_N_VPH_ENTRIES];          uint32_t                        phys_addr[ARM_N_VPH_ENTRIES];
230          struct arm_tc_physpage          *phys_page[ARM_N_VPH_ENTRIES];          struct arm_tc_physpage          *phys_page[ARM_N_VPH_ENTRIES];
231    
232            uint32_t                        phystranslation[ARM_N_VPH_ENTRIES/32];
233            int16_t                         vaddr_to_tlbindex[ARM_N_VPH_ENTRIES];
234    
235            /*  ARM specific: */
236            unsigned char                   is_userpage[ARM_N_VPH_ENTRIES/8];
237  };  };
238    
239    
# Line 245  struct arm_cpu { Line 255  struct arm_cpu {
255  #define ARM_CONTROL_L4          0x8000  #define ARM_CONTROL_L4          0x8000
256    
257  /*  cpu_arm.c:  */  /*  cpu_arm.c:  */
258    void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
259    void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
260            uint32_t paddr);
261    void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
262            uint32_t paddr);
263  void arm_exception(struct cpu *, int);  void arm_exception(struct cpu *, int);
264  void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
265          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
266  void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);  void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
267  void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
 void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);  
268  void arm_load_register_bank(struct cpu *cpu);  void arm_load_register_bank(struct cpu *cpu);
269  void arm_save_register_bank(struct cpu *cpu);  void arm_save_register_bank(struct cpu *cpu);
270  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
# Line 268  void arm_coproc_i80321_14(struct cpu *cp Line 282  void arm_coproc_i80321_14(struct cpu *cp
282  /*  memory_arm.c:  */  /*  memory_arm.c:  */
283  int arm_translate_address(struct cpu *cpu, uint64_t vaddr,  int arm_translate_address(struct cpu *cpu, uint64_t vaddr,
284          uint64_t *return_addr, int flags);          uint64_t *return_addr, int flags);
285    int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr,
286            uint64_t *return_addr, int flags);
287    
288  #endif  /*  CPU_ARM_H  */  #endif  /*  CPU_ARM_H  */
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