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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.h,v 1.1 2005/06/03 07:39:28 debug Exp $ |
* $Id: cpu_arm.h,v 1.10 2005/06/26 22:23:43 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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|
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struct cpu_family; |
struct cpu_family; |
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#define ARM_SL 10 |
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#define ARM_FP 11 |
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#define ARM_IP 12 |
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#define ARM_SP 13 |
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#define ARM_LR 14 |
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#define ARM_PC 15 |
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#define N_ARM_REGS 16 |
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/* |
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* Translated instruction calls: |
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* |
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* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets |
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* to arm_tc_physpage structs. |
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*/ |
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#define N_IC_ARGS 3 |
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#define IC_ENTRIES_SHIFT 10 |
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#define IC_ENTRIES_PER_PAGE (1 << IC_ENTRIES_SHIFT) |
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#define PC_TO_IC_ENTRY(a) (((a) >> 2) & (IC_ENTRIES_PER_PAGE-1)) |
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#define ADDR_TO_PAGENR(a) ((a) >> (IC_ENTRIES_SHIFT+2)) |
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#define N_BASE_TABLE_ENTRIES 32768 |
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#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
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#define ARM_TRANSLATION_CACHE_SIZE (1048576 * 16) |
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#define ARM_TRANSLATION_CACHE_MARGIN 65536 |
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struct arm_instr_call { |
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void (*f)(struct cpu *, struct arm_instr_call *); |
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size_t arg[N_IC_ARGS]; |
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}; |
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struct arm_tc_physpage { |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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uint32_t physaddr; |
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int flags; |
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struct arm_instr_call ics[IC_ENTRIES_PER_PAGE + 1]; |
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}; |
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#define ARM_COMBINATIONS 1 |
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#define ARM_FLAG_N 0x80000000 /* Negative flag */ |
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#define ARM_FLAG_Z 0x40000000 /* Zero flag */ |
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#define ARM_FLAG_C 0x20000000 /* Carry flag */ |
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#define ARM_FLAG_V 0x10000000 /* Overflow flag */ |
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#define ARM_FLAG_I 0x00000080 /* Interrupt disable */ |
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#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */ |
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#define ARM_FLAG_MODE 0x0000001f |
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#define ARM_MODE_USR26 0x00 |
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#define ARM_MODE_FIQ26 0x01 |
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#define ARM_MODE_IRQ26 0x02 |
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#define ARM_MODE_SVC26 0x03 |
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#define ARM_MODE_USR32 0x10 |
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#define ARM_MODE_FIQ32 0x11 |
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#define ARM_MODE_IRQ32 0x12 |
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#define ARM_MODE_SVC32 0x13 |
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#define ARM_MODE_ABT32 0x17 |
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#define ARM_MODE_UND32 0x1b |
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struct arm_cpu { |
struct arm_cpu { |
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int dummy; |
uint32_t flags; |
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/* |
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* General Purpose Registers (including the program counter): |
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* |
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* r[] always contains the current register set. The others are |
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* only used to swap to/from when changing modes. (An exception is |
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* r[0..7], which are never swapped out, they are always present.) |
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*/ |
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uint32_t r[N_ARM_REGS]; |
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uint32_t usr_r8_r14[7]; |
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uint32_t fiq_r8_r14[7]; |
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uint32_t irq_r13_r14[2]; |
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uint32_t svc_r13_r14[2]; |
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uint32_t abt_r13_r14[2]; |
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uint32_t und_r13_r14[2]; |
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/* |
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* Instruction translation cache: |
116 |
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*/ |
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unsigned char *translation_cache; |
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size_t translation_cache_cur_ofs; |
119 |
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|
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/* cur_ic_page is a pointer to an array of IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct arm_tc_physpage *cur_physpage; |
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struct arm_instr_call *cur_ic_page; |
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struct arm_instr_call *next_ic; |
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|
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int running_translated; |
128 |
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int32_t n_translated_instrs; |
129 |
}; |
}; |
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