/[gxemul]/trunk/src/include/cpu_arm.h
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revision 12 by dpavlin, Mon Oct 8 16:18:38 2007 UTC revision 26 by dpavlin, Mon Oct 8 16:20:10 2007 UTC
# Line 2  Line 2 
2  #define CPU_ARM_H  #define CPU_ARM_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_arm.h,v 1.26 2005/08/14 23:44:23 debug Exp $   *  $Id: cpu_arm.h,v 1.66 2006/06/24 21:47:23 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 36  Line 36 
36    
37  struct cpu_family;  struct cpu_family;
38    
39    /*  ARM CPU types:  */
40    struct arm_cpu_type_def {
41            char            *name;
42            uint32_t        cpu_id;
43            int             flags;
44            int             icache_shift;
45            int             iway;
46            int             dcache_shift;
47            int             dway;
48    };
49    
50    
51  #define ARM_SL                  10  #define ARM_SL                  10
52  #define ARM_FP                  11  #define ARM_FP                  11
53  #define ARM_IP                  12  #define ARM_IP                  12
# Line 57  struct cpu_family; Line 69  struct cpu_family;
69          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \          "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }          "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71    
72    #ifdef ONEKPAGE
73    #define ARM_IC_ENTRIES_SHIFT            8
74    #else
75    #define ARM_IC_ENTRIES_SHIFT            10
76    #endif
77    
78  #define ARM_N_IC_ARGS                   3  #define ARM_N_IC_ARGS                   3
79  #define ARM_INSTR_ALIGNMENT_SHIFT       2  #define ARM_INSTR_ALIGNMENT_SHIFT       2
 #define ARM_IC_ENTRIES_SHIFT            10  
80  #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)  #define ARM_IC_ENTRIES_PER_PAGE         (1 << ARM_IC_ENTRIES_SHIFT)
81  #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \  #define ARM_PC_TO_IC_ENTRY(a)           (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82                                          & (ARM_IC_ENTRIES_PER_PAGE-1))                                          & (ARM_IC_ENTRIES_PER_PAGE-1))
# Line 73  struct arm_instr_call { Line 90  struct arm_instr_call {
90    
91  /*  Translation cache struct for each physical page:  */  /*  Translation cache struct for each physical page:  */
92  struct arm_tc_physpage {  struct arm_tc_physpage {
93            struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
94          uint32_t        next_ofs;       /*  or 0 for end of chain  */          uint32_t        next_ofs;       /*  or 0 for end of chain  */
95          uint32_t        physaddr;          uint32_t        physaddr;
96          int             flags;          int             flags;
         struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];  
97  };  };
98    
99    
100    #define ARM_F_N         8       /*  Same as ARM_FLAG_*, but        */
101    #define ARM_F_Z         4       /*  for the 'flags' field instead  */
102    #define ARM_F_C         2       /*  of cpsr.                       */
103    #define ARM_F_V         1
104    
105  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */  #define ARM_FLAG_N      0x80000000      /*  Negative flag  */
106  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */  #define ARM_FLAG_Z      0x40000000      /*  Zero flag  */
107  #define ARM_FLAG_C      0x20000000      /*  Carry flag  */  #define ARM_FLAG_C      0x20000000      /*  Carry flag  */
108  #define ARM_FLAG_V      0x10000000      /*  Overflow flag  */  #define ARM_FLAG_V      0x10000000      /*  Overflow flag  */
109    #define ARM_FLAG_Q      0x08000000      /*  DSP saturation overflow  */
110  #define ARM_FLAG_I      0x00000080      /*  Interrupt disable  */  #define ARM_FLAG_I      0x00000080      /*  Interrupt disable  */
111  #define ARM_FLAG_F      0x00000040      /*  Fast Interrupt disable  */  #define ARM_FLAG_F      0x00000040      /*  Fast Interrupt disable  */
112    #define ARM_FLAG_T      0x00000020      /*  Thumb mode  */
113    
114  #define ARM_FLAG_MODE   0x0000001f  #define ARM_FLAG_MODE   0x0000001f
115  #define ARM_MODE_USR26        0x00  #define ARM_MODE_USR26        0x00
# Line 98  struct arm_tc_physpage { Line 122  struct arm_tc_physpage {
122  #define ARM_MODE_SVC32        0x13  #define ARM_MODE_SVC32        0x13
123  #define ARM_MODE_ABT32        0x17  #define ARM_MODE_ABT32        0x17
124  #define ARM_MODE_UND32        0x1b  #define ARM_MODE_UND32        0x1b
125    #define ARM_MODE_SYS32        0x1f
126    
127    #define ARM_EXCEPTION_TO_MODE   {       \
128            ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
129            ARM_MODE_ABT32, 0,              ARM_MODE_IRQ32, ARM_MODE_FIQ32  }
130    
131    #define N_ARM_EXCEPTIONS        8
132    
133    #define ARM_EXCEPTION_RESET     0
134    #define ARM_EXCEPTION_UND       1
135    #define ARM_EXCEPTION_SWI       2
136    #define ARM_EXCEPTION_PREF_ABT  3
137    #define ARM_EXCEPTION_DATA_ABT  4
138    /*  5 was address exception in 26-bit ARM  */
139    #define ARM_EXCEPTION_IRQ       6
140    #define ARM_EXCEPTION_FIQ       7
141    
 #define ARM_N_VPH_ENTRIES       1048576  
142    
143  #define ARM_MAX_VPH_TLB_ENTRIES         256  #define ARM_MAX_VPH_TLB_ENTRIES         128
144  struct arm_vpg_tlb_entry {  struct arm_vpg_tlb_entry {
145          int             valid;          unsigned char   valid;
146          int             writeflag;          unsigned char   writeflag;
         int64_t         timestamp;  
         unsigned char   *host_page;  
147          uint32_t        vaddr_page;          uint32_t        vaddr_page;
148          uint32_t        paddr_page;          uint32_t        paddr_page;
149            unsigned char   *host_page;
150  };  };
151    
152    
# Line 117  struct arm_cpu { Line 154  struct arm_cpu {
154          /*          /*
155           *  Misc.:           *  Misc.:
156           */           */
157          uint32_t                flags;          struct arm_cpu_type_def cpu_type;
158            uint32_t                of_emul_addr;
159    
160            void                    (*coproc[16])(struct cpu *, int opcode1,
161                                        int opcode2, int l_bit, int crn, int crm,
162                                        int rd);
163    
164          /*          /*
165           *  General Purpose Registers (including the program counter):           *  General Purpose Registers (including the program counter):
# Line 129  struct arm_cpu { Line 170  struct arm_cpu {
170           */           */
171    
172          uint32_t                r[N_ARM_REGS];          uint32_t                r[N_ARM_REGS];
173          uint32_t                usr_r8_r14[7];  
174            uint32_t                default_r8_r14[7];      /*  usr and sys  */
175          uint32_t                fiq_r8_r14[7];          uint32_t                fiq_r8_r14[7];
176          uint32_t                irq_r13_r14[2];          uint32_t                irq_r13_r14[2];
177          uint32_t                svc_r13_r14[2];          uint32_t                svc_r13_r14[2];
178          uint32_t                abt_r13_r14[2];          uint32_t                abt_r13_r14[2];
179          uint32_t                und_r13_r14[2];          uint32_t                und_r13_r14[2];
180    
181            uint32_t                tmp_pc;         /*  Used for load/stores  */
182    
183            /*
184             *  Flag/status registers:
185             *
186             *  NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
187             *  the flags should be copied from 'flags', and when cpsr is written
188             *  to, 'flags' should be updated as well.
189             */
190            size_t                  flags;
191            uint32_t                cpsr;
192            uint32_t                spsr_svc;
193            uint32_t                spsr_abt;
194            uint32_t                spsr_und;
195            uint32_t                spsr_irq;
196            uint32_t                spsr_fiq;
197    
198    
199          /*          /*
200           *  Instruction translation cache:           *  System Control Coprocessor registers:
201           */           */
202            uint32_t                cachetype;      /*  Cache Type Register  */
203            uint32_t                control;        /*  Control Register  */
204            uint32_t                auxctrl;        /*  Aux. Control Register  */
205            uint32_t                ttb;            /*  Translation Table Base  */
206            uint32_t                dacr;           /*  Domain Access Control  */
207            uint32_t                fsr;            /*  Fault Status Register  */
208            uint32_t                far;            /*  Fault Address Register  */
209            uint32_t                pid;            /*  Process Id Register  */
210            uint32_t                cpar;           /*  CoProcessor Access Reg.  */
211    
212            /*  i80321 Coprocessor 6: ICU (Interrupt controller)  */
213            uint32_t                i80321_inten;   /*  enable  */
214            uint32_t                i80321_isteer;
215            uint32_t                i80321_isrc;    /*  current assertions  */
216            uint32_t                tmr0;
217            uint32_t                tmr1;
218            uint32_t                tcr0;
219            uint32_t                tcr1;
220            uint32_t                trr0;
221            uint32_t                trr1;
222            uint32_t                tisr;
223            uint32_t                wdtcr;
224    
225            /*  XScale Coprocessor 14: (Performance Monitoring Unit)  */
226            /*  XSC1 access style:  */
227            uint32_t                xsc1_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
228            uint32_t                xsc1_ccnt;      /*  Clock Counter  */
229            uint32_t                xsc1_pmn0;      /*  Perf. Counter Reg. 0  */
230            uint32_t                xsc1_pmn1;      /*  Perf. Counter Reg. 1  */
231            /*  XSC2 access style:  */
232            uint32_t                xsc2_pmnc;      /*  Perf. Monitor Ctrl Reg.  */
233            uint32_t                xsc2_ccnt;      /*  Clock Counter  */
234            uint32_t                xsc2_inten;     /*  Interrupt Enable  */
235            uint32_t                xsc2_flag;      /*  Overflow Flag Register  */
236            uint32_t                xsc2_evtsel;    /*  Event Selection Register  */
237            uint32_t                xsc2_pmn0;      /*  Perf. Counter Reg. 0  */
238            uint32_t                xsc2_pmn1;      /*  Perf. Counter Reg. 1  */
239            uint32_t                xsc2_pmn2;      /*  Perf. Counter Reg. 2  */
240            uint32_t                xsc2_pmn3;      /*  Perf. Counter Reg. 3  */
241    
242            /*  For caching the host address of the L1 translation table:  */
243            unsigned char           *translation_table;
244            uint32_t                last_ttb;
245    
246          /*  cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE          /*
247              instruction call entries. next_ic points to the next such           *  Interrupts:
248              call to be executed.  */           */
249          struct arm_tc_physpage  *cur_physpage;          int                     irq_asserted;
         struct arm_instr_call   *cur_ic_page;  
         struct arm_instr_call   *next_ic;  
250    
251    
252          /*          /*
253           *  Virtual -> physical -> host address translation:           *  Instruction translation cache, and 32-bit virtual -> physical ->
254           *           *  host address translation:
          *  host_load and host_store point to arrays of ARM_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  ARM_N_VPH_ENTRIES uint32_t.  
255           */           */
256            DYNTRANS_ITC(arm)
257            VPH_TLBS(arm,ARM)
258            VPH32(arm,ARM,uint32_t,uint8_t)
259    
260          struct arm_vpg_tlb_entry        vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];          /*  ARM specific: */
261          unsigned char                   *host_load[ARM_N_VPH_ENTRIES];          uint32_t                        is_userpage[N_VPH32_ENTRIES/32];
         unsigned char                   *host_store[ARM_N_VPH_ENTRIES];  
         uint32_t                        phys_addr[ARM_N_VPH_ENTRIES];  
         struct arm_tc_physpage          *phys_page[ARM_N_VPH_ENTRIES];  
262  };  };
263    
264    
265    /*  System Control Coprocessor, control bits:  */
266    #define ARM_CONTROL_MMU         0x0001
267    #define ARM_CONTROL_ALIGN       0x0002
268    #define ARM_CONTROL_CACHE       0x0004
269    #define ARM_CONTROL_WBUFFER     0x0008
270    #define ARM_CONTROL_PROG32      0x0010
271    #define ARM_CONTROL_DATA32      0x0020
272    #define ARM_CONTROL_BIG         0x0080
273    #define ARM_CONTROL_S           0x0100
274    #define ARM_CONTROL_R           0x0200
275    #define ARM_CONTROL_F           0x0400
276    #define ARM_CONTROL_Z           0x0800
277    #define ARM_CONTROL_ICACHE      0x1000
278    #define ARM_CONTROL_V           0x2000
279    #define ARM_CONTROL_RR          0x4000
280    #define ARM_CONTROL_L4          0x8000
281    
282    /*  Auxiliary Control Register bits:  */
283    #define ARM_AUXCTRL_MD          0x30    /*  MiniData Cache Attribute  */
284    #define ARM_AUXCTRL_MD_SHIFT    4
285    #define ARM_AUXCTRL_P           0x02    /*  Page Table Memory Attribute  */
286    #define ARM_AUXCTRL_K           0x01    /*  Write Buffer Coalescing Disable  */
287    
288    /*  Cache Type register bits:  */
289    #define ARM_CACHETYPE_CLASS             0x1e000000
290    #define ARM_CACHETYPE_CLASS_SHIFT       25
291    #define ARM_CACHETYPE_HARVARD           0x01000000
292    #define ARM_CACHETYPE_HARVARD_SHIFT     24
293    #define ARM_CACHETYPE_DSIZE             0x001c0000
294    #define ARM_CACHETYPE_DSIZE_SHIFT       18
295    #define ARM_CACHETYPE_DASSOC            0x00038000
296    #define ARM_CACHETYPE_DASSOC_SHIFT      15
297    #define ARM_CACHETYPE_DLINE             0x00003000
298    #define ARM_CACHETYPE_DLINE_SHIFT       12
299    #define ARM_CACHETYPE_ISIZE             0x000001c0
300    #define ARM_CACHETYPE_ISIZE_SHIFT       6
301    #define ARM_CACHETYPE_IASSOC            0x00000038
302    #define ARM_CACHETYPE_IASSOC_SHIFT      3
303    #define ARM_CACHETYPE_ILINE             0x00000003
304    #define ARM_CACHETYPE_ILINE_SHIFT       0
305    
306  /*  cpu_arm.c:  */  /*  cpu_arm.c:  */
307    void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
308    void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
309            uint32_t paddr);
310    void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
311            uint32_t paddr);
312    void arm_exception(struct cpu *, int);
313  void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
314          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
315  void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr);  void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
316  void arm_invalidate_code_translation_caches(struct cpu *cpu);  void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
317    void arm_load_register_bank(struct cpu *cpu);
318    void arm_save_register_bank(struct cpu *cpu);
319  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
320          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
321  int arm_cpu_family_init(struct cpu_family *);  int arm_cpu_family_init(struct cpu_family *);
322    
323    /*  cpu_arm_coproc.c:  */
324    void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
325            int crn, int crm, int rd);
326    void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
327            int crn, int crm, int rd);
328    void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
329            int crn, int crm, int rd);
330    
331    /*  memory_arm.c:  */
332    int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
333            uint64_t *return_addr, int flags);
334    int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
335            uint64_t *return_addr, int flags);
336    
337  #endif  /*  CPU_ARM_H  */  #endif  /*  CPU_ARM_H  */
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