/[gxemul]/trunk/src/include/cpu_arm.h
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Revision 42 - (hide annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 10600 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 dpavlin 6 #ifndef CPU_ARM_H
2     #define CPU_ARM_H
3    
4     /*
5 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 dpavlin 6 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 42 * $Id: cpu_arm.h,v 1.74 2007/06/14 04:53:14 debug Exp $
32 dpavlin 6 */
33    
34     #include "misc.h"
35 dpavlin 34 #include "interrupt.h"
36 dpavlin 6
37     struct cpu_family;
38 dpavlin 42 struct timer;
39 dpavlin 6
40 dpavlin 14 /* ARM CPU types: */
41     struct arm_cpu_type_def {
42     char *name;
43     uint32_t cpu_id;
44     int flags;
45     int icache_shift;
46     int iway;
47     int dcache_shift;
48     int dway;
49     };
50    
51    
52 dpavlin 10 #define ARM_SL 10
53     #define ARM_FP 11
54     #define ARM_IP 12
55     #define ARM_SP 13
56     #define ARM_LR 14
57     #define ARM_PC 15
58     #define N_ARM_REGS 16
59    
60 dpavlin 12 #define ARM_REG_NAMES { \
61     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
62     "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
63 dpavlin 10
64 dpavlin 12 #define ARM_CONDITION_STRINGS { \
65     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
66     "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
67    
68     /* Names of Data Processing Instructions: */
69     #define ARM_DPI_NAMES { \
70     "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
71     "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
72    
73 dpavlin 22 #define ARM_IC_ENTRIES_SHIFT 10
74    
75 dpavlin 12 #define ARM_N_IC_ARGS 3
76     #define ARM_INSTR_ALIGNMENT_SHIFT 2
77     #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
78     #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
79     & (ARM_IC_ENTRIES_PER_PAGE-1))
80     #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
81     + ARM_INSTR_ALIGNMENT_SHIFT))
82    
83 dpavlin 20 #define ARM_F_N 8 /* Same as ARM_FLAG_*, but */
84     #define ARM_F_Z 4 /* for the 'flags' field instead */
85     #define ARM_F_C 2 /* of cpsr. */
86     #define ARM_F_V 1
87    
88 dpavlin 10 #define ARM_FLAG_N 0x80000000 /* Negative flag */
89     #define ARM_FLAG_Z 0x40000000 /* Zero flag */
90     #define ARM_FLAG_C 0x20000000 /* Carry flag */
91     #define ARM_FLAG_V 0x10000000 /* Overflow flag */
92 dpavlin 14 #define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
93 dpavlin 10 #define ARM_FLAG_I 0x00000080 /* Interrupt disable */
94     #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
95 dpavlin 14 #define ARM_FLAG_T 0x00000020 /* Thumb mode */
96 dpavlin 10
97     #define ARM_FLAG_MODE 0x0000001f
98     #define ARM_MODE_USR26 0x00
99     #define ARM_MODE_FIQ26 0x01
100     #define ARM_MODE_IRQ26 0x02
101     #define ARM_MODE_SVC26 0x03
102     #define ARM_MODE_USR32 0x10
103     #define ARM_MODE_FIQ32 0x11
104     #define ARM_MODE_IRQ32 0x12
105     #define ARM_MODE_SVC32 0x13
106     #define ARM_MODE_ABT32 0x17
107     #define ARM_MODE_UND32 0x1b
108 dpavlin 14 #define ARM_MODE_SYS32 0x1f
109 dpavlin 10
110 dpavlin 14 #define ARM_EXCEPTION_TO_MODE { \
111     ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
112     ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
113 dpavlin 12
114 dpavlin 14 #define N_ARM_EXCEPTIONS 8
115    
116     #define ARM_EXCEPTION_RESET 0
117     #define ARM_EXCEPTION_UND 1
118     #define ARM_EXCEPTION_SWI 2
119     #define ARM_EXCEPTION_PREF_ABT 3
120     #define ARM_EXCEPTION_DATA_ABT 4
121     /* 5 was address exception in 26-bit ARM */
122     #define ARM_EXCEPTION_IRQ 6
123     #define ARM_EXCEPTION_FIQ 7
124    
125 dpavlin 28 DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t)
126 dpavlin 14
127 dpavlin 42 #define ARM_MAX_VPH_TLB_ENTRIES 384
128 dpavlin 12
129    
130 dpavlin 6 struct arm_cpu {
131 dpavlin 12 /*
132     * Misc.:
133     */
134 dpavlin 14 struct arm_cpu_type_def cpu_type;
135     uint32_t of_emul_addr;
136 dpavlin 10
137 dpavlin 14 void (*coproc[16])(struct cpu *, int opcode1,
138     int opcode2, int l_bit, int crn, int crm,
139     int rd);
140 dpavlin 12
141 dpavlin 10 /*
142     * General Purpose Registers (including the program counter):
143     *
144     * r[] always contains the current register set. The others are
145     * only used to swap to/from when changing modes. (An exception is
146     * r[0..7], which are never swapped out, they are always present.)
147     */
148 dpavlin 12
149 dpavlin 10 uint32_t r[N_ARM_REGS];
150 dpavlin 14
151     uint32_t default_r8_r14[7]; /* usr and sys */
152 dpavlin 10 uint32_t fiq_r8_r14[7];
153     uint32_t irq_r13_r14[2];
154     uint32_t svc_r13_r14[2];
155     uint32_t abt_r13_r14[2];
156     uint32_t und_r13_r14[2];
157    
158 dpavlin 14 uint32_t tmp_pc; /* Used for load/stores */
159 dpavlin 12
160 dpavlin 20 /*
161     * Flag/status registers:
162     *
163     * NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
164     * the flags should be copied from 'flags', and when cpsr is written
165     * to, 'flags' should be updated as well.
166     */
167     size_t flags;
168 dpavlin 14 uint32_t cpsr;
169     uint32_t spsr_svc;
170     uint32_t spsr_abt;
171     uint32_t spsr_und;
172     uint32_t spsr_irq;
173     uint32_t spsr_fiq;
174    
175    
176 dpavlin 10 /*
177 dpavlin 14 * System Control Coprocessor registers:
178     */
179 dpavlin 22 uint32_t cachetype; /* Cache Type Register */
180     uint32_t control; /* Control Register */
181     uint32_t auxctrl; /* Aux. Control Register */
182 dpavlin 14 uint32_t ttb; /* Translation Table Base */
183     uint32_t dacr; /* Domain Access Control */
184     uint32_t fsr; /* Fault Status Register */
185     uint32_t far; /* Fault Address Register */
186     uint32_t pid; /* Process Id Register */
187 dpavlin 22 uint32_t cpar; /* CoProcessor Access Reg. */
188 dpavlin 14
189 dpavlin 22 /* i80321 Coprocessor 6: ICU (Interrupt controller) */
190     uint32_t i80321_inten; /* enable */
191     uint32_t i80321_isteer;
192     uint32_t i80321_isrc; /* current assertions */
193     uint32_t tmr0;
194     uint32_t tmr1;
195 dpavlin 34 struct interrupt tmr0_irq;
196     struct interrupt tmr1_irq;
197 dpavlin 22 uint32_t tcr0;
198     uint32_t tcr1;
199     uint32_t trr0;
200     uint32_t trr1;
201     uint32_t tisr;
202     uint32_t wdtcr;
203    
204     /* XScale Coprocessor 14: (Performance Monitoring Unit) */
205     /* XSC1 access style: */
206     uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */
207     uint32_t xsc1_ccnt; /* Clock Counter */
208     uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */
209     uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */
210     /* XSC2 access style: */
211     uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */
212     uint32_t xsc2_ccnt; /* Clock Counter */
213     uint32_t xsc2_inten; /* Interrupt Enable */
214     uint32_t xsc2_flag; /* Overflow Flag Register */
215     uint32_t xsc2_evtsel; /* Event Selection Register */
216     uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */
217     uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */
218     uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */
219     uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */
220    
221 dpavlin 18 /* For caching the host address of the L1 translation table: */
222     unsigned char *translation_table;
223     uint32_t last_ttb;
224 dpavlin 14
225     /*
226     * Interrupts:
227     */
228     int irq_asserted;
229    
230    
231     /*
232 dpavlin 22 * Instruction translation cache, and 32-bit virtual -> physical ->
233     * host address translation:
234 dpavlin 10 */
235 dpavlin 22 DYNTRANS_ITC(arm)
236     VPH_TLBS(arm,ARM)
237 dpavlin 42 VPH32_16BITVPHENTRIES(arm,ARM)
238 dpavlin 10
239 dpavlin 18 /* ARM specific: */
240 dpavlin 22 uint32_t is_userpage[N_VPH32_ENTRIES/32];
241 dpavlin 6 };
242    
243    
244 dpavlin 14 /* System Control Coprocessor, control bits: */
245     #define ARM_CONTROL_MMU 0x0001
246     #define ARM_CONTROL_ALIGN 0x0002
247     #define ARM_CONTROL_CACHE 0x0004
248     #define ARM_CONTROL_WBUFFER 0x0008
249     #define ARM_CONTROL_PROG32 0x0010
250     #define ARM_CONTROL_DATA32 0x0020
251     #define ARM_CONTROL_BIG 0x0080
252     #define ARM_CONTROL_S 0x0100
253     #define ARM_CONTROL_R 0x0200
254     #define ARM_CONTROL_F 0x0400
255     #define ARM_CONTROL_Z 0x0800
256     #define ARM_CONTROL_ICACHE 0x1000
257     #define ARM_CONTROL_V 0x2000
258     #define ARM_CONTROL_RR 0x4000
259     #define ARM_CONTROL_L4 0x8000
260    
261 dpavlin 22 /* Auxiliary Control Register bits: */
262     #define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */
263     #define ARM_AUXCTRL_MD_SHIFT 4
264     #define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */
265     #define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */
266    
267     /* Cache Type register bits: */
268     #define ARM_CACHETYPE_CLASS 0x1e000000
269     #define ARM_CACHETYPE_CLASS_SHIFT 25
270     #define ARM_CACHETYPE_HARVARD 0x01000000
271     #define ARM_CACHETYPE_HARVARD_SHIFT 24
272     #define ARM_CACHETYPE_DSIZE 0x001c0000
273     #define ARM_CACHETYPE_DSIZE_SHIFT 18
274     #define ARM_CACHETYPE_DASSOC 0x00038000
275     #define ARM_CACHETYPE_DASSOC_SHIFT 15
276     #define ARM_CACHETYPE_DLINE 0x00003000
277     #define ARM_CACHETYPE_DLINE_SHIFT 12
278     #define ARM_CACHETYPE_ISIZE 0x000001c0
279     #define ARM_CACHETYPE_ISIZE_SHIFT 6
280     #define ARM_CACHETYPE_IASSOC 0x00000038
281     #define ARM_CACHETYPE_IASSOC_SHIFT 3
282     #define ARM_CACHETYPE_ILINE 0x00000003
283     #define ARM_CACHETYPE_ILINE_SHIFT 0
284    
285 dpavlin 6 /* cpu_arm.c: */
286 dpavlin 18 void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
287     void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
288     uint32_t paddr);
289     void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
290     uint32_t paddr);
291 dpavlin 14 void arm_exception(struct cpu *, int);
292 dpavlin 28 int arm_run_instr(struct cpu *cpu);
293 dpavlin 42 void arm_timer_sample_tick(struct timer *, void *);
294 dpavlin 12 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
295     unsigned char *host_page, int writeflag, uint64_t paddr_page);
296 dpavlin 18 void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
297 dpavlin 14 void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
298     void arm_load_register_bank(struct cpu *cpu);
299     void arm_save_register_bank(struct cpu *cpu);
300 dpavlin 6 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
301     unsigned char *data, size_t len, int writeflag, int cache_flags);
302     int arm_cpu_family_init(struct cpu_family *);
303    
304 dpavlin 14 /* cpu_arm_coproc.c: */
305     void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
306     int crn, int crm, int rd);
307 dpavlin 22 void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
308 dpavlin 14 int crn, int crm, int rd);
309 dpavlin 22 void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
310 dpavlin 14 int crn, int crm, int rd);
311 dpavlin 6
312 dpavlin 14 /* memory_arm.c: */
313 dpavlin 26 int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
314 dpavlin 14 uint64_t *return_addr, int flags);
315 dpavlin 26 int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
316 dpavlin 18 uint64_t *return_addr, int flags);
317 dpavlin 14
318 dpavlin 6 #endif /* CPU_ARM_H */
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