/[gxemul]/trunk/src/include/cpu_arm.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Revision 34 - (hide annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 10596 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 dpavlin 6 #ifndef CPU_ARM_H
2     #define CPU_ARM_H
3    
4     /*
5 dpavlin 34 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 dpavlin 6 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 34 * $Id: cpu_arm.h,v 1.70 2007/02/05 16:49:21 debug Exp $
32 dpavlin 6 */
33    
34     #include "misc.h"
35 dpavlin 34 #include "interrupt.h"
36 dpavlin 6
37     struct cpu_family;
38    
39 dpavlin 14 /* ARM CPU types: */
40     struct arm_cpu_type_def {
41     char *name;
42     uint32_t cpu_id;
43     int flags;
44     int icache_shift;
45     int iway;
46     int dcache_shift;
47     int dway;
48     };
49    
50    
51 dpavlin 10 #define ARM_SL 10
52     #define ARM_FP 11
53     #define ARM_IP 12
54     #define ARM_SP 13
55     #define ARM_LR 14
56     #define ARM_PC 15
57     #define N_ARM_REGS 16
58    
59 dpavlin 12 #define ARM_REG_NAMES { \
60     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61     "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62 dpavlin 10
63 dpavlin 12 #define ARM_CONDITION_STRINGS { \
64     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65     "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
66    
67     /* Names of Data Processing Instructions: */
68     #define ARM_DPI_NAMES { \
69     "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70     "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71    
72 dpavlin 22 #ifdef ONEKPAGE
73     #define ARM_IC_ENTRIES_SHIFT 8
74     #else
75     #define ARM_IC_ENTRIES_SHIFT 10
76     #endif
77    
78 dpavlin 12 #define ARM_N_IC_ARGS 3
79     #define ARM_INSTR_ALIGNMENT_SHIFT 2
80     #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
81     #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82     & (ARM_IC_ENTRIES_PER_PAGE-1))
83     #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
84     + ARM_INSTR_ALIGNMENT_SHIFT))
85    
86 dpavlin 20 #define ARM_F_N 8 /* Same as ARM_FLAG_*, but */
87     #define ARM_F_Z 4 /* for the 'flags' field instead */
88     #define ARM_F_C 2 /* of cpsr. */
89     #define ARM_F_V 1
90    
91 dpavlin 10 #define ARM_FLAG_N 0x80000000 /* Negative flag */
92     #define ARM_FLAG_Z 0x40000000 /* Zero flag */
93     #define ARM_FLAG_C 0x20000000 /* Carry flag */
94     #define ARM_FLAG_V 0x10000000 /* Overflow flag */
95 dpavlin 14 #define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
96 dpavlin 10 #define ARM_FLAG_I 0x00000080 /* Interrupt disable */
97     #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
98 dpavlin 14 #define ARM_FLAG_T 0x00000020 /* Thumb mode */
99 dpavlin 10
100     #define ARM_FLAG_MODE 0x0000001f
101     #define ARM_MODE_USR26 0x00
102     #define ARM_MODE_FIQ26 0x01
103     #define ARM_MODE_IRQ26 0x02
104     #define ARM_MODE_SVC26 0x03
105     #define ARM_MODE_USR32 0x10
106     #define ARM_MODE_FIQ32 0x11
107     #define ARM_MODE_IRQ32 0x12
108     #define ARM_MODE_SVC32 0x13
109     #define ARM_MODE_ABT32 0x17
110     #define ARM_MODE_UND32 0x1b
111 dpavlin 14 #define ARM_MODE_SYS32 0x1f
112 dpavlin 10
113 dpavlin 14 #define ARM_EXCEPTION_TO_MODE { \
114     ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
115     ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
116 dpavlin 12
117 dpavlin 14 #define N_ARM_EXCEPTIONS 8
118    
119     #define ARM_EXCEPTION_RESET 0
120     #define ARM_EXCEPTION_UND 1
121     #define ARM_EXCEPTION_SWI 2
122     #define ARM_EXCEPTION_PREF_ABT 3
123     #define ARM_EXCEPTION_DATA_ABT 4
124     /* 5 was address exception in 26-bit ARM */
125     #define ARM_EXCEPTION_IRQ 6
126     #define ARM_EXCEPTION_FIQ 7
127    
128 dpavlin 28 DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t)
129 dpavlin 14
130 dpavlin 18 #define ARM_MAX_VPH_TLB_ENTRIES 128
131 dpavlin 12
132    
133 dpavlin 6 struct arm_cpu {
134 dpavlin 12 /*
135     * Misc.:
136     */
137 dpavlin 14 struct arm_cpu_type_def cpu_type;
138     uint32_t of_emul_addr;
139 dpavlin 10
140 dpavlin 14 void (*coproc[16])(struct cpu *, int opcode1,
141     int opcode2, int l_bit, int crn, int crm,
142     int rd);
143 dpavlin 12
144 dpavlin 10 /*
145     * General Purpose Registers (including the program counter):
146     *
147     * r[] always contains the current register set. The others are
148     * only used to swap to/from when changing modes. (An exception is
149     * r[0..7], which are never swapped out, they are always present.)
150     */
151 dpavlin 12
152 dpavlin 10 uint32_t r[N_ARM_REGS];
153 dpavlin 14
154     uint32_t default_r8_r14[7]; /* usr and sys */
155 dpavlin 10 uint32_t fiq_r8_r14[7];
156     uint32_t irq_r13_r14[2];
157     uint32_t svc_r13_r14[2];
158     uint32_t abt_r13_r14[2];
159     uint32_t und_r13_r14[2];
160    
161 dpavlin 14 uint32_t tmp_pc; /* Used for load/stores */
162 dpavlin 12
163 dpavlin 20 /*
164     * Flag/status registers:
165     *
166     * NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
167     * the flags should be copied from 'flags', and when cpsr is written
168     * to, 'flags' should be updated as well.
169     */
170     size_t flags;
171 dpavlin 14 uint32_t cpsr;
172     uint32_t spsr_svc;
173     uint32_t spsr_abt;
174     uint32_t spsr_und;
175     uint32_t spsr_irq;
176     uint32_t spsr_fiq;
177    
178    
179 dpavlin 10 /*
180 dpavlin 14 * System Control Coprocessor registers:
181     */
182 dpavlin 22 uint32_t cachetype; /* Cache Type Register */
183     uint32_t control; /* Control Register */
184     uint32_t auxctrl; /* Aux. Control Register */
185 dpavlin 14 uint32_t ttb; /* Translation Table Base */
186     uint32_t dacr; /* Domain Access Control */
187     uint32_t fsr; /* Fault Status Register */
188     uint32_t far; /* Fault Address Register */
189     uint32_t pid; /* Process Id Register */
190 dpavlin 22 uint32_t cpar; /* CoProcessor Access Reg. */
191 dpavlin 14
192 dpavlin 22 /* i80321 Coprocessor 6: ICU (Interrupt controller) */
193     uint32_t i80321_inten; /* enable */
194     uint32_t i80321_isteer;
195     uint32_t i80321_isrc; /* current assertions */
196     uint32_t tmr0;
197     uint32_t tmr1;
198 dpavlin 34 struct interrupt tmr0_irq;
199     struct interrupt tmr1_irq;
200 dpavlin 22 uint32_t tcr0;
201     uint32_t tcr1;
202     uint32_t trr0;
203     uint32_t trr1;
204     uint32_t tisr;
205     uint32_t wdtcr;
206    
207     /* XScale Coprocessor 14: (Performance Monitoring Unit) */
208     /* XSC1 access style: */
209     uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */
210     uint32_t xsc1_ccnt; /* Clock Counter */
211     uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */
212     uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */
213     /* XSC2 access style: */
214     uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */
215     uint32_t xsc2_ccnt; /* Clock Counter */
216     uint32_t xsc2_inten; /* Interrupt Enable */
217     uint32_t xsc2_flag; /* Overflow Flag Register */
218     uint32_t xsc2_evtsel; /* Event Selection Register */
219     uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */
220     uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */
221     uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */
222     uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */
223    
224 dpavlin 18 /* For caching the host address of the L1 translation table: */
225     unsigned char *translation_table;
226     uint32_t last_ttb;
227 dpavlin 14
228     /*
229     * Interrupts:
230     */
231     int irq_asserted;
232    
233    
234     /*
235 dpavlin 22 * Instruction translation cache, and 32-bit virtual -> physical ->
236     * host address translation:
237 dpavlin 10 */
238 dpavlin 22 DYNTRANS_ITC(arm)
239     VPH_TLBS(arm,ARM)
240     VPH32(arm,ARM,uint32_t,uint8_t)
241 dpavlin 10
242 dpavlin 18 /* ARM specific: */
243 dpavlin 22 uint32_t is_userpage[N_VPH32_ENTRIES/32];
244 dpavlin 6 };
245    
246    
247 dpavlin 14 /* System Control Coprocessor, control bits: */
248     #define ARM_CONTROL_MMU 0x0001
249     #define ARM_CONTROL_ALIGN 0x0002
250     #define ARM_CONTROL_CACHE 0x0004
251     #define ARM_CONTROL_WBUFFER 0x0008
252     #define ARM_CONTROL_PROG32 0x0010
253     #define ARM_CONTROL_DATA32 0x0020
254     #define ARM_CONTROL_BIG 0x0080
255     #define ARM_CONTROL_S 0x0100
256     #define ARM_CONTROL_R 0x0200
257     #define ARM_CONTROL_F 0x0400
258     #define ARM_CONTROL_Z 0x0800
259     #define ARM_CONTROL_ICACHE 0x1000
260     #define ARM_CONTROL_V 0x2000
261     #define ARM_CONTROL_RR 0x4000
262     #define ARM_CONTROL_L4 0x8000
263    
264 dpavlin 22 /* Auxiliary Control Register bits: */
265     #define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */
266     #define ARM_AUXCTRL_MD_SHIFT 4
267     #define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */
268     #define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */
269    
270     /* Cache Type register bits: */
271     #define ARM_CACHETYPE_CLASS 0x1e000000
272     #define ARM_CACHETYPE_CLASS_SHIFT 25
273     #define ARM_CACHETYPE_HARVARD 0x01000000
274     #define ARM_CACHETYPE_HARVARD_SHIFT 24
275     #define ARM_CACHETYPE_DSIZE 0x001c0000
276     #define ARM_CACHETYPE_DSIZE_SHIFT 18
277     #define ARM_CACHETYPE_DASSOC 0x00038000
278     #define ARM_CACHETYPE_DASSOC_SHIFT 15
279     #define ARM_CACHETYPE_DLINE 0x00003000
280     #define ARM_CACHETYPE_DLINE_SHIFT 12
281     #define ARM_CACHETYPE_ISIZE 0x000001c0
282     #define ARM_CACHETYPE_ISIZE_SHIFT 6
283     #define ARM_CACHETYPE_IASSOC 0x00000038
284     #define ARM_CACHETYPE_IASSOC_SHIFT 3
285     #define ARM_CACHETYPE_ILINE 0x00000003
286     #define ARM_CACHETYPE_ILINE_SHIFT 0
287    
288 dpavlin 6 /* cpu_arm.c: */
289 dpavlin 18 void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
290     void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
291     uint32_t paddr);
292     void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
293     uint32_t paddr);
294 dpavlin 14 void arm_exception(struct cpu *, int);
295 dpavlin 28 int arm_run_instr(struct cpu *cpu);
296 dpavlin 12 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
297     unsigned char *host_page, int writeflag, uint64_t paddr_page);
298 dpavlin 18 void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
299 dpavlin 14 void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
300     void arm_load_register_bank(struct cpu *cpu);
301     void arm_save_register_bank(struct cpu *cpu);
302 dpavlin 6 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
303     unsigned char *data, size_t len, int writeflag, int cache_flags);
304     int arm_cpu_family_init(struct cpu_family *);
305    
306 dpavlin 14 /* cpu_arm_coproc.c: */
307     void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
308     int crn, int crm, int rd);
309 dpavlin 22 void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
310 dpavlin 14 int crn, int crm, int rd);
311 dpavlin 22 void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
312 dpavlin 14 int crn, int crm, int rd);
313 dpavlin 6
314 dpavlin 14 /* memory_arm.c: */
315 dpavlin 26 int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
316 dpavlin 14 uint64_t *return_addr, int flags);
317 dpavlin 26 int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
318 dpavlin 18 uint64_t *return_addr, int flags);
319 dpavlin 14
320 dpavlin 6 #endif /* CPU_ARM_H */
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