/[gxemul]/trunk/src/include/cpu_arm.h
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Mon Oct 8 16:19:37 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============
1 dpavlin 6 #ifndef CPU_ARM_H
2     #define CPU_ARM_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 6 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 22 * $Id: cpu_arm.h,v 1.65 2006/02/17 18:38:30 debug Exp $
32 dpavlin 6 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39 dpavlin 14 /* ARM CPU types: */
40     struct arm_cpu_type_def {
41     char *name;
42     uint32_t cpu_id;
43     int flags;
44     int icache_shift;
45     int iway;
46     int dcache_shift;
47     int dway;
48     };
49    
50    
51 dpavlin 10 #define ARM_SL 10
52     #define ARM_FP 11
53     #define ARM_IP 12
54     #define ARM_SP 13
55     #define ARM_LR 14
56     #define ARM_PC 15
57     #define N_ARM_REGS 16
58    
59 dpavlin 12 #define ARM_REG_NAMES { \
60     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61     "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62 dpavlin 10
63 dpavlin 12 #define ARM_CONDITION_STRINGS { \
64     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65     "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
66    
67     /* Names of Data Processing Instructions: */
68     #define ARM_DPI_NAMES { \
69     "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70     "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71    
72 dpavlin 22 #ifdef ONEKPAGE
73     #define ARM_IC_ENTRIES_SHIFT 8
74     #else
75     #define ARM_IC_ENTRIES_SHIFT 10
76     #endif
77    
78 dpavlin 12 #define ARM_N_IC_ARGS 3
79     #define ARM_INSTR_ALIGNMENT_SHIFT 2
80     #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
81     #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
82     & (ARM_IC_ENTRIES_PER_PAGE-1))
83     #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
84     + ARM_INSTR_ALIGNMENT_SHIFT))
85    
86 dpavlin 10 struct arm_instr_call {
87     void (*f)(struct cpu *, struct arm_instr_call *);
88 dpavlin 12 size_t arg[ARM_N_IC_ARGS];
89 dpavlin 10 };
90    
91 dpavlin 12 /* Translation cache struct for each physical page: */
92 dpavlin 10 struct arm_tc_physpage {
93 dpavlin 18 struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
94 dpavlin 10 uint32_t next_ofs; /* or 0 for end of chain */
95     uint32_t physaddr;
96     int flags;
97     };
98    
99    
100 dpavlin 20 #define ARM_F_N 8 /* Same as ARM_FLAG_*, but */
101     #define ARM_F_Z 4 /* for the 'flags' field instead */
102     #define ARM_F_C 2 /* of cpsr. */
103     #define ARM_F_V 1
104    
105 dpavlin 10 #define ARM_FLAG_N 0x80000000 /* Negative flag */
106     #define ARM_FLAG_Z 0x40000000 /* Zero flag */
107     #define ARM_FLAG_C 0x20000000 /* Carry flag */
108     #define ARM_FLAG_V 0x10000000 /* Overflow flag */
109 dpavlin 14 #define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
110 dpavlin 10 #define ARM_FLAG_I 0x00000080 /* Interrupt disable */
111     #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
112 dpavlin 14 #define ARM_FLAG_T 0x00000020 /* Thumb mode */
113 dpavlin 10
114     #define ARM_FLAG_MODE 0x0000001f
115     #define ARM_MODE_USR26 0x00
116     #define ARM_MODE_FIQ26 0x01
117     #define ARM_MODE_IRQ26 0x02
118     #define ARM_MODE_SVC26 0x03
119     #define ARM_MODE_USR32 0x10
120     #define ARM_MODE_FIQ32 0x11
121     #define ARM_MODE_IRQ32 0x12
122     #define ARM_MODE_SVC32 0x13
123     #define ARM_MODE_ABT32 0x17
124     #define ARM_MODE_UND32 0x1b
125 dpavlin 14 #define ARM_MODE_SYS32 0x1f
126 dpavlin 10
127 dpavlin 14 #define ARM_EXCEPTION_TO_MODE { \
128     ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
129     ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
130 dpavlin 12
131 dpavlin 14 #define N_ARM_EXCEPTIONS 8
132    
133     #define ARM_EXCEPTION_RESET 0
134     #define ARM_EXCEPTION_UND 1
135     #define ARM_EXCEPTION_SWI 2
136     #define ARM_EXCEPTION_PREF_ABT 3
137     #define ARM_EXCEPTION_DATA_ABT 4
138     /* 5 was address exception in 26-bit ARM */
139     #define ARM_EXCEPTION_IRQ 6
140     #define ARM_EXCEPTION_FIQ 7
141    
142    
143 dpavlin 18 #define ARM_MAX_VPH_TLB_ENTRIES 128
144 dpavlin 12 struct arm_vpg_tlb_entry {
145 dpavlin 20 unsigned char valid;
146     unsigned char writeflag;
147 dpavlin 12 uint32_t vaddr_page;
148     uint32_t paddr_page;
149 dpavlin 20 unsigned char *host_page;
150 dpavlin 12 };
151    
152    
153 dpavlin 6 struct arm_cpu {
154 dpavlin 12 /*
155     * Misc.:
156     */
157 dpavlin 14 struct arm_cpu_type_def cpu_type;
158     uint32_t of_emul_addr;
159 dpavlin 10
160 dpavlin 14 void (*coproc[16])(struct cpu *, int opcode1,
161     int opcode2, int l_bit, int crn, int crm,
162     int rd);
163 dpavlin 12
164 dpavlin 10 /*
165     * General Purpose Registers (including the program counter):
166     *
167     * r[] always contains the current register set. The others are
168     * only used to swap to/from when changing modes. (An exception is
169     * r[0..7], which are never swapped out, they are always present.)
170     */
171 dpavlin 12
172 dpavlin 10 uint32_t r[N_ARM_REGS];
173 dpavlin 14
174     uint32_t default_r8_r14[7]; /* usr and sys */
175 dpavlin 10 uint32_t fiq_r8_r14[7];
176     uint32_t irq_r13_r14[2];
177     uint32_t svc_r13_r14[2];
178     uint32_t abt_r13_r14[2];
179     uint32_t und_r13_r14[2];
180    
181 dpavlin 14 uint32_t tmp_pc; /* Used for load/stores */
182 dpavlin 12
183 dpavlin 20 /*
184     * Flag/status registers:
185     *
186     * NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
187     * the flags should be copied from 'flags', and when cpsr is written
188     * to, 'flags' should be updated as well.
189     */
190     size_t flags;
191 dpavlin 14 uint32_t cpsr;
192     uint32_t spsr_svc;
193     uint32_t spsr_abt;
194     uint32_t spsr_und;
195     uint32_t spsr_irq;
196     uint32_t spsr_fiq;
197    
198    
199 dpavlin 10 /*
200 dpavlin 14 * System Control Coprocessor registers:
201     */
202 dpavlin 22 uint32_t cachetype; /* Cache Type Register */
203     uint32_t control; /* Control Register */
204     uint32_t auxctrl; /* Aux. Control Register */
205 dpavlin 14 uint32_t ttb; /* Translation Table Base */
206     uint32_t dacr; /* Domain Access Control */
207     uint32_t fsr; /* Fault Status Register */
208     uint32_t far; /* Fault Address Register */
209     uint32_t pid; /* Process Id Register */
210 dpavlin 22 uint32_t cpar; /* CoProcessor Access Reg. */
211 dpavlin 14
212 dpavlin 22 /* i80321 Coprocessor 6: ICU (Interrupt controller) */
213     uint32_t i80321_inten; /* enable */
214     uint32_t i80321_isteer;
215     uint32_t i80321_isrc; /* current assertions */
216     uint32_t tmr0;
217     uint32_t tmr1;
218     uint32_t tcr0;
219     uint32_t tcr1;
220     uint32_t trr0;
221     uint32_t trr1;
222     uint32_t tisr;
223     uint32_t wdtcr;
224    
225     /* XScale Coprocessor 14: (Performance Monitoring Unit) */
226     /* XSC1 access style: */
227     uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */
228     uint32_t xsc1_ccnt; /* Clock Counter */
229     uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */
230     uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */
231     /* XSC2 access style: */
232     uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */
233     uint32_t xsc2_ccnt; /* Clock Counter */
234     uint32_t xsc2_inten; /* Interrupt Enable */
235     uint32_t xsc2_flag; /* Overflow Flag Register */
236     uint32_t xsc2_evtsel; /* Event Selection Register */
237     uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */
238     uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */
239     uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */
240     uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */
241    
242 dpavlin 18 /* For caching the host address of the L1 translation table: */
243     unsigned char *translation_table;
244     uint32_t last_ttb;
245 dpavlin 14
246     /*
247     * Interrupts:
248     */
249     int irq_asserted;
250    
251    
252     /*
253 dpavlin 22 * Instruction translation cache, and 32-bit virtual -> physical ->
254     * host address translation:
255 dpavlin 10 */
256 dpavlin 22 DYNTRANS_ITC(arm)
257     VPH_TLBS(arm,ARM)
258     VPH32(arm,ARM,uint32_t,uint8_t)
259 dpavlin 10
260 dpavlin 18 /* ARM specific: */
261 dpavlin 22 uint32_t is_userpage[N_VPH32_ENTRIES/32];
262 dpavlin 6 };
263    
264    
265 dpavlin 14 /* System Control Coprocessor, control bits: */
266     #define ARM_CONTROL_MMU 0x0001
267     #define ARM_CONTROL_ALIGN 0x0002
268     #define ARM_CONTROL_CACHE 0x0004
269     #define ARM_CONTROL_WBUFFER 0x0008
270     #define ARM_CONTROL_PROG32 0x0010
271     #define ARM_CONTROL_DATA32 0x0020
272     #define ARM_CONTROL_BIG 0x0080
273     #define ARM_CONTROL_S 0x0100
274     #define ARM_CONTROL_R 0x0200
275     #define ARM_CONTROL_F 0x0400
276     #define ARM_CONTROL_Z 0x0800
277     #define ARM_CONTROL_ICACHE 0x1000
278     #define ARM_CONTROL_V 0x2000
279     #define ARM_CONTROL_RR 0x4000
280     #define ARM_CONTROL_L4 0x8000
281    
282 dpavlin 22 /* Auxiliary Control Register bits: */
283     #define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */
284     #define ARM_AUXCTRL_MD_SHIFT 4
285     #define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */
286     #define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */
287    
288     /* Cache Type register bits: */
289     #define ARM_CACHETYPE_CLASS 0x1e000000
290     #define ARM_CACHETYPE_CLASS_SHIFT 25
291     #define ARM_CACHETYPE_HARVARD 0x01000000
292     #define ARM_CACHETYPE_HARVARD_SHIFT 24
293     #define ARM_CACHETYPE_DSIZE 0x001c0000
294     #define ARM_CACHETYPE_DSIZE_SHIFT 18
295     #define ARM_CACHETYPE_DASSOC 0x00038000
296     #define ARM_CACHETYPE_DASSOC_SHIFT 15
297     #define ARM_CACHETYPE_DLINE 0x00003000
298     #define ARM_CACHETYPE_DLINE_SHIFT 12
299     #define ARM_CACHETYPE_ISIZE 0x000001c0
300     #define ARM_CACHETYPE_ISIZE_SHIFT 6
301     #define ARM_CACHETYPE_IASSOC 0x00000038
302     #define ARM_CACHETYPE_IASSOC_SHIFT 3
303     #define ARM_CACHETYPE_ILINE 0x00000003
304     #define ARM_CACHETYPE_ILINE_SHIFT 0
305    
306 dpavlin 6 /* cpu_arm.c: */
307 dpavlin 18 void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
308     void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
309     uint32_t paddr);
310     void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
311     uint32_t paddr);
312 dpavlin 14 void arm_exception(struct cpu *, int);
313 dpavlin 12 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
314     unsigned char *host_page, int writeflag, uint64_t paddr_page);
315 dpavlin 18 void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
316 dpavlin 14 void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
317     void arm_load_register_bank(struct cpu *cpu);
318     void arm_save_register_bank(struct cpu *cpu);
319 dpavlin 6 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
320     unsigned char *data, size_t len, int writeflag, int cache_flags);
321     int arm_cpu_family_init(struct cpu_family *);
322    
323 dpavlin 14 /* cpu_arm_coproc.c: */
324     void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
325     int crn, int crm, int rd);
326 dpavlin 22 void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
327 dpavlin 14 int crn, int crm, int rd);
328 dpavlin 22 void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
329 dpavlin 14 int crn, int crm, int rd);
330 dpavlin 6
331 dpavlin 14 /* memory_arm.c: */
332     int arm_translate_address(struct cpu *cpu, uint64_t vaddr,
333     uint64_t *return_addr, int flags);
334 dpavlin 18 int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr,
335     uint64_t *return_addr, int flags);
336 dpavlin 14
337 dpavlin 6 #endif /* CPU_ARM_H */
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