/[gxemul]/trunk/src/include/cpu_arm.h
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Revision 14 - (hide annotations)
Mon Oct 8 16:18:51 2007 UTC (16 years, 7 months ago) by dpavlin
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File size: 8478 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.
1 dpavlin 6 #ifndef CPU_ARM_H
2     #define CPU_ARM_H
3    
4     /*
5     * Copyright (C) 2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 14 * $Id: cpu_arm.h,v 1.43 2005/10/07 22:10:53 debug Exp $
32 dpavlin 6 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39 dpavlin 14 /* ARM CPU types: */
40     struct arm_cpu_type_def {
41     char *name;
42     uint32_t cpu_id;
43     int flags;
44     int icache_shift;
45     int iway;
46     int dcache_shift;
47     int dway;
48     };
49    
50    
51 dpavlin 10 #define ARM_SL 10
52     #define ARM_FP 11
53     #define ARM_IP 12
54     #define ARM_SP 13
55     #define ARM_LR 14
56     #define ARM_PC 15
57     #define N_ARM_REGS 16
58    
59 dpavlin 12 #define ARM_REG_NAMES { \
60     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61     "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62 dpavlin 10
63 dpavlin 12 #define ARM_CONDITION_STRINGS { \
64     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65     "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
66    
67     /* Names of Data Processing Instructions: */
68     #define ARM_DPI_NAMES { \
69     "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70     "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71    
72     #define ARM_N_IC_ARGS 3
73     #define ARM_INSTR_ALIGNMENT_SHIFT 2
74     #define ARM_IC_ENTRIES_SHIFT 10
75     #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
76     #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
77     & (ARM_IC_ENTRIES_PER_PAGE-1))
78     #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
79     + ARM_INSTR_ALIGNMENT_SHIFT))
80    
81 dpavlin 10 struct arm_instr_call {
82     void (*f)(struct cpu *, struct arm_instr_call *);
83 dpavlin 12 size_t arg[ARM_N_IC_ARGS];
84 dpavlin 10 };
85    
86 dpavlin 12 /* Translation cache struct for each physical page: */
87 dpavlin 10 struct arm_tc_physpage {
88     uint32_t next_ofs; /* or 0 for end of chain */
89     uint32_t physaddr;
90     int flags;
91 dpavlin 12 struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1];
92 dpavlin 10 };
93    
94    
95     #define ARM_FLAG_N 0x80000000 /* Negative flag */
96     #define ARM_FLAG_Z 0x40000000 /* Zero flag */
97     #define ARM_FLAG_C 0x20000000 /* Carry flag */
98     #define ARM_FLAG_V 0x10000000 /* Overflow flag */
99 dpavlin 14 #define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
100 dpavlin 10 #define ARM_FLAG_I 0x00000080 /* Interrupt disable */
101     #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
102 dpavlin 14 #define ARM_FLAG_T 0x00000020 /* Thumb mode */
103 dpavlin 10
104     #define ARM_FLAG_MODE 0x0000001f
105     #define ARM_MODE_USR26 0x00
106     #define ARM_MODE_FIQ26 0x01
107     #define ARM_MODE_IRQ26 0x02
108     #define ARM_MODE_SVC26 0x03
109     #define ARM_MODE_USR32 0x10
110     #define ARM_MODE_FIQ32 0x11
111     #define ARM_MODE_IRQ32 0x12
112     #define ARM_MODE_SVC32 0x13
113     #define ARM_MODE_ABT32 0x17
114     #define ARM_MODE_UND32 0x1b
115 dpavlin 14 #define ARM_MODE_SYS32 0x1f
116 dpavlin 10
117 dpavlin 14 #define ARM_EXCEPTION_TO_MODE { \
118     ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
119     ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
120 dpavlin 12
121 dpavlin 14 #define N_ARM_EXCEPTIONS 8
122    
123     #define ARM_EXCEPTION_RESET 0
124     #define ARM_EXCEPTION_UND 1
125     #define ARM_EXCEPTION_SWI 2
126     #define ARM_EXCEPTION_PREF_ABT 3
127     #define ARM_EXCEPTION_DATA_ABT 4
128     /* 5 was address exception in 26-bit ARM */
129     #define ARM_EXCEPTION_IRQ 6
130     #define ARM_EXCEPTION_FIQ 7
131    
132    
133 dpavlin 12 #define ARM_N_VPH_ENTRIES 1048576
134    
135 dpavlin 14 #define ARM_MAX_VPH_TLB_ENTRIES 64
136 dpavlin 12 struct arm_vpg_tlb_entry {
137     int valid;
138     int writeflag;
139     int64_t timestamp;
140     unsigned char *host_page;
141     uint32_t vaddr_page;
142     uint32_t paddr_page;
143     };
144    
145    
146 dpavlin 6 struct arm_cpu {
147 dpavlin 12 /*
148     * Misc.:
149     */
150 dpavlin 14 struct arm_cpu_type_def cpu_type;
151     uint32_t of_emul_addr;
152 dpavlin 10
153 dpavlin 14 void (*coproc[16])(struct cpu *, int opcode1,
154     int opcode2, int l_bit, int crn, int crm,
155     int rd);
156 dpavlin 12
157 dpavlin 10 /*
158     * General Purpose Registers (including the program counter):
159     *
160     * r[] always contains the current register set. The others are
161     * only used to swap to/from when changing modes. (An exception is
162     * r[0..7], which are never swapped out, they are always present.)
163     */
164 dpavlin 12
165 dpavlin 10 uint32_t r[N_ARM_REGS];
166 dpavlin 14
167     uint32_t default_r8_r14[7]; /* usr and sys */
168 dpavlin 10 uint32_t fiq_r8_r14[7];
169     uint32_t irq_r13_r14[2];
170     uint32_t svc_r13_r14[2];
171     uint32_t abt_r13_r14[2];
172     uint32_t und_r13_r14[2];
173    
174 dpavlin 14 uint32_t tmp_pc; /* Used for load/stores */
175 dpavlin 12
176 dpavlin 14 /* Flag/status registers: */
177     uint32_t cpsr;
178     uint32_t spsr_svc;
179     uint32_t spsr_abt;
180     uint32_t spsr_und;
181     uint32_t spsr_irq;
182     uint32_t spsr_fiq;
183    
184    
185 dpavlin 10 /*
186 dpavlin 14 * System Control Coprocessor registers:
187     */
188     uint32_t control;
189     uint32_t ttb; /* Translation Table Base */
190     uint32_t dacr; /* Domain Access Control */
191     uint32_t fsr; /* Fault Status Register */
192     uint32_t far; /* Fault Address Register */
193     uint32_t pid; /* Process Id Register */
194    
195    
196     /*
197     * Interrupts:
198     */
199     int irq_asserted;
200    
201    
202     /*
203 dpavlin 10 * Instruction translation cache:
204     */
205    
206 dpavlin 12 /* cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE
207 dpavlin 10 instruction call entries. next_ic points to the next such
208     call to be executed. */
209     struct arm_tc_physpage *cur_physpage;
210     struct arm_instr_call *cur_ic_page;
211     struct arm_instr_call *next_ic;
212    
213 dpavlin 12
214     /*
215     * Virtual -> physical -> host address translation:
216     *
217     * host_load and host_store point to arrays of ARM_N_VPH_ENTRIES
218     * pointers (to host pages); phys_addr points to an array of
219     * ARM_N_VPH_ENTRIES uint32_t.
220     */
221    
222     struct arm_vpg_tlb_entry vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES];
223     unsigned char *host_load[ARM_N_VPH_ENTRIES];
224     unsigned char *host_store[ARM_N_VPH_ENTRIES];
225     uint32_t phys_addr[ARM_N_VPH_ENTRIES];
226     struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES];
227 dpavlin 6 };
228    
229    
230 dpavlin 14 /* System Control Coprocessor, control bits: */
231     #define ARM_CONTROL_MMU 0x0001
232     #define ARM_CONTROL_ALIGN 0x0002
233     #define ARM_CONTROL_CACHE 0x0004
234     #define ARM_CONTROL_WBUFFER 0x0008
235     #define ARM_CONTROL_PROG32 0x0010
236     #define ARM_CONTROL_DATA32 0x0020
237     #define ARM_CONTROL_BIG 0x0080
238     #define ARM_CONTROL_S 0x0100
239     #define ARM_CONTROL_R 0x0200
240     #define ARM_CONTROL_F 0x0400
241     #define ARM_CONTROL_Z 0x0800
242     #define ARM_CONTROL_ICACHE 0x1000
243     #define ARM_CONTROL_V 0x2000
244     #define ARM_CONTROL_RR 0x4000
245     #define ARM_CONTROL_L4 0x8000
246    
247 dpavlin 6 /* cpu_arm.c: */
248 dpavlin 14 void arm_exception(struct cpu *, int);
249 dpavlin 12 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
250     unsigned char *host_page, int writeflag, uint64_t paddr_page);
251 dpavlin 14 void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
252     void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
253     void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
254     void arm_load_register_bank(struct cpu *cpu);
255     void arm_save_register_bank(struct cpu *cpu);
256 dpavlin 6 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
257     unsigned char *data, size_t len, int writeflag, int cache_flags);
258     int arm_cpu_family_init(struct cpu_family *);
259    
260 dpavlin 14 /* cpu_arm_coproc.c: */
261     void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
262     int crn, int crm, int rd);
263     void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
264     int crn, int crm, int rd);
265     void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
266     int crn, int crm, int rd);
267 dpavlin 6
268 dpavlin 14 /* memory_arm.c: */
269     int arm_translate_address(struct cpu *cpu, uint64_t vaddr,
270     uint64_t *return_addr, int flags);
271    
272 dpavlin 6 #endif /* CPU_ARM_H */
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