/[gxemul]/trunk/src/include/cpu_alpha.h
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Contents of /trunk/src/include/cpu_alpha.h

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Revision 44 - (show annotations)
Mon Oct 8 16:22:56 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 5663 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1632 2007/09/11 21:46:35 debug Exp $
20070616	Implementing the MIPS32/64 revision 2 "ror" instruction.
20070617	Adding a struct for each physpage which keeps track of which
		ranges within that page (base offset, length) that are
		continuously translatable. When running with native code
		generation enabled (-b), a range is added after each read-
		ahead loop.
		Experimenting with using the physical program counter sample
		data (implemented 20070608) together with the "translatable
		range" information, to figure out which physical address ranges
		would be worth translating to native code (if the number of
		samples falling within a range is above a certain threshold).
20070618	Adding automagic building of .index comment files for
		src/file/, src/promemul/, src src/useremul/ as well.
		Adding a "has been translated" bit to the ranges, so that only
		not-yet-translated ranges will be sampled.
20070619	Moving src/cpu.c and src/memory_rw.c into src/cpus/,
		src/device.c into src/devices/, and src/machine.c into
		src/machines/.
		Creating a skeleton cc/ld native backend module; beginning on
		the function which will detect cc command line, etc.
20070620	Continuing on the native code generation infrastructure.
20070621	Moving src/x11.c and src/console.c into a new src/console/
		subdir (for everything that is console or framebuffer related).
		Moving src/symbol*.c into a new src/symbol/, which should
		contain anything that is symbol handling related.
20070624	Making the program counter sampling threshold a "settings
		variable" (sampling_threshold), i.e. it can now be changed
		during runtime.
		Switching the RELEASE notes format from plain text to HTML.
		If the TMPDIR environment variable is set, it is used instead
		of "/tmp" for temporary files.
		Continuing on the cc/ld backend: simple .c code is generated,
		the compiler and linker are called, etc.
		Adding detection of host architecture to the configure script
		(again), and adding icache invalidation support (only
		implemented for Alpha hosts so far).
20070625	Simplifying the program counter sampling mechanism.
20070626	Removing the cc/ld native code generation stuff, program
		counter sampling, etc; it would not have worked well in the
		general case.
20070627	Removing everything related to native code generation.
20070629	Removing the (practically unusable) support for multiple
		emulations. (The single emulation allowed now still supports
		multiple simultaneous machines, as before.)
		Beginning on PCCTWO and M88K interrupts.
20070723	Adding a dummy skeleton for emulation of M32R processors.
20070901	Fixing a warning found by "gcc version 4.3.0 20070817
		(experimental)" on amd64.
20070905	Removing some more traces of the old "multiple emulations"
		code.
		Also looking in /usr/local/include and /usr/local/lib for
		X11 libs, when running configure.
20070909	Minor updates to the guest OS install instructions, in
		preparation for the NetBSD 4.0 release.
20070918	More testing of NetBSD 4.0 RC1.
1 #ifndef CPU_ALPHA_H
2 #define CPU_ALPHA_H
3
4 /*
5 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu_alpha.h,v 1.49 2007/07/20 09:03:33 debug Exp $
32 */
33
34 #include "misc.h"
35
36 #include "alpha_cpu.h"
37
38
39 /* ALPHA CPU types: */
40 struct alpha_cpu_type_def {
41 char *name;
42 uint64_t pcs_type; /* See alpha_rpb.h */
43 int features;
44 int implver;
45 int icache_shift;
46 int ilinesize;
47 int iway;
48 int dcache_shift;
49 int dlinesize;
50 int dway;
51 int l2cache_shift;
52 int l2linesize;
53 int l2way;
54 };
55
56 /* TODO: More features */
57 #define ALPHA_FEATURE_BWX 1
58
59 #define ALPHA_CPU_TYPE_DEFS { \
60 { "21064", 0x000000002ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \
61 { "21066", 0x200000004ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \
62 { "21164", 0x000000005ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
63 { "21164A-2", 0x000000007ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
64 { "21164PC", 0x000000009ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
65 { "21264", 0x00000000dULL, 0, 2, 16,5,2, 16,5,2, 0,0,0 }, \
66 { "21364", 0x000000000ULL, 0, 3, 16,5,2, 16,5,2, 0,0,0 }, \
67 { NULL, 0x000000000ULL, 0, 0, 0,0,0, 0,0,0, 0,0,0 } }
68
69
70 struct cpu_family;
71
72 /* ALPHA_KENTRY_INT .. ALPHA_KENTRY_SYS */
73 #define N_ALPHA_KENTRY 6
74
75 #define ALPHA_V0 0
76 #define ALPHA_A0 16
77 #define ALPHA_A1 17
78 #define ALPHA_A2 18
79 #define ALPHA_A3 19
80 #define ALPHA_A4 20
81 #define ALPHA_A5 21
82 #define ALPHA_RA 26
83 #define ALPHA_T12 27
84 #define ALPHA_SP 30
85 #define ALPHA_ZERO 31
86 #define N_ALPHA_REGS 32
87
88 #define ALPHA_REG_NAMES { \
89 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
90 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
91 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
92 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
93
94
95 /* Dyntrans definitions: */
96
97 #define ALPHA_N_IC_ARGS 3
98 #define ALPHA_INSTR_ALIGNMENT_SHIFT 2
99 #define ALPHA_IC_ENTRIES_SHIFT 11
100 #define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
101 #define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
102 & (ALPHA_IC_ENTRIES_PER_PAGE-1))
103 #define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
104 + ALPHA_INSTR_ALIGNMENT_SHIFT))
105
106 #define ALPHA_MAX_VPH_TLB_ENTRIES 128
107
108 #define ALPHA_L2N 17
109 #define ALPHA_L3N 17
110
111 DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t)
112 DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t)
113
114
115 #define ALPHA_PAGESHIFT 13
116
117
118 struct alpha_cpu {
119 struct alpha_cpu_type_def cpu_type;
120
121
122 /*
123 * General Purpose Registers:
124 */
125
126 uint64_t r[N_ALPHA_REGS]; /* Integer */
127 uint64_t f[N_ALPHA_REGS]; /* Floating Point */
128
129 uint64_t fpcr; /* FP Control Reg. */
130
131 /* Misc.: */
132 uint64_t pcc; /* Cycle Counter */
133 uint64_t ipl;
134 uint64_t load_linked_addr;
135 int ll_flag;
136
137 int irq_asserted;
138
139 /* OSF1 PALcode specific: */
140 uint64_t vptptr; /* Virtual Page Table Ptr */
141 uint64_t sysvalue;
142 uint64_t kgp; /* Kernel GP */
143 uint64_t kentry[N_ALPHA_KENTRY];
144 uint64_t ctx; /* Ptr to current PCB (?) */
145 struct alpha_pcb pcb; /* Process Control Block */
146
147
148 /*
149 * Instruction translation cache and Virtual->Physical->Host
150 * address translation:
151 */
152 DYNTRANS_ITC(alpha)
153 VPH_TLBS(alpha,ALPHA)
154 VPH64(alpha,ALPHA)
155 };
156
157
158 /* cpu_alpha.c: */
159 void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
160 unsigned char *host_page, int writeflag, uint64_t paddr_page);
161 void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
162 void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
163 void alpha_init_64bit_dummy_tables(struct cpu *cpu);
164 int alpha_run_instr(struct cpu *cpu);
165 int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
166 unsigned char *data, size_t len, int writeflag, int cache_flags);
167 int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem,
168 uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
169 int cache_flags);
170 int alpha_cpu_family_init(struct cpu_family *);
171
172 /* cpu_alpha_palcode.c: */
173 void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
174 void alpha_palcode(struct cpu *cpu, uint32_t palcode);
175
176 /* memory_alpha.c: */
177 int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
178 uint64_t *return_addr, int flags);
179
180
181 #endif /* CPU_ALPHA_H */
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