Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $ 20050816 Some success in decoding the way the SGI O2 PROM draws graphics during bootup; lines/rectangles and bitmaps work, enough to show the bootlogo etc. :-) Adding more PPC instructions, and (dummy) BAT registers. 20050817 Updating the pckbc to support scancode type 3 keyboards (required in order to interact with the SGI O2 PROM). Adding more PPC instructions. 20050818 Adding more ARM instructions; general register forms. Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy) CATS machine mode (using SA110 as the default CPU). Continuing on general dyntrans related stuff. 20050819 Register forms for ARM load/stores. Gaah! The Compaq C Compiler bug is triggered for ARM loads as well, not just PPC :-( Adding full support for ARM PC-relative load/stores, and load/ stores where the PC register is the destination register. Adding support for ARM a.out binaries. 20050820 Continuing to add more ARM instructions, and correcting some bugs. Continuing on CATS emulation. More work on the PPC stuff. 20050821 Minor PPC and ARM updates. Adding more machine types. 20050822 All ARM "data processing instructions" are now generated automatically. 20050824 Beginning the work on the ARM system control coprocessor. Adding support for ARM halfword load/stores, and signed loads. 20050825 Fixing an important bug related to the ARM condition codes. OpenBSD/zaurus and NetBSD/netwinder now print some boot messages. :) Adding a dummy SH (Hitachi SuperH) cpu family. Beginning to add some ARM virtual address translation. MIPS bugfixes: unaligned PC now cause an ADEL exception (at least for non-bintrans execution), and ADEL/ADES (not TLBL/TLBS) are used if userland tries to access kernel space. (Thanks to Joshua Wise for making me aware of these bugs.) 20050827 More work on the ARM emulation, and various other updates. 20050828 More ARM updates. Finally taking the time to work on translation invalidation (i.e. invalidating translated code mappings when memory is written to). Hopefully this doesn't break anything. 20050829 Moving CPU related files from src/ to a new subdir, src/cpus/. Moving PROM emulation stuff from src/ to src/promemul/. Better debug instruction trace for ARM loads and stores. 20050830 Various ARM updates (correcting CMP flag calculation, etc). 20050831 PPC instruction updates. (Flag fixes, etc.) 20050901 Various minor PPC and ARM instruction emulation updates. Minor OpenFirmware emulation updates. 20050903 Adding support for adding arbitrary ARM coprocessors (with the i80321 I/O coprocessor as a first test). Various other ARM and PPC updates. 20050904 Adding some SHcompact disassembly routines. 20050907 (Re)adding a dummy HPPA CPU module, and a dummy i960 module. 20050908 Began hacking on some Apple Partition Table support. 20050909 Adding support for loading Mach-O (Darwin PPC) binaries. 20050910 Fixing an ARM bug (Carry flag was incorrectly updated for some data processing instructions); OpenBSD/cats and NetBSD/ netwinder get quite a bit further now. Applying a patch to dev_wdc, and a one-liner to dev_pcic, to make them work better when emulating new versions of OpenBSD. (Thanks to Alexander Yurchenko for the patches.) Also doing some other minor updates to dev_wdc. (Some cleanup, and finally converting to devinit, etc.) 20050912 IRIX doesn't have u_int64_t by default (noticed by Andreas <avr@gnulinux.nl>); configure updated to reflect this. Working on ARM register bank switching, CPSR vs SPSR issues, and beginning the work on interrupt/exception support. 20050913 Various minor ARM updates (speeding up load/store multiple, and fixing a ROR bug in R(); NetBSD/cats now boots as far as OpenBSD/cats). 20050917 Adding a dummy Atmel AVR (8-bit) cpu family skeleton. 20050918 Various minor updates. 20050919 Symbols are now loaded from Mach-O executables. Continuing the work on adding ARM exception support. 20050920 More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach userland! :-) 20050921 Some more progress on ARM interrupt specifics. 20050923 Fixing linesize for VR4121 (patch by Yurchenko). Also fixing linesizes/cachesizes for some other VR4xxx. Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a dummy Symphony Labs 83C553 bridge (for Netwinder), usable by dev_footbridge. 20050924 Some PPC progress. 20050925 More PPC progress. 20050926 PPC progress (fixing some bugs etc); Darwin's kernel gets slightly further than before. 20050928 Various updates: footbridge/ISA/pciide stuff, and finally fixing the VGA text scroll-by-changing-the-base-offset bug. 20050930 Adding a dummy S3 ViRGE pci card for CATS emulation, which both NetBSD and OpenBSD detects as VGA. Continuing on Footbridge (timers, ISA interrupt stuff). 20051001 Continuing... there are still bugs, probably interrupt- related. 20051002 More work on the Footbridge (interrupt stuff). 20051003 Various minor updates. (Trying to find the bug(s).) 20051004 Continuing on the ARM stuff. 20051005 More ARM-related fixes. 20051007 FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the other was because of an error in the ARM manual (load multiple with the S-bit set should _NOT_ load usermode registers, as the manual says, but it should load saved registers, which may or may not happen to be usermode registers). NetBSD/cats and OpenBSD/cats seem to install fine now :-) except for a minor bug at the end of the OpenBSD/cats install. Updating the documentation, preparing for the next release. 20051008 Continuing with release testing and cleanup.
1 | #ifndef CPU_ALPHA_H |
2 | #define CPU_ALPHA_H |
3 | |
4 | /* |
5 | * Copyright (C) 2005 Anders Gavare. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions are met: |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * |
31 | * $Id: cpu_alpha.h,v 1.23 2005/08/28 20:16:24 debug Exp $ |
32 | */ |
33 | |
34 | #include "misc.h" |
35 | |
36 | |
37 | struct cpu_family; |
38 | |
39 | #define ALPHA_V0 0 |
40 | #define ALPHA_A0 16 |
41 | #define ALPHA_A1 17 |
42 | #define ALPHA_A2 18 |
43 | #define ALPHA_A3 19 |
44 | #define ALPHA_A4 20 |
45 | #define ALPHA_A5 21 |
46 | #define ALPHA_RA 26 |
47 | #define ALPHA_T12 27 |
48 | #define ALPHA_SP 30 |
49 | #define ALPHA_ZERO 31 |
50 | #define N_ALPHA_REGS 32 |
51 | |
52 | #define ALPHA_REG_NAMES { \ |
53 | "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \ |
54 | "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \ |
55 | "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \ |
56 | "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" } |
57 | |
58 | |
59 | #define ALPHA_N_IC_ARGS 3 |
60 | #define ALPHA_INSTR_ALIGNMENT_SHIFT 2 |
61 | #define ALPHA_IC_ENTRIES_SHIFT 11 |
62 | #define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT) |
63 | #define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \ |
64 | & (ALPHA_IC_ENTRIES_PER_PAGE-1)) |
65 | #define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \ |
66 | + ALPHA_INSTR_ALIGNMENT_SHIFT)) |
67 | |
68 | struct alpha_instr_call { |
69 | void (*f)(struct cpu *, struct alpha_instr_call *); |
70 | size_t arg[ALPHA_N_IC_ARGS]; |
71 | }; |
72 | |
73 | /* Translation cache struct for each physical page: */ |
74 | struct alpha_tc_physpage { |
75 | uint32_t next_ofs; /* or 0 for end of chain */ |
76 | uint32_t physaddr; |
77 | int flags; |
78 | struct alpha_instr_call ics[ALPHA_IC_ENTRIES_PER_PAGE + 1]; |
79 | }; |
80 | |
81 | |
82 | /* |
83 | * Virtual->physical->host page entry: |
84 | * |
85 | * 13 + 13 + 13 bits = 39 bits (should be enough for most userspace |
86 | * applications) |
87 | * |
88 | * There is also an additional check for kernel space addresses. |
89 | */ |
90 | #define ALPHA_TOPSHIFT 39 |
91 | #define ALPHA_TOP_KERNEL 0x1fffff8 |
92 | #define ALPHA_LEVEL0_SHIFT 26 |
93 | #define ALPHA_LEVEL0 8192 |
94 | #define ALPHA_LEVEL1_SHIFT 13 |
95 | #define ALPHA_LEVEL1 8192 |
96 | struct alpha_vph_page { |
97 | void *host_load[ALPHA_LEVEL1]; |
98 | void *host_store[ALPHA_LEVEL1]; |
99 | uint64_t phys_addr[ALPHA_LEVEL1]; |
100 | struct alpha_tc_physpage *phys_page[ALPHA_LEVEL1]; |
101 | int refcount; |
102 | struct alpha_vph_page *next; /* Freelist, used if refcount = 0. */ |
103 | }; |
104 | |
105 | #define ALPHA_MAX_VPH_TLB_ENTRIES 128 |
106 | struct alpha_vpg_tlb_entry { |
107 | int valid; |
108 | int writeflag; |
109 | int64_t timestamp; |
110 | unsigned char *host_page; |
111 | uint64_t vaddr_page; |
112 | uint64_t paddr_page; |
113 | }; |
114 | |
115 | struct alpha_cpu { |
116 | /* |
117 | * General Purpose Registers: |
118 | */ |
119 | |
120 | uint64_t r[N_ALPHA_REGS]; /* Integer */ |
121 | uint64_t f[N_ALPHA_REGS]; /* Floating Point */ |
122 | |
123 | |
124 | /* Misc.: */ |
125 | uint64_t pcc; /* Cycle Counter */ |
126 | uint64_t ipl; |
127 | uint64_t load_linked_addr; |
128 | int ll_flag; |
129 | |
130 | |
131 | /* |
132 | * Instruction translation cache: |
133 | */ |
134 | |
135 | /* cur_ic_page is a pointer to an array of ALPHA_IC_ENTRIES_PER_PAGE |
136 | instruction call entries. next_ic points to the next such |
137 | call to be executed. */ |
138 | struct alpha_tc_physpage *cur_physpage; |
139 | struct alpha_instr_call *cur_ic_page; |
140 | struct alpha_instr_call *next_ic; |
141 | |
142 | |
143 | /* |
144 | * Virtual -> physical -> host address translation: |
145 | */ |
146 | |
147 | struct alpha_vpg_tlb_entry vph_tlb_entry[ALPHA_MAX_VPH_TLB_ENTRIES]; |
148 | struct alpha_vph_page *vph_default_page; |
149 | struct alpha_vph_page *vph_next_free_page; |
150 | struct alpha_vph_table *vph_next_free_table; |
151 | struct alpha_vph_page *vph_table0[ALPHA_LEVEL0]; |
152 | struct alpha_vph_page *vph_table0_kernel[ALPHA_LEVEL0]; |
153 | }; |
154 | |
155 | |
156 | /* cpu_alpha.c: */ |
157 | void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
158 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
159 | void alpha_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
160 | void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
161 | int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
162 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
163 | int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem, |
164 | uint64_t vaddr, unsigned char *data, size_t len, int writeflag, |
165 | int cache_flags); |
166 | int alpha_cpu_family_init(struct cpu_family *); |
167 | |
168 | /* cpu_alpha_palcode.c: */ |
169 | void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen); |
170 | void alpha_palcode(struct cpu *cpu, uint32_t palcode); |
171 | |
172 | |
173 | #endif /* CPU_ALPHA_H */ |
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