/[gxemul]/trunk/src/include/cpu_alpha.h
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Annotation of /trunk/src/include/cpu_alpha.h

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Revision 28 - (hide annotations)
Mon Oct 8 16:20:26 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 5052 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1298 2006/07/22 11:27:46 debug Exp $
20060626	Continuing on SPARC emulation (beginning on the 'save'
		instruction, register windows, etc).
20060629	Planning statistics gathering (new -s command line option),
		and renaming speed_tricks to allow_instruction_combinations.
20060630	Some minor manual page updates.
		Various cleanups.
		Implementing the -s command line option.
20060701	FINALLY found the bug which prevented Linux and Ultrix from
		running without the ugly hack in the R2000/R3000 cache isol
		code; it was the phystranslation hint array which was buggy.
		Removing the phystranslation hint code completely, for now.
20060702	Minor dyntrans cleanups; invalidation of physpages now only
		invalidate those parts of a page that have actually been
		translated. (32 parts per page.)
		Some MIPS non-R3000 speed fixes.
		Experimenting with MIPS instruction combination for some
		addiu+bne+sw loops, and sw+sw+sw.
		Adding support (again) for larger-than-4KB pages in MIPS tlbw*.
		Continuing on SPARC emulation: adding load/store instructions.
20060704	Fixing a virtual vs physical page shift bug in the new tlbw*
		implementation. Problem noticed by Jakub Jermar. (Many thanks.)
		Moving rfe and eret to cpu_mips_instr.c, since that is the
		only place that uses them nowadays.
20060705	Removing the BSD license from the "testmachine" include files,
		placing them in the public domain instead; this enables the
		testmachine stuff to be used from projects which are
		incompatible with the BSD license for some reason.
20060707	Adding instruction combinations for the R2000/R3000 L1
		I-cache invalidation code used by NetBSD/pmax 3.0, lui+addiu,
		various branches followed by addiu or nop, and jr ra followed
		by addiu. The time it takes to perform a full NetBSD/pmax R3000
		install on the laptop has dropped from 573 seconds to 539. :-)
20060708	Adding a framebuffer controller device (dev_fbctrl), which so
		far can be used to change the fb resolution during runtime, but
		in the future will also be useful for accelerated block fill/
		copy, and possibly also simplified character output.
		Adding an instruction combination for NetBSD/pmax' strlen.
20060709	Minor fixes: reading raw files in src/file.c wasn't memblock
		aligned, removing buggy multi_sw MIPS instruction combination,
		etc.
20060711	Adding a machine_qemu.c, which contains a "qemu_mips" machine.
		(It mimics QEMU's MIPS machine mode, so that a test kernel
		made for QEMU_MIPS also can run in GXemul... at least to some
		extent.)  Adding a short section about how to run this mode to
		doc/guestoses.html.
20060714	Misc. minor code cleanups.
20060715	Applying a patch which adds getchar() to promemul/yamon.c
		(from Oleksandr Tymoshenko).
		Adding yamon.h from NetBSD, and rewriting yamon.c to use it
		(instead of ugly hardcoded numbers) + some cleanup.
20060716	Found and fixed the bug which broke single-stepping of 64-bit
		programs between 0.4.0 and 0.4.0.1 (caused by too quick
		refactoring and no testing). Hopefully this fix will not
		break too many other things.
20060718	Continuing on the 8253 PIT; it now works with Linux/QEMU_MIPS.
		Re-adding the sw+sw+sw instr comb (the problem was that I had
		ignored endian issues); however, it doesn't seem to give any
		big performance gain.
20060720	Adding a dummy Transputer mode (T414, T800 etc) skeleton (only
		the 'j' and 'ldc' instructions are implemented so far). :-}
20060721	Adding gtreg.h from NetBSD, updating dev_gt.c to use it, plus
		misc. other updates to get Linux 2.6 for evbmips/malta working
		(thanks to Alec Voropay for the details).
		FINALLY found and fixed the bug which made tlbw* for non-R3000
		buggy; it was a reference count problem in the dyntrans core.
20060722	Testing stuff; things seem stable enough for a new release.

==============  RELEASE 0.4.1  ==============
1 dpavlin 12 #ifndef CPU_ALPHA_H
2     #define CPU_ALPHA_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 12 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 28 * $Id: cpu_alpha.h,v 1.39 2006/07/16 13:32:27 debug Exp $
32 dpavlin 12 */
33    
34     #include "misc.h"
35    
36    
37 dpavlin 24 /* ALPHA CPU types: */
38     struct alpha_cpu_type_def {
39     char *name;
40     int features;
41     int icache_shift;
42     int ilinesize;
43     int iway;
44     int dcache_shift;
45     int dlinesize;
46     int dway;
47     int l2cache_shift;
48     int l2linesize;
49     int l2way;
50     };
51    
52     /* TODO: More features */
53     #define ALPHA_FEATURE_BWX 1
54    
55     #define ALPHA_CPU_TYPE_DEFS { \
56     { "21064", 0, 16,5,2, 16,5,2, 0,0,0 }, \
57     { "21066", 0, 16,5,2, 16,5,2, 0,0,0 }, \
58     { "21164", 0, 16,5,2, 16,5,2, 0,0,0 }, \
59     { "21164A-2", 0, 16,5,2, 16,5,2, 0,0,0 }, \
60     { "21164PC", 0, 16,5,2, 16,5,2, 0,0,0 }, \
61     { "21264", 0, 16,5,2, 16,5,2, 0,0,0 }, \
62     { "21364", 0, 16,5,2, 16,5,2, 0,0,0 }, \
63     { NULL, 0, 0,0,0, 0,0,0, 0,0,0 } }
64    
65    
66 dpavlin 12 struct cpu_family;
67    
68     #define ALPHA_V0 0
69     #define ALPHA_A0 16
70     #define ALPHA_A1 17
71     #define ALPHA_A2 18
72     #define ALPHA_A3 19
73     #define ALPHA_A4 20
74     #define ALPHA_A5 21
75     #define ALPHA_RA 26
76     #define ALPHA_T12 27
77     #define ALPHA_SP 30
78     #define ALPHA_ZERO 31
79     #define N_ALPHA_REGS 32
80    
81     #define ALPHA_REG_NAMES { \
82     "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
83     "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
84     "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
85     "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
86    
87    
88     #define ALPHA_N_IC_ARGS 3
89     #define ALPHA_INSTR_ALIGNMENT_SHIFT 2
90     #define ALPHA_IC_ENTRIES_SHIFT 11
91     #define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
92     #define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
93     & (ALPHA_IC_ENTRIES_PER_PAGE-1))
94     #define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
95     + ALPHA_INSTR_ALIGNMENT_SHIFT))
96    
97 dpavlin 24 #define ALPHA_MAX_VPH_TLB_ENTRIES 128
98 dpavlin 12
99 dpavlin 24 #define ALPHA_L2N 17
100     #define ALPHA_L3N 17
101 dpavlin 12
102 dpavlin 24 DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t)
103     DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t)
104 dpavlin 12
105    
106     struct alpha_cpu {
107     /*
108     * General Purpose Registers:
109     */
110    
111     uint64_t r[N_ALPHA_REGS]; /* Integer */
112     uint64_t f[N_ALPHA_REGS]; /* Floating Point */
113    
114 dpavlin 24 uint64_t fpcr; /* FP Control Reg. */
115 dpavlin 12
116     /* Misc.: */
117     uint64_t pcc; /* Cycle Counter */
118     uint64_t ipl;
119     uint64_t load_linked_addr;
120     int ll_flag;
121    
122 dpavlin 24 /* PALcode specific: */
123     uint64_t wrvptptr;
124     uint64_t sysvalue;
125 dpavlin 12
126 dpavlin 24
127 dpavlin 12 /*
128 dpavlin 24 * Instruction translation cache and Virtual->Physical->Host
129     * address translation:
130 dpavlin 12 */
131 dpavlin 22 DYNTRANS_ITC(alpha)
132     VPH_TLBS(alpha,ALPHA)
133 dpavlin 24 VPH64(alpha,ALPHA,uint8_t)
134 dpavlin 12 };
135    
136    
137     /* cpu_alpha.c: */
138     void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
139     unsigned char *host_page, int writeflag, uint64_t paddr_page);
140 dpavlin 18 void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
141 dpavlin 14 void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
142 dpavlin 24 void alpha_init_64bit_dummy_tables(struct cpu *cpu);
143 dpavlin 28 int alpha_run_instr(struct cpu *cpu);
144 dpavlin 12 int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
145     unsigned char *data, size_t len, int writeflag, int cache_flags);
146     int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem,
147     uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
148     int cache_flags);
149     int alpha_cpu_family_init(struct cpu_family *);
150    
151     /* cpu_alpha_palcode.c: */
152     void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
153     void alpha_palcode(struct cpu *cpu, uint32_t palcode);
154    
155 dpavlin 24 /* memory_alpha.c: */
156 dpavlin 26 int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
157 dpavlin 24 uint64_t *return_addr, int flags);
158 dpavlin 12
159 dpavlin 28
160 dpavlin 12 #endif /* CPU_ALPHA_H */
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