src/include/cpu_alpha.h

#ifndef CPU_ALPHA_H
#define CPU_ALPHA_H

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_alpha.h,v 1.38 2006/06/24 21:47:23 debug Exp $
 */

#include "misc.h"


/*  ALPHA CPU types:  */
struct alpha_cpu_type_def { 
        char            *name;
        int             features;
        int             icache_shift;
        int             ilinesize;
        int             iway;
        int             dcache_shift;
        int             dlinesize;
        int             dway;
        int             l2cache_shift;
        int             l2linesize;
        int             l2way;
};

/*  TODO: More features  */
#define ALPHA_FEATURE_BWX               1

#define ALPHA_CPU_TYPE_DEFS     {                                       \
        { "21064",      0,       16,5,2, 16,5,2,  0,0,0 },              \
        { "21066",      0,       16,5,2, 16,5,2,  0,0,0 },              \
        { "21164",      0,       16,5,2, 16,5,2,  0,0,0 },              \
        { "21164A-2",   0,       16,5,2, 16,5,2,  0,0,0 },              \
        { "21164PC",    0,       16,5,2, 16,5,2,  0,0,0 },              \
        { "21264",      0,       16,5,2, 16,5,2,  0,0,0 },              \
        { "21364",      0,       16,5,2, 16,5,2,  0,0,0 },              \
        { NULL,         0,        0,0,0,  0,0,0,   0,0,0 }              }


struct cpu_family;

#define ALPHA_V0                0
#define ALPHA_A0                16
#define ALPHA_A1                17
#define ALPHA_A2                18
#define ALPHA_A3                19
#define ALPHA_A4                20
#define ALPHA_A5                21
#define ALPHA_RA                26
#define ALPHA_T12               27
#define ALPHA_SP                30
#define ALPHA_ZERO              31
#define N_ALPHA_REGS            32

#define ALPHA_REG_NAMES         {                               \
        "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",         \
        "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",         \
        "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",         \
        "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero"     }


#define ALPHA_N_IC_ARGS                 3
#define ALPHA_INSTR_ALIGNMENT_SHIFT     2
#define ALPHA_IC_ENTRIES_SHIFT          11
#define ALPHA_IC_ENTRIES_PER_PAGE       (1 << ALPHA_IC_ENTRIES_SHIFT)
#define ALPHA_PC_TO_IC_ENTRY(a)         (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
                                        & (ALPHA_IC_ENTRIES_PER_PAGE-1))
#define ALPHA_ADDR_TO_PAGENR(a)         ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
                                        + ALPHA_INSTR_ALIGNMENT_SHIFT))

#define ALPHA_MAX_VPH_TLB_ENTRIES       128

#define ALPHA_L2N               17
#define ALPHA_L3N               17

DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t)
DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t)


struct alpha_cpu {
        /*
         *  General Purpose Registers:
         */

        uint64_t                r[N_ALPHA_REGS];        /*  Integer  */
        uint64_t                f[N_ALPHA_REGS];        /*  Floating Point  */

        uint64_t                fpcr;                   /*  FP Control Reg.  */

        /*  Misc.:  */
        uint64_t                pcc;                    /*  Cycle Counter  */
        uint64_t                ipl;
        uint64_t                load_linked_addr;
        int                     ll_flag;

        /*  PALcode specific:  */
        uint64_t                wrvptptr;
        uint64_t                sysvalue;


        /*
         *  Instruction translation cache and Virtual->Physical->Host
         *  address translation:
         */
        DYNTRANS_ITC(alpha)
        VPH_TLBS(alpha,ALPHA)
        VPH64(alpha,ALPHA,uint8_t)
};


/*  cpu_alpha.c:  */
void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void alpha_init_64bit_dummy_tables(struct cpu *cpu);
int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem,
        uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
        int cache_flags);
int alpha_cpu_family_init(struct cpu_family *);

/*  cpu_alpha_palcode.c:  */
void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
void alpha_palcode(struct cpu *cpu, uint32_t palcode);

/*  memory_alpha.c:  */
int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);

#endif  /*  CPU_ALPHA_H  */
1	dpavlin	12	#ifndef CPU_ALPHA_H
2			#define CPU_ALPHA_H
3
4			/*
5	dpavlin	22	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6	dpavlin	12	*
7			* Redistribution and use in source and binary forms, with or without
8			* modification, are permitted provided that the following conditions are met:
9			*
10			* 1. Redistributions of source code must retain the above copyright
11			* notice, this list of conditions and the following disclaimer.
12			* 2. Redistributions in binary form must reproduce the above copyright
13			* notice, this list of conditions and the following disclaimer in the
14			* documentation and/or other materials provided with the distribution.
15			* 3. The name of the author may not be used to endorse or promote products
16			* derived from this software without specific prior written permission.
17			*
18			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28			* SUCH DAMAGE.
29			*
30			*
31	dpavlin	26	* $Id: cpu_alpha.h,v 1.38 2006/06/24 21:47:23 debug Exp $
32	dpavlin	12	*/
33
34			#include "misc.h"
35
36
37	dpavlin	24	/* ALPHA CPU types: */
38			struct alpha_cpu_type_def {
39			char *name;
40			int features;
41			int icache_shift;
42			int ilinesize;
43			int iway;
44			int dcache_shift;
45			int dlinesize;
46			int dway;
47			int l2cache_shift;
48			int l2linesize;
49			int l2way;
50			};
51
52			/* TODO: More features */
53			#define ALPHA_FEATURE_BWX 1
54
55			#define ALPHA_CPU_TYPE_DEFS { \
56			{ "21064", 0, 16,5,2, 16,5,2, 0,0,0 }, \
57			{ "21066", 0, 16,5,2, 16,5,2, 0,0,0 }, \
58			{ "21164", 0, 16,5,2, 16,5,2, 0,0,0 }, \
59			{ "21164A-2", 0, 16,5,2, 16,5,2, 0,0,0 }, \
60			{ "21164PC", 0, 16,5,2, 16,5,2, 0,0,0 }, \
61			{ "21264", 0, 16,5,2, 16,5,2, 0,0,0 }, \
62			{ "21364", 0, 16,5,2, 16,5,2, 0,0,0 }, \
63			{ NULL, 0, 0,0,0, 0,0,0, 0,0,0 } }
64
65
66	dpavlin	12	struct cpu_family;
67
68			#define ALPHA_V0 0
69			#define ALPHA_A0 16
70			#define ALPHA_A1 17
71			#define ALPHA_A2 18
72			#define ALPHA_A3 19
73			#define ALPHA_A4 20
74			#define ALPHA_A5 21
75			#define ALPHA_RA 26
76			#define ALPHA_T12 27
77			#define ALPHA_SP 30
78			#define ALPHA_ZERO 31
79			#define N_ALPHA_REGS 32
80
81			#define ALPHA_REG_NAMES { \
82			"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
83			"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
84			"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
85			"t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
86
87
88			#define ALPHA_N_IC_ARGS 3
89			#define ALPHA_INSTR_ALIGNMENT_SHIFT 2
90			#define ALPHA_IC_ENTRIES_SHIFT 11
91			#define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
92			#define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
93			& (ALPHA_IC_ENTRIES_PER_PAGE-1))
94			#define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
95			+ ALPHA_INSTR_ALIGNMENT_SHIFT))
96
97	dpavlin	24	#define ALPHA_MAX_VPH_TLB_ENTRIES 128
98	dpavlin	12
99	dpavlin	24	#define ALPHA_L2N 17
100			#define ALPHA_L3N 17
101	dpavlin	12
102	dpavlin	24	DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t)
103			DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t)
104	dpavlin	12
105
106			struct alpha_cpu {
107			/*
108			* General Purpose Registers:
109			*/
110
111			uint64_t r[N_ALPHA_REGS]; /* Integer */
112			uint64_t f[N_ALPHA_REGS]; /* Floating Point */
113
114	dpavlin	24	uint64_t fpcr; /* FP Control Reg. */
115	dpavlin	12
116			/* Misc.: */
117			uint64_t pcc; /* Cycle Counter */
118			uint64_t ipl;
119			uint64_t load_linked_addr;
120			int ll_flag;
121
122	dpavlin	24	/* PALcode specific: */
123			uint64_t wrvptptr;
124			uint64_t sysvalue;
125	dpavlin	12
126	dpavlin	24
127	dpavlin	12	/*
128	dpavlin	24	* Instruction translation cache and Virtual->Physical->Host
129			* address translation:
130	dpavlin	12	*/
131	dpavlin	22	DYNTRANS_ITC(alpha)
132			VPH_TLBS(alpha,ALPHA)
133	dpavlin	24	VPH64(alpha,ALPHA,uint8_t)
134	dpavlin	12	};
135
136
137			/* cpu_alpha.c: */
138			void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
139			unsigned char *host_page, int writeflag, uint64_t paddr_page);
140	dpavlin	18	void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
141	dpavlin	14	void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
142	dpavlin	24	void alpha_init_64bit_dummy_tables(struct cpu *cpu);
143	dpavlin	12	int alpha_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
144			unsigned char *data, size_t len, int writeflag, int cache_flags);
145			int alpha_userland_memory_rw(struct cpu cpu, struct memory mem,
146			uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
147			int cache_flags);
148			int alpha_cpu_family_init(struct cpu_family *);
149
150			/* cpu_alpha_palcode.c: */
151			void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
152			void alpha_palcode(struct cpu *cpu, uint32_t palcode);
153
154	dpavlin	24	/* memory_alpha.c: */
155	dpavlin	26	int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
156	dpavlin	24	uint64_t *return_addr, int flags);
157	dpavlin	12
158			#endif /* CPU_ALPHA_H */