/[gxemul]/trunk/src/include/cpu_alpha.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Annotation of /trunk/src/include/cpu_alpha.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 22 - (hide annotations)
Mon Oct 8 16:19:37 2007 UTC (11 years, 11 months ago) by dpavlin
File MIME type: text/plain
File size: 5318 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============


1 dpavlin 12 #ifndef CPU_ALPHA_H
2     #define CPU_ALPHA_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 12 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 22 * $Id: cpu_alpha.h,v 1.30 2006/02/09 22:40:27 debug Exp $
32 dpavlin 12 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39     #define ALPHA_V0 0
40     #define ALPHA_A0 16
41     #define ALPHA_A1 17
42     #define ALPHA_A2 18
43     #define ALPHA_A3 19
44     #define ALPHA_A4 20
45     #define ALPHA_A5 21
46     #define ALPHA_RA 26
47     #define ALPHA_T12 27
48     #define ALPHA_SP 30
49     #define ALPHA_ZERO 31
50     #define N_ALPHA_REGS 32
51    
52     #define ALPHA_REG_NAMES { \
53     "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
54     "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
55     "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
56     "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
57    
58    
59     #define ALPHA_N_IC_ARGS 3
60     #define ALPHA_INSTR_ALIGNMENT_SHIFT 2
61     #define ALPHA_IC_ENTRIES_SHIFT 11
62     #define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
63     #define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
64     & (ALPHA_IC_ENTRIES_PER_PAGE-1))
65     #define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
66     + ALPHA_INSTR_ALIGNMENT_SHIFT))
67    
68     struct alpha_instr_call {
69     void (*f)(struct cpu *, struct alpha_instr_call *);
70     size_t arg[ALPHA_N_IC_ARGS];
71     };
72    
73     /* Translation cache struct for each physical page: */
74     struct alpha_tc_physpage {
75 dpavlin 18 struct alpha_instr_call ics[ALPHA_IC_ENTRIES_PER_PAGE + 1];
76 dpavlin 12 uint32_t next_ofs; /* or 0 for end of chain */
77     uint32_t physaddr;
78     int flags;
79     };
80    
81    
82     /*
83     * Virtual->physical->host page entry:
84     *
85     * 13 + 13 + 13 bits = 39 bits (should be enough for most userspace
86     * applications)
87     *
88     * There is also an additional check for kernel space addresses.
89     */
90     #define ALPHA_TOPSHIFT 39
91     #define ALPHA_TOP_KERNEL 0x1fffff8
92     #define ALPHA_LEVEL0_SHIFT 26
93     #define ALPHA_LEVEL0 8192
94     #define ALPHA_LEVEL1_SHIFT 13
95     #define ALPHA_LEVEL1 8192
96     struct alpha_vph_page {
97     void *host_load[ALPHA_LEVEL1];
98     void *host_store[ALPHA_LEVEL1];
99     uint64_t phys_addr[ALPHA_LEVEL1];
100     struct alpha_tc_physpage *phys_page[ALPHA_LEVEL1];
101     int refcount;
102     struct alpha_vph_page *next; /* Freelist, used if refcount = 0. */
103     };
104    
105     #define ALPHA_MAX_VPH_TLB_ENTRIES 128
106     struct alpha_vpg_tlb_entry {
107 dpavlin 20 unsigned char valid;
108     unsigned char writeflag;
109 dpavlin 12 int64_t timestamp;
110     uint64_t vaddr_page;
111     uint64_t paddr_page;
112 dpavlin 20 unsigned char *host_page;
113 dpavlin 12 };
114    
115     struct alpha_cpu {
116     /*
117     * General Purpose Registers:
118     */
119    
120     uint64_t r[N_ALPHA_REGS]; /* Integer */
121     uint64_t f[N_ALPHA_REGS]; /* Floating Point */
122    
123    
124     /* Misc.: */
125     uint64_t pcc; /* Cycle Counter */
126     uint64_t ipl;
127 dpavlin 22 uint64_t sysvalue;
128 dpavlin 12 uint64_t load_linked_addr;
129     int ll_flag;
130    
131    
132     /*
133     * Instruction translation cache:
134     */
135 dpavlin 22 DYNTRANS_ITC(alpha)
136 dpavlin 12
137     /*
138 dpavlin 22 * Hardcoded Alpha virtual -> physical -> host address translation:
139 dpavlin 12 */
140 dpavlin 22 VPH_TLBS(alpha,ALPHA)
141 dpavlin 12 struct alpha_vph_page *vph_default_page;
142     struct alpha_vph_page *vph_next_free_page;
143     struct alpha_vph_table *vph_next_free_table;
144     struct alpha_vph_page *vph_table0[ALPHA_LEVEL0];
145     struct alpha_vph_page *vph_table0_kernel[ALPHA_LEVEL0];
146     };
147    
148    
149     /* cpu_alpha.c: */
150     void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
151     unsigned char *host_page, int writeflag, uint64_t paddr_page);
152 dpavlin 18 void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
153 dpavlin 14 void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
154 dpavlin 12 int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
155     unsigned char *data, size_t len, int writeflag, int cache_flags);
156     int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem,
157     uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
158     int cache_flags);
159     int alpha_cpu_family_init(struct cpu_family *);
160    
161     /* cpu_alpha_palcode.c: */
162     void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
163     void alpha_palcode(struct cpu *cpu, uint32_t palcode);
164    
165    
166     #endif /* CPU_ALPHA_H */

  ViewVC Help
Powered by ViewVC 1.1.26