/[gxemul]/trunk/src/include/cpu_alpha.h
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Annotation of /trunk/src/include/cpu_alpha.h

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Revision 18 - (hide annotations)
Mon Oct 8 16:19:11 2007 UTC (11 years, 11 months ago) by dpavlin
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File size: 5566 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============


1 dpavlin 12 #ifndef CPU_ALPHA_H
2     #define CPU_ALPHA_H
3    
4     /*
5     * Copyright (C) 2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 18 * $Id: cpu_alpha.h,v 1.25 2005/10/22 17:24:22 debug Exp $
32 dpavlin 12 */
33    
34     #include "misc.h"
35    
36    
37     struct cpu_family;
38    
39     #define ALPHA_V0 0
40     #define ALPHA_A0 16
41     #define ALPHA_A1 17
42     #define ALPHA_A2 18
43     #define ALPHA_A3 19
44     #define ALPHA_A4 20
45     #define ALPHA_A5 21
46     #define ALPHA_RA 26
47     #define ALPHA_T12 27
48     #define ALPHA_SP 30
49     #define ALPHA_ZERO 31
50     #define N_ALPHA_REGS 32
51    
52     #define ALPHA_REG_NAMES { \
53     "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
54     "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
55     "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
56     "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
57    
58    
59     #define ALPHA_N_IC_ARGS 3
60     #define ALPHA_INSTR_ALIGNMENT_SHIFT 2
61     #define ALPHA_IC_ENTRIES_SHIFT 11
62     #define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
63     #define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
64     & (ALPHA_IC_ENTRIES_PER_PAGE-1))
65     #define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
66     + ALPHA_INSTR_ALIGNMENT_SHIFT))
67    
68     struct alpha_instr_call {
69     void (*f)(struct cpu *, struct alpha_instr_call *);
70     size_t arg[ALPHA_N_IC_ARGS];
71     };
72    
73     /* Translation cache struct for each physical page: */
74     struct alpha_tc_physpage {
75 dpavlin 18 struct alpha_instr_call ics[ALPHA_IC_ENTRIES_PER_PAGE + 1];
76 dpavlin 12 uint32_t next_ofs; /* or 0 for end of chain */
77     uint32_t physaddr;
78     int flags;
79     };
80    
81    
82     /*
83     * Virtual->physical->host page entry:
84     *
85     * 13 + 13 + 13 bits = 39 bits (should be enough for most userspace
86     * applications)
87     *
88     * There is also an additional check for kernel space addresses.
89     */
90     #define ALPHA_TOPSHIFT 39
91     #define ALPHA_TOP_KERNEL 0x1fffff8
92     #define ALPHA_LEVEL0_SHIFT 26
93     #define ALPHA_LEVEL0 8192
94     #define ALPHA_LEVEL1_SHIFT 13
95     #define ALPHA_LEVEL1 8192
96     struct alpha_vph_page {
97     void *host_load[ALPHA_LEVEL1];
98     void *host_store[ALPHA_LEVEL1];
99     uint64_t phys_addr[ALPHA_LEVEL1];
100     struct alpha_tc_physpage *phys_page[ALPHA_LEVEL1];
101     int refcount;
102     struct alpha_vph_page *next; /* Freelist, used if refcount = 0. */
103     };
104    
105     #define ALPHA_MAX_VPH_TLB_ENTRIES 128
106     struct alpha_vpg_tlb_entry {
107     int valid;
108     int writeflag;
109     int64_t timestamp;
110     unsigned char *host_page;
111     uint64_t vaddr_page;
112     uint64_t paddr_page;
113     };
114    
115     struct alpha_cpu {
116     /*
117     * General Purpose Registers:
118     */
119    
120     uint64_t r[N_ALPHA_REGS]; /* Integer */
121     uint64_t f[N_ALPHA_REGS]; /* Floating Point */
122    
123    
124     /* Misc.: */
125     uint64_t pcc; /* Cycle Counter */
126     uint64_t ipl;
127     uint64_t load_linked_addr;
128     int ll_flag;
129    
130    
131     /*
132     * Instruction translation cache:
133     */
134    
135     /* cur_ic_page is a pointer to an array of ALPHA_IC_ENTRIES_PER_PAGE
136     instruction call entries. next_ic points to the next such
137     call to be executed. */
138     struct alpha_tc_physpage *cur_physpage;
139     struct alpha_instr_call *cur_ic_page;
140     struct alpha_instr_call *next_ic;
141    
142    
143     /*
144     * Virtual -> physical -> host address translation:
145     */
146    
147     struct alpha_vpg_tlb_entry vph_tlb_entry[ALPHA_MAX_VPH_TLB_ENTRIES];
148     struct alpha_vph_page *vph_default_page;
149     struct alpha_vph_page *vph_next_free_page;
150     struct alpha_vph_table *vph_next_free_table;
151     struct alpha_vph_page *vph_table0[ALPHA_LEVEL0];
152     struct alpha_vph_page *vph_table0_kernel[ALPHA_LEVEL0];
153     };
154    
155    
156     /* cpu_alpha.c: */
157     void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
158     unsigned char *host_page, int writeflag, uint64_t paddr_page);
159 dpavlin 18 void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
160 dpavlin 14 void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
161 dpavlin 12 int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
162     unsigned char *data, size_t len, int writeflag, int cache_flags);
163     int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem,
164     uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
165     int cache_flags);
166     int alpha_cpu_family_init(struct cpu_family *);
167    
168     /* cpu_alpha_palcode.c: */
169     void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
170     void alpha_palcode(struct cpu *cpu, uint32_t palcode);
171    
172    
173     #endif /* CPU_ALPHA_H */

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