--- trunk/src/include/cpu.h 2007/10/08 16:19:23 20 +++ trunk/src/include/cpu.h 2007/10/08 16:19:37 22 @@ -2,7 +2,7 @@ #define CPU_H /* - * Copyright (C) 2005 Anders Gavare. All rights reserved. + * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -28,9 +28,9 @@ * SUCH DAMAGE. * * - * $Id: cpu.h,v 1.54 2005/11/16 21:15:19 debug Exp $ + * $Id: cpu.h,v 1.62 2006/02/09 22:40:27 debug Exp $ * - * See cpu.c. + * CPU-related definitions. */ @@ -38,9 +38,117 @@ #include #include -/* This is needed for undefining 'mips' or 'ppc', on weird systems: */ +/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */ #include "../../config.h" +/* + * Dyntrans misc declarations, used throughout the dyntrans code. + */ +#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ + arch ## _instr_call { \ + void (*f)(struct cpu *, struct arch ## _instr_call *); \ + size_t arg[ARCH ## _N_IC_ARGS]; \ + }; \ + \ + /* Translation cache struct for each physical page: */ \ + struct arch ## _tc_physpage { \ + struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+1];\ + uint32_t next_ofs; /* (0 for end of chain) */ \ + int flags; \ + addrtype physaddr; \ + }; \ + \ + struct arch ## _vpg_tlb_entry { \ + uint8_t valid; \ + uint8_t writeflag; \ + addrtype vaddr_page; \ + addrtype paddr_page; \ + unsigned char *host_page; \ + int64_t timestamp; \ + }; + +/* + * Dyntrans "Instruction Translation Cache": + * + * cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to + * be the same as cur_ic_page, because all the instrcalls should be placed + * first in the physpage struct!) + * + * cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE + * instruction call entries. + * + * next_ic points to the next such instruction call to be executed. + * + * combination_check, when set to non-NULL, is executed automatically after + * an instruction has been translated. (It check for combinations of + * instructions; low_addr is the offset of the translated instruction in the + * current page, NOT shifted right.) + */ +#define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \ + struct arch ## _instr_call *cur_ic_page; \ + struct arch ## _instr_call *next_ic; \ + void (*combination_check)(struct cpu *, \ + struct arch ## _instr_call *, int low_addr); + +/* + * Virtual -> physical -> host address translation TLB entries: + * ------------------------------------------------------------ + * + * Regardless of whether 32-bit or 64-bit address translation is used, the + * same TLB entry structure is used. + */ +#define VPH_TLBS(arch,ARCH) \ + struct arch ## _vpg_tlb_entry \ + vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES]; + +/* + * 32-bit dyntrans emulated Virtual -> physical -> host address translation: + * ------------------------------------------------------------------------- + * + * This stuff assumes that 4 KB pages are used. 20 bits to select a page + * means just 1 M entries needed. This is small enough that a couple of + * full-size tables can fit in virtual memory on modern hosts (both 32-bit + * and 64-bit hosts). :-) + * + * Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t) + * or VPH32(sparc,SPARC,uint64_t,uint16_t) + * + * The vph_tlb_entry entries are cpu dependent tlb entries. + * + * The host_load and host_store entries point to host pages; the phys_addr + * entries are uint32_t or uint64_t (emulated physical addresses). + * + * phys_page points to translation cache physpages. + * + * phystranslation is a bitmap which tells us whether a physical page has + * a code translation. + * + * vaddr_to_tlbindex is a virtual address to tlb index hint table. + * The values in this array are the tlb index plus 1, so a value of, say, + * 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which + * is not a valid index. (I.e. no hit.) + */ +#define N_VPH32_ENTRIES 1048576 +#define VPH32(arch,ARCH,paddrtype,tlbindextype) \ + unsigned char *host_load[N_VPH32_ENTRIES]; \ + unsigned char *host_store[N_VPH32_ENTRIES]; \ + paddrtype phys_addr[N_VPH32_ENTRIES]; \ + struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ + uint32_t phystranslation[N_VPH32_ENTRIES/32]; \ + tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES]; + +/* + * 64-bit dyntrans emulated Virtual -> physical -> host address translation: + * ------------------------------------------------------------------------- + * + * Usage: e.g. VPH64(alpha,ALPHA,uint8_t) + * or VPH64(sparc,SPARC,uint16_t) + * + * TODO + */ +#define VPH64(arch,ARCH,tlbindextype) \ + int dummy; + #include "cpu_alpha.h" #include "cpu_arm.h" #include "cpu_avr.h" @@ -49,7 +157,6 @@ #include "cpu_ia64.h" #include "cpu_m68k.h" #include "cpu_mips.h" -#include "cpu_newmips.h" #include "cpu_ppc.h" #include "cpu_sh.h" #include "cpu_sparc.h" @@ -92,13 +199,9 @@ uint64_t f, int n_args); }; -#ifdef TRACE_NULL_CRASHES -#define TRACE_NULL_N_ENTRIES 16 -#endif - /* - * Dynamic translation definitions: + * More dyntrans stuff: * * The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets * into the cache, for possible translation cache structs for physical pages. @@ -108,13 +211,62 @@ #define TRANSLATIONS 1 #define COMBINATIONS 2 -#define DYNTRANS_CACHE_SIZE (20*1048576) +#define DYNTRANS_CACHE_SIZE (16*1048576) #define DYNTRANS_CACHE_MARGIN 300000 #define N_BASE_TABLE_ENTRIES 32768 #define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) +#ifdef DYNTRANS_BACKEND + +/* TODO: convert this into a fixed-size array? Might increase performace. */ +struct dtb_fixup { + struct dtb_fixup *next; + int type; /* Fixup type [optional] */ + void *addr; /* Address of the instruction + (in host memory) */ + size_t data; /* Emulation data. */ +}; + +struct translation_context { + /* Current address of where to emit host instructions: */ + /* (NULL means no translation is currently being done.) */ + void *p; + + /* index of the instr_call of the first translated instruction: */ + void *ic_page; + int start_instr_call_index; + + /* Fixups needed after first translation pass: */ + struct dtb_fixup *fixups; + + int n_simple; + + /* translation_buffer should have room for max_size bytes, + plus some margin. */ + unsigned char *translation_buffer; + size_t cur_size; +}; + +#define DTB_TRANSLATION_SIZE_MAX 3072 +#define DTB_TRANSLATION_SIZE_MARGIN 1024 + +void cpu_dtb_add_fixup(struct cpu *cpu, int type, void *addr, size_t data); +void cpu_dtb_do_fixups(struct cpu *cpu); + +void dtb_host_cacheinvalidate(void *p, size_t len); +int dtb_function_prologue(struct translation_context *ctx, size_t *sizep); +int dtb_function_epilogue(struct translation_context *ctx, size_t *sizep); +int dtb_generate_fcall(struct cpu *cpu, struct translation_context *ctx, + size_t *sizep, size_t f, size_t instr_call_ptr); +int dtb_generate_ptr_inc(struct cpu *cpu, struct translation_context *ctx, + size_t *sizep, void *ptr, int amount); + +#endif /* DYNTRANS_BACKEND */ + + + /* * The generic CPU struct: */ @@ -164,6 +316,9 @@ int n_translated_instrs; unsigned char *translation_cache; size_t translation_cache_cur_ofs; +#ifdef DYNTRANS_BACKEND + struct translation_context translation_context; +#endif /* * CPU-family dependent: @@ -177,7 +332,6 @@ struct ia64_cpu ia64; struct m68k_cpu m68k; struct mips_cpu mips; - struct newmips_cpu newmips; struct ppc_cpu ppc; struct sh_cpu sh; struct sparc_cpu sparc; @@ -216,6 +370,7 @@ #define INVALIDATE_ALL 2 #define INVALIDATE_PADDR 4 #define INVALIDATE_VADDR 8 +#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */ #define TLB_CODE 0x02 @@ -246,7 +401,7 @@ fp->register_match = n ## _cpu_register_match; \ fp->disassemble_instr = n ## _cpu_disassemble_instr; \ fp->register_dump = n ## _cpu_register_dump; \ - fp->run = n ## _cpu_run; \ + fp->run = n ## _OLD_cpu_run; \ fp->dumpinfo = n ## _cpu_dumpinfo; \ fp->show_full_statistics = n ## _cpu_show_full_statistics; \ fp->tlbdump = n ## _cpu_tlbdump; \