src/include/cpu.h

#ifndef CPU_H
#define CPU_H

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu.h,v 1.143 2007/08/29 20:36:49 debug Exp $
 *
 *  CPU-related definitions.
 */


#include <sys/types.h>
#include <inttypes.h>
#include <sys/time.h>

/*  This is needed for undefining 'mips', 'ppc' etc. on weird systems:  */
#include "../../config.h"

#include "timer.h"


/*
 *  Dyntrans misc declarations, used throughout the dyntrans code.
 *
 *  Note that there is space for all instruction calls within a page, and then
 *  two more. The first one of these "extra" instruction slots is the end-of-
 *  page slot. It transfers control to the first instruction slot on the next
 *  (virtual) page.
 *
 *  The second of these extra instruction slots is an additional end-of-page
 *  slot for delay-slot architectures. On e.g. MIPS, a branch instruction can
 *  "nullify" (skip) the delay-slot. If the end-of-page slot is skipped, then
 *  we end up one step after that. That's where the end_of_page2 slot is. :)
 *
 *  next_ofs points to the next page in a chain of possible pages. (Several
 *  pages can be in the same chain, but only one matches the specific physaddr.)
 *
 *  translations_bitmap is a tiny bitmap indicating which parts of the page have
 *  actual translations. Bit 0 corresponds to the lowest 1/32th of the page, bit
 *  1 to the second-lowest 1/32th, and so on. This speeds up page invalidations,
 *  since only part of the page need to be reset.
 *
 *  translation_ranges_ofs is an offset within the translation cache to a short
 *  list of ranges for this physpage which contain code. The list is of fixed
 *  length; to extend the list, the list should be made to point to another
 *  list, and so forth. (Bad, O(n) find/insert complexity. Should be fixed some
 *  day. TODO)  See definition of physpage_ranges below.
 */
#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype)  struct \
        arch ## _instr_call {                                   \
                void    (*f)(struct cpu *, struct arch ## _instr_call *); \
                size_t  arg[ARCH ## _N_IC_ARGS];                        \
        };                                                              \
                                                                        \
        /*  Translation cache struct for each physical page:  */        \
        struct arch ## _tc_physpage {                                   \
                struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\
                uint32_t        next_ofs;       /*  (0 for end of chain)  */ \
                uint32_t        translations_bitmap;                    \
                uint32_t        translation_ranges_ofs;                 \
                addrtype        physaddr;                               \
        };                                                              \
                                                                        \
        struct arch ## _vpg_tlb_entry {                                 \
                uint8_t         valid;                                  \
                uint8_t         writeflag;                              \
                addrtype        vaddr_page;                             \
                addrtype        paddr_page;                             \
                unsigned char   *host_page;                             \
        };

#define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype)            \
        struct arch ## _l3_64_table {                                   \
                unsigned char   *host_load[1 << ARCH ## _L3N];          \
                unsigned char   *host_store[1 << ARCH ## _L3N];         \
                uint64_t        phys_addr[1 << ARCH ## _L3N];           \
                tlbindextype    vaddr_to_tlbindex[1 << ARCH ## _L3N];   \
                struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \
                struct arch ## _l3_64_table     *next;                  \
                int             refcount;                               \
        };                                                              \
        struct arch ## _l2_64_table {                                   \
                struct arch ## _l3_64_table     *l3[1 << ARCH ## _L2N]; \
                struct arch ## _l2_64_table     *next;                  \
                int                             refcount;               \
        };


/*
 *  This structure contains a list of ranges within an emulated
 *  physical page that contain translatable code.
 */
#define PHYSPAGE_RANGES_ENTRIES_PER_LIST                20
struct physpage_ranges {
        uint32_t        next_ofs;       /*  0 for end of chain  */
        uint32_t        n_entries_used;
        uint16_t        base[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
        uint16_t        length[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
        uint16_t        count[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
};


/*
 *  Dyntrans "Instruction Translation Cache":
 *
 *  cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to
 *  be the same as cur_ic_page, because all the instrcalls should be placed
 *  first in the physpage struct!)
 *
 *  cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE
 *  instruction call entries.
 *
 *  next_ic points to the next such instruction call to be executed.
 *
 *  combination_check, when set to non-NULL, is executed automatically after
 *  an instruction has been translated. (It check for combinations of
 *  instructions; low_addr is the offset of the translated instruction in the
 *  current page, NOT shifted right.)
 */
#define DYNTRANS_ITC(arch)      struct arch ## _tc_physpage *cur_physpage;  \
                                struct arch ## _instr_call  *cur_ic_page;   \
                                struct arch ## _instr_call  *next_ic;       \
                                struct arch ## _tc_physpage *physpage_template;\
                                void (*combination_check)(struct cpu *,     \
                                    struct arch ## _instr_call *, int low_addr);

/*
 *  Virtual -> physical -> host address translation TLB entries:
 *  ------------------------------------------------------------
 *
 *  Regardless of whether 32-bit or 64-bit address translation is used, the
 *  same TLB entry structure is used.
 */
#define VPH_TLBS(arch,ARCH)                                             \
        struct arch ## _vpg_tlb_entry                                   \
            vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES];

/*
 *  32-bit dyntrans emulated Virtual -> physical -> host address translation:
 *  -------------------------------------------------------------------------
 *
 *  This stuff assumes that 4 KB pages are used. 20 bits to select a page
 *  means just 1 M entries needed. This is small enough that a couple of
 *  full-size tables can fit in virtual memory on modern hosts (both 32-bit
 *  and 64-bit hosts). :-)
 *
 *  Usage: e.g. VPH32(arm,ARM)
 *           or VPH32(sparc,SPARC)
 *
 *  The vph_tlb_entry entries are cpu dependent tlb entries.
 *
 *  The host_load and host_store entries point to host pages; the phys_addr
 *  entries are uint32_t (emulated physical addresses).
 *
 *  phys_page points to translation cache physpages.
 *
 *  vaddr_to_tlbindex is a virtual address to tlb index hint table.
 *  The values in this array are the tlb index plus 1, so a value of, say,
 *  3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
 *  is not a valid index. (I.e. no hit.)
 *
 *  The VPH32EXTENDED variant adds an additional postfix to the array
 *  names. Used so far only for usermode addresses in M88K emulation.
 */
#define N_VPH32_ENTRIES         1048576
#define VPH32(arch,ARCH)                                                \
        unsigned char           *host_load[N_VPH32_ENTRIES];            \
        unsigned char           *host_store[N_VPH32_ENTRIES];           \
        uint32_t                phys_addr[N_VPH32_ENTRIES];             \
        struct arch ## _tc_physpage  *phys_page[N_VPH32_ENTRIES];       \
        uint8_t                 vaddr_to_tlbindex[N_VPH32_ENTRIES];
#define VPH32_16BITVPHENTRIES(arch,ARCH)                                \
        unsigned char           *host_load[N_VPH32_ENTRIES];            \
        unsigned char           *host_store[N_VPH32_ENTRIES];           \
        uint32_t                phys_addr[N_VPH32_ENTRIES];             \
        struct arch ## _tc_physpage  *phys_page[N_VPH32_ENTRIES];       \
        uint16_t                vaddr_to_tlbindex[N_VPH32_ENTRIES];
#define VPH32EXTENDED(arch,ARCH,ex)                                     \
        unsigned char           *host_load_ ## ex[N_VPH32_ENTRIES];     \
        unsigned char           *host_store_ ## ex[N_VPH32_ENTRIES];    \
        uint32_t                phys_addr_ ## ex[N_VPH32_ENTRIES];      \
        struct arch ## _tc_physpage  *phys_page_ ## ex[N_VPH32_ENTRIES];\
        uint8_t                 vaddr_to_tlbindex_ ## ex[N_VPH32_ENTRIES];


/*
 *  64-bit dyntrans emulated Virtual -> physical -> host address translation:
 *  -------------------------------------------------------------------------
 *
 *  Usage: e.g. VPH64(alpha,ALPHA)
 *           or VPH64(sparc,SPARC)
 *
 *  l1_64 is an array containing poiners to l2 tables.
 *
 *  l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL
 *  pointers in l1_64 for unused slots, a pointer to the dummy table can be
 *  used.
 */
#define DYNTRANS_L1N            17
#define VPH64(arch,ARCH)                                                \
        struct arch ## _l3_64_table     *l3_64_dummy;                   \
        struct arch ## _l3_64_table     *next_free_l3;                  \
        struct arch ## _l2_64_table     *l2_64_dummy;                   \
        struct arch ## _l2_64_table     *next_free_l2;                  \
        struct arch ## _l2_64_table     *l1_64[1 << DYNTRANS_L1N];


/*  Include all CPUs' header files here:  */
#include "cpu_alpha.h"
#include "cpu_arm.h"
#include "cpu_m32r.h"
#include "cpu_m88k.h"
#include "cpu_mips.h"
#include "cpu_ppc.h"
#include "cpu_sh.h"
#include "cpu_sparc.h"

struct cpu;
struct emul;
struct machine;
struct memory;
struct settings;


/*
 *  cpu_family
 *  ----------
 *
 *  This structure consists of various pointers to functions, performing
 *  architecture-specific functions.
 *
 *  Except for the next and arch fields at the top, all fields in the
 *  cpu_family struct are filled in by ecah CPU family's init function.
 */
struct cpu_family {
        struct cpu_family       *next;
        int                     arch;

        /*  Familty name, e.g. "MIPS", "Alpha" etc.  */
        char                    *name;

        /*  Fill in architecture specific parts of a struct cpu.  */
        int                     (*cpu_new)(struct cpu *cpu, struct memory *mem,
                                    struct machine *machine,
                                    int cpu_id, char *cpu_type_name);

        /*  Initialize various translation tables.  */
        void                    (*init_tables)(struct cpu *cpu);

        /*  List available CPU types for this architecture.  */
        void                    (*list_available_types)(void);

        /*  Disassemble an instruction.  */
        int                     (*disassemble_instr)(struct cpu *cpu,
                                    unsigned char *instr, int running,
                                    uint64_t dumpaddr);

        /*  Dump CPU registers in readable format.  */
        void                    (*register_dump)(struct cpu *cpu,
                                    int gprs, int coprocs);

        /*  Dump generic CPU info in readable format.  */
        void                    (*dumpinfo)(struct cpu *cpu);

        /*  Dump TLB data for CPU id x.  */
        void                    (*tlbdump)(struct machine *m, int x,
                                    int rawflag);

        /*  Print architecture-specific function call arguments.
            (This is called for each function call, if running with -t.)  */
        void                    (*functioncall_trace)(struct cpu *,
                                    uint64_t f, int n_args);
};


/*
 *  More dyntrans stuff:
 *
 *  The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
 *  into the cache, for possible translation cache structs for physical pages.
 */

/*  Meaning of delay_slot:  */
#define NOT_DELAYED                     0
#define DELAYED                         1
#define TO_BE_DELAYED                   2
#define EXCEPTION_IN_DELAY_SLOT         8

#define N_SAFE_DYNTRANS_LIMIT_SHIFT     14
#define N_SAFE_DYNTRANS_LIMIT   ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)

#define MAX_DYNTRANS_READAHEAD          128

#define DEFAULT_DYNTRANS_CACHE_SIZE     (48*1048576)
#define DYNTRANS_CACHE_MARGIN           200000

#define N_BASE_TABLE_ENTRIES            65536
#define PAGENR_TO_TABLE_INDEX(a)        ((a) & (N_BASE_TABLE_ENTRIES-1))


/*
 *  The generic CPU struct:
 */

struct cpu {
        /*  Pointer back to the machine this CPU is in:  */
        struct machine  *machine;

        /*  Settings:  */
        struct settings *settings;

        /*  CPU-specific name, e.g. "R2000", "21164PC", etc.  */
        char            *name;

        /*  Full "path" to the CPU, e.g. "machine[0].cpu[0]":  */
        char            *path;

        /*  Nr of instructions executed, etc.:  */
        int64_t         ninstrs;
        int64_t         ninstrs_show;
        int64_t         ninstrs_flush;
        int64_t         ninstrs_since_gettimeofday;
        struct timeval  starttime;

        /*  EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN.  */
        uint8_t         byte_order;

        /*  0 for emulated 64-bit CPUs, 1 for 32-bit.  */
        uint8_t         is_32bit;

        /*  1 while running, 0 when paused/stopped.  */
        uint8_t         running;

        /*  See comment further up.  */
        uint8_t         delay_slot;

        /*  0-based CPU id, in an emulated SMP system.  */
        int             cpu_id;

        /*  A pointer to the main memory connected to this CPU.  */
        struct memory   *mem;

        int             (*run_instr)(struct cpu *cpu);
        int             (*memory_rw)(struct cpu *cpu,
                            struct memory *mem, uint64_t vaddr,
                            unsigned char *data, size_t len,
                            int writeflag, int cache_flags);
        int             (*translate_v2p)(struct cpu *, uint64_t vaddr,
                            uint64_t *return_paddr, int flags);
        void            (*update_translation_table)(struct cpu *,
                            uint64_t vaddr_page, unsigned char *host_page,
                            int writeflag, uint64_t paddr_page);
        void            (*invalidate_translation_caches)(struct cpu *,
                            uint64_t paddr, int flags);
        void            (*invalidate_code_translation)(struct cpu *,
                            uint64_t paddr, int flags);
        void            (*useremul_syscall)(struct cpu *cpu, uint32_t code);
        int             (*instruction_has_delayslot)(struct cpu *cpu,
                            unsigned char *ib);

        /*  The program counter. (For 32-bit modes, not all bits are used.)  */
        uint64_t        pc;

        /*  The current depth of function call tracing.  */
        int             trace_tree_depth;

        /*
         *  If is_halted is true when an interrupt trap occurs, the pointer
         *  to the next instruction to execute will be the instruction
         *  following the halt instruction, not the halt instrucion itself.
         *
         *  If has_been_idling is true when printing the number of executed
         *  instructions per second, "idling" is printed instead. (The number
         *  of instrs per second when idling is meaningless anyway.)
         */
        char            is_halted;
        char            has_been_idling;

        /*
         *  Dynamic translation:
         *
         *  The number of translated instructions is assumed to be 1 per
         *  instruction call. For each case where this differs from the
         *  truth, n_translated_instrs should be modified. E.g. if 1000
         *  instruction calls are done, and n_translated_instrs is 50, then
         *  1050 emulated instructions were actually executed.
         *
         *  Note that it can also be adjusted negatively, that is, the way
         *  to "get out" of a dyntrans loop is to set the current instruction
         *  call pointer to the "nothing" instruction. This instruction
         *  _decreases_ n_translated_instrs by 1. That way, once the dyntrans
         *  loop exits, only real instructions will be counted, and not the
         *  "nothing" instructions.
         *
         *  The translation cache is a relative large chunk of memory (say,
         *  32 MB) which is used for translations. When it has been used up,
         *  everything restarts from scratch.
         *
         *  translation_readahead is non-zero when translating instructions
         *  ahead of the current (emulated) instruction pointer.
         */

        int             translation_readahead;

        /*  Instruction translation cache:  */
        int             n_translated_instrs;
        unsigned char   *translation_cache;
        size_t          translation_cache_cur_ofs;


        /*
         *  CPU-family dependent:
         *
         *  These contain everything ranging from general purpose registers,
         *  control registers, memory management, status words, interrupt
         *  specifics, etc.
         */
        union {
                struct alpha_cpu      alpha;
                struct arm_cpu        arm;
                struct m32r_cpu       m32r;
                struct m88k_cpu       m88k;
                struct mips_cpu       mips;
                struct ppc_cpu        ppc;
                struct sh_cpu         sh;
                struct sparc_cpu      sparc;
        } cd;
};


/*  cpu.c:  */
struct cpu *cpu_new(struct memory *mem, struct machine *machine,
        int cpu_id, char *cpu_type_name);
void cpu_destroy(struct cpu *cpu);

void cpu_tlbdump(struct machine *m, int x, int rawflag);
void cpu_register_dump(struct machine *m, struct cpu *cpu,
        int gprs, int coprocs);
int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
        unsigned char *instr, int running, uint64_t addr);

void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
void cpu_functioncall_trace_return(struct cpu *cpu);

void cpu_create_or_reset_tc(struct cpu *cpu);

void cpu_run_init(struct machine *machine);
void cpu_run_deinit(struct machine *machine);

void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
void cpu_list_available_types(void);
void cpu_show_cycles(struct machine *machine, int forced);

struct cpu_family *cpu_family_ptr_by_number(int arch);
void cpu_init(void);


#define JUST_MARK_AS_NON_WRITABLE       1
#define INVALIDATE_ALL                  2
#define INVALIDATE_PADDR                4
#define INVALIDATE_VADDR                8
#define INVALIDATE_VADDR_UPPER4         16      /*  useful for PPC emulation  */


/*  Note: 64-bit processors running in 32-bit mode use a 32-bit
    display format, even though the underlying data is 64-bits.  */
#define CPU_SETTINGS_ADD_REGISTER64(name, var)                             \
        settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT64,         \
            cpu->is_32bit? SETTINGS_FORMAT_HEX32 : SETTINGS_FORMAT_HEX64,  \
            (void *) &(var));
#define CPU_SETTINGS_ADD_REGISTER32(name, var)                             \
        settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT32,         \
            SETTINGS_FORMAT_HEX32, (void *) &(var));
#define CPU_SETTINGS_ADD_REGISTER16(name, var)                             \
        settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT16,         \
            SETTINGS_FORMAT_HEX16, (void *) &(var));
#define CPU_SETTINGS_ADD_REGISTER8(name, var)                              \
        settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT8,          \
            SETTINGS_FORMAT_HEX8, (void *) &(var));


#define CPU_FAMILY_INIT(n,s)    int n ## _cpu_family_init(              \
        struct cpu_family *fp) {                                        \
        /*  Fill in the cpu_family struct with valid data for this arch.  */ \
        fp->name = s;                                                   \
        fp->cpu_new = n ## _cpu_new;                                    \
        fp->list_available_types = n ## _cpu_list_available_types;      \
        fp->disassemble_instr = n ## _cpu_disassemble_instr;            \
        fp->register_dump = n ## _cpu_register_dump;                    \
        fp->dumpinfo = n ## _cpu_dumpinfo;                              \
        fp->functioncall_trace = n ## _cpu_functioncall_trace;          \
        fp->tlbdump = n ## _cpu_tlbdump;                                \
        fp->init_tables = n ## _cpu_init_tables;                        \
        return 1;                                                       \
        }


#endif  /*  CPU_H  */
1	#ifndef CPU_H
2	#define CPU_H
3
4	/*
5	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu.h,v 1.143 2007/08/29 20:36:49 debug Exp $
32	*
33	* CPU-related definitions.
34	*/
35
36
37	#include <sys/types.h>
38	#include <inttypes.h>
39	#include <sys/time.h>
40
41	/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */
42	#include "../../config.h"
43
44	#include "timer.h"
45
46
47	/*
48	* Dyntrans misc declarations, used throughout the dyntrans code.
49	*
50	* Note that there is space for all instruction calls within a page, and then
51	* two more. The first one of these "extra" instruction slots is the end-of-
52	* page slot. It transfers control to the first instruction slot on the next
53	* (virtual) page.
54	*
55	* The second of these extra instruction slots is an additional end-of-page
56	* slot for delay-slot architectures. On e.g. MIPS, a branch instruction can
57	* "nullify" (skip) the delay-slot. If the end-of-page slot is skipped, then
58	* we end up one step after that. That's where the end_of_page2 slot is. :)
59	*
60	* next_ofs points to the next page in a chain of possible pages. (Several
61	* pages can be in the same chain, but only one matches the specific physaddr.)
62	*
63	* translations_bitmap is a tiny bitmap indicating which parts of the page have
64	* actual translations. Bit 0 corresponds to the lowest 1/32th of the page, bit
65	* 1 to the second-lowest 1/32th, and so on. This speeds up page invalidations,
66	* since only part of the page need to be reset.
67	*
68	* translation_ranges_ofs is an offset within the translation cache to a short
69	* list of ranges for this physpage which contain code. The list is of fixed
70	* length; to extend the list, the list should be made to point to another
71	* list, and so forth. (Bad, O(n) find/insert complexity. Should be fixed some
72	* day. TODO) See definition of physpage_ranges below.
73	*/
74	#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \
75	arch ## _instr_call { \
76	void (f)(struct cpu , struct arch ## _instr_call *); \
77	size_t arg[ARCH ## _N_IC_ARGS]; \
78	}; \
79	\
80	/* Translation cache struct for each physical page: */ \
81	struct arch ## _tc_physpage { \
82	struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\
83	uint32_t next_ofs; /* (0 for end of chain) */ \
84	uint32_t translations_bitmap; \
85	uint32_t translation_ranges_ofs; \
86	addrtype physaddr; \
87	}; \
88	\
89	struct arch ## _vpg_tlb_entry { \
90	uint8_t valid; \
91	uint8_t writeflag; \
92	addrtype vaddr_page; \
93	addrtype paddr_page; \
94	unsigned char *host_page; \
95	};
96
97	#define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \
98	struct arch ## _l3_64_table { \
99	unsigned char *host_load[1 << ARCH ## _L3N]; \
100	unsigned char *host_store[1 << ARCH ## _L3N]; \
101	uint64_t phys_addr[1 << ARCH ## _L3N]; \
102	tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \
103	struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \
104	struct arch ## _l3_64_table *next; \
105	int refcount; \
106	}; \
107	struct arch ## _l2_64_table { \
108	struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \
109	struct arch ## _l2_64_table *next; \
110	int refcount; \
111	};
112
113
114	/*
115	* This structure contains a list of ranges within an emulated
116	* physical page that contain translatable code.
117	*/
118	#define PHYSPAGE_RANGES_ENTRIES_PER_LIST 20
119	struct physpage_ranges {
120	uint32_t next_ofs; /* 0 for end of chain */
121	uint32_t n_entries_used;
122	uint16_t base[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
123	uint16_t length[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
124	uint16_t count[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
125	};
126
127
128	/*
129	* Dyntrans "Instruction Translation Cache":
130	*
131	* cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to
132	* be the same as cur_ic_page, because all the instrcalls should be placed
133	* first in the physpage struct!)
134	*
135	* cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE
136	* instruction call entries.
137	*
138	* next_ic points to the next such instruction call to be executed.
139	*
140	* combination_check, when set to non-NULL, is executed automatically after
141	* an instruction has been translated. (It check for combinations of
142	* instructions; low_addr is the offset of the translated instruction in the
143	* current page, NOT shifted right.)
144	*/
145	#define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \
146	struct arch ## _instr_call *cur_ic_page; \
147	struct arch ## _instr_call *next_ic; \
148	struct arch ## _tc_physpage *physpage_template;\
149	void (combination_check)(struct cpu , \
150	struct arch ## _instr_call *, int low_addr);
151
152	/*
153	* Virtual -> physical -> host address translation TLB entries:
154	* ------------------------------------------------------------
155	*
156	* Regardless of whether 32-bit or 64-bit address translation is used, the
157	* same TLB entry structure is used.
158	*/
159	#define VPH_TLBS(arch,ARCH) \
160	struct arch ## _vpg_tlb_entry \
161	vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES];
162
163	/*
164	* 32-bit dyntrans emulated Virtual -> physical -> host address translation:
165	* -------------------------------------------------------------------------
166	*
167	* This stuff assumes that 4 KB pages are used. 20 bits to select a page
168	* means just 1 M entries needed. This is small enough that a couple of
169	* full-size tables can fit in virtual memory on modern hosts (both 32-bit
170	* and 64-bit hosts). :-)
171	*
172	* Usage: e.g. VPH32(arm,ARM)
173	* or VPH32(sparc,SPARC)
174	*
175	* The vph_tlb_entry entries are cpu dependent tlb entries.
176	*
177	* The host_load and host_store entries point to host pages; the phys_addr
178	* entries are uint32_t (emulated physical addresses).
179	*
180	* phys_page points to translation cache physpages.
181	*
182	* vaddr_to_tlbindex is a virtual address to tlb index hint table.
183	* The values in this array are the tlb index plus 1, so a value of, say,
184	* 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
185	* is not a valid index. (I.e. no hit.)
186	*
187	* The VPH32EXTENDED variant adds an additional postfix to the array
188	* names. Used so far only for usermode addresses in M88K emulation.
189	*/
190	#define N_VPH32_ENTRIES 1048576
191	#define VPH32(arch,ARCH) \
192	unsigned char *host_load[N_VPH32_ENTRIES]; \
193	unsigned char *host_store[N_VPH32_ENTRIES]; \
194	uint32_t phys_addr[N_VPH32_ENTRIES]; \
195	struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \
196	uint8_t vaddr_to_tlbindex[N_VPH32_ENTRIES];
197	#define VPH32_16BITVPHENTRIES(arch,ARCH) \
198	unsigned char *host_load[N_VPH32_ENTRIES]; \
199	unsigned char *host_store[N_VPH32_ENTRIES]; \
200	uint32_t phys_addr[N_VPH32_ENTRIES]; \
201	struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \
202	uint16_t vaddr_to_tlbindex[N_VPH32_ENTRIES];
203	#define VPH32EXTENDED(arch,ARCH,ex) \
204	unsigned char *host_load_ ## ex[N_VPH32_ENTRIES]; \
205	unsigned char *host_store_ ## ex[N_VPH32_ENTRIES]; \
206	uint32_t phys_addr_ ## ex[N_VPH32_ENTRIES]; \
207	struct arch ## _tc_physpage *phys_page_ ## ex[N_VPH32_ENTRIES];\
208	uint8_t vaddr_to_tlbindex_ ## ex[N_VPH32_ENTRIES];
209
210
211	/*
212	* 64-bit dyntrans emulated Virtual -> physical -> host address translation:
213	* -------------------------------------------------------------------------
214	*
215	* Usage: e.g. VPH64(alpha,ALPHA)
216	* or VPH64(sparc,SPARC)
217	*
218	* l1_64 is an array containing poiners to l2 tables.
219	*
220	* l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL
221	* pointers in l1_64 for unused slots, a pointer to the dummy table can be
222	* used.
223	*/
224	#define DYNTRANS_L1N 17
225	#define VPH64(arch,ARCH) \
226	struct arch ## _l3_64_table *l3_64_dummy; \
227	struct arch ## _l3_64_table *next_free_l3; \
228	struct arch ## _l2_64_table *l2_64_dummy; \
229	struct arch ## _l2_64_table *next_free_l2; \
230	struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N];
231
232
233	/* Include all CPUs' header files here: */
234	#include "cpu_alpha.h"
235	#include "cpu_arm.h"
236	#include "cpu_m32r.h"
237	#include "cpu_m88k.h"
238	#include "cpu_mips.h"
239	#include "cpu_ppc.h"
240	#include "cpu_sh.h"
241	#include "cpu_sparc.h"
242
243	struct cpu;
244	struct emul;
245	struct machine;
246	struct memory;
247	struct settings;
248
249
250	/*
251	* cpu_family
252	* ----------
253	*
254	* This structure consists of various pointers to functions, performing
255	* architecture-specific functions.
256	*
257	* Except for the next and arch fields at the top, all fields in the
258	* cpu_family struct are filled in by ecah CPU family's init function.
259	*/
260	struct cpu_family {
261	struct cpu_family *next;
262	int arch;
263
264	/* Familty name, e.g. "MIPS", "Alpha" etc. */
265	char *name;
266
267	/* Fill in architecture specific parts of a struct cpu. */
268	int (cpu_new)(struct cpu cpu, struct memory *mem,
269	struct machine *machine,
270	int cpu_id, char *cpu_type_name);
271
272	/* Initialize various translation tables. */
273	void (init_tables)(struct cpu cpu);
274
275	/* List available CPU types for this architecture. */
276	void (*list_available_types)(void);
277
278	/* Disassemble an instruction. */
279	int (disassemble_instr)(struct cpu cpu,
280	unsigned char *instr, int running,
281	uint64_t dumpaddr);
282
283	/* Dump CPU registers in readable format. */
284	void (register_dump)(struct cpu cpu,
285	int gprs, int coprocs);
286
287	/* Dump generic CPU info in readable format. */
288	void (dumpinfo)(struct cpu cpu);
289
290	/* Dump TLB data for CPU id x. */
291	void (tlbdump)(struct machine m, int x,
292	int rawflag);
293
294	/* Print architecture-specific function call arguments.
295	(This is called for each function call, if running with -t.) */
296	void (functioncall_trace)(struct cpu ,
297	uint64_t f, int n_args);
298	};
299
300
301	/*
302	* More dyntrans stuff:
303	*
304	* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
305	* into the cache, for possible translation cache structs for physical pages.
306	*/
307
308	/* Meaning of delay_slot: */
309	#define NOT_DELAYED 0
310	#define DELAYED 1
311	#define TO_BE_DELAYED 2
312	#define EXCEPTION_IN_DELAY_SLOT 8
313
314	#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14
315	#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)
316
317	#define MAX_DYNTRANS_READAHEAD 128
318
319	#define DEFAULT_DYNTRANS_CACHE_SIZE (48*1048576)
320	#define DYNTRANS_CACHE_MARGIN 200000
321
322	#define N_BASE_TABLE_ENTRIES 65536
323	#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1))
324
325
326	/*
327	* The generic CPU struct:
328	*/
329
330	struct cpu {
331	/* Pointer back to the machine this CPU is in: */
332	struct machine *machine;
333
334	/* Settings: */
335	struct settings *settings;
336
337	/* CPU-specific name, e.g. "R2000", "21164PC", etc. */
338	char *name;
339
340	/* Full "path" to the CPU, e.g. "machine[0].cpu[0]": */
341	char *path;
342
343	/* Nr of instructions executed, etc.: */
344	int64_t ninstrs;
345	int64_t ninstrs_show;
346	int64_t ninstrs_flush;
347	int64_t ninstrs_since_gettimeofday;
348	struct timeval starttime;
349
350	/* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */
351	uint8_t byte_order;
352
353	/* 0 for emulated 64-bit CPUs, 1 for 32-bit. */
354	uint8_t is_32bit;
355
356	/* 1 while running, 0 when paused/stopped. */
357	uint8_t running;
358
359	/* See comment further up. */
360	uint8_t delay_slot;
361
362	/* 0-based CPU id, in an emulated SMP system. */
363	int cpu_id;
364
365	/* A pointer to the main memory connected to this CPU. */
366	struct memory *mem;
367
368	int (run_instr)(struct cpu cpu);
369	int (memory_rw)(struct cpu cpu,
370	struct memory *mem, uint64_t vaddr,
371	unsigned char *data, size_t len,
372	int writeflag, int cache_flags);
373	int (translate_v2p)(struct cpu , uint64_t vaddr,
374	uint64_t *return_paddr, int flags);
375	void (update_translation_table)(struct cpu ,
376	uint64_t vaddr_page, unsigned char *host_page,
377	int writeflag, uint64_t paddr_page);
378	void (invalidate_translation_caches)(struct cpu ,
379	uint64_t paddr, int flags);
380	void (invalidate_code_translation)(struct cpu ,
381	uint64_t paddr, int flags);
382	void (useremul_syscall)(struct cpu cpu, uint32_t code);
383	int (instruction_has_delayslot)(struct cpu cpu,
384	unsigned char *ib);
385
386	/* The program counter. (For 32-bit modes, not all bits are used.) */
387	uint64_t pc;
388
389	/* The current depth of function call tracing. */
390	int trace_tree_depth;
391
392	/*
393	* If is_halted is true when an interrupt trap occurs, the pointer
394	* to the next instruction to execute will be the instruction
395	* following the halt instruction, not the halt instrucion itself.
396	*
397	* If has_been_idling is true when printing the number of executed
398	* instructions per second, "idling" is printed instead. (The number
399	* of instrs per second when idling is meaningless anyway.)
400	*/
401	char is_halted;
402	char has_been_idling;
403
404	/*
405	* Dynamic translation:
406	*
407	* The number of translated instructions is assumed to be 1 per
408	* instruction call. For each case where this differs from the
409	* truth, n_translated_instrs should be modified. E.g. if 1000
410	* instruction calls are done, and n_translated_instrs is 50, then
411	* 1050 emulated instructions were actually executed.
412	*
413	* Note that it can also be adjusted negatively, that is, the way
414	* to "get out" of a dyntrans loop is to set the current instruction
415	* call pointer to the "nothing" instruction. This instruction
416	* _decreases_ n_translated_instrs by 1. That way, once the dyntrans
417	* loop exits, only real instructions will be counted, and not the
418	* "nothing" instructions.
419	*
420	* The translation cache is a relative large chunk of memory (say,
421	* 32 MB) which is used for translations. When it has been used up,
422	* everything restarts from scratch.
423	*
424	* translation_readahead is non-zero when translating instructions
425	* ahead of the current (emulated) instruction pointer.
426	*/
427
428	int translation_readahead;
429
430	/* Instruction translation cache: */
431	int n_translated_instrs;
432	unsigned char *translation_cache;
433	size_t translation_cache_cur_ofs;
434
435
436	/*
437	* CPU-family dependent:
438	*
439	* These contain everything ranging from general purpose registers,
440	* control registers, memory management, status words, interrupt
441	* specifics, etc.
442	*/
443	union {
444	struct alpha_cpu alpha;
445	struct arm_cpu arm;
446	struct m32r_cpu m32r;
447	struct m88k_cpu m88k;
448	struct mips_cpu mips;
449	struct ppc_cpu ppc;
450	struct sh_cpu sh;
451	struct sparc_cpu sparc;
452	} cd;
453	};
454
455
456	/* cpu.c: */
457	struct cpu cpu_new(struct memory mem, struct machine *machine,
458	int cpu_id, char *cpu_type_name);
459	void cpu_destroy(struct cpu *cpu);
460
461	void cpu_tlbdump(struct machine *m, int x, int rawflag);
462	void cpu_register_dump(struct machine m, struct cpu cpu,
463	int gprs, int coprocs);
464	int cpu_disassemble_instr(struct machine m, struct cpu cpu,
465	unsigned char *instr, int running, uint64_t addr);
466
467	void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
468	void cpu_functioncall_trace_return(struct cpu *cpu);
469
470	void cpu_create_or_reset_tc(struct cpu *cpu);
471
472	void cpu_run_init(struct machine *machine);
473	void cpu_run_deinit(struct machine *machine);
474
475	void cpu_dumpinfo(struct machine m, struct cpu cpu);
476	void cpu_list_available_types(void);
477	void cpu_show_cycles(struct machine *machine, int forced);
478
479	struct cpu_family *cpu_family_ptr_by_number(int arch);
480	void cpu_init(void);
481
482
483	#define JUST_MARK_AS_NON_WRITABLE 1
484	#define INVALIDATE_ALL 2
485	#define INVALIDATE_PADDR 4
486	#define INVALIDATE_VADDR 8
487	#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */
488
489
490	/* Note: 64-bit processors running in 32-bit mode use a 32-bit
491	display format, even though the underlying data is 64-bits. */
492	#define CPU_SETTINGS_ADD_REGISTER64(name, var) \
493	settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT64, \
494	cpu->is_32bit? SETTINGS_FORMAT_HEX32 : SETTINGS_FORMAT_HEX64, \
495	(void *) &(var));
496	#define CPU_SETTINGS_ADD_REGISTER32(name, var) \
497	settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT32, \
498	SETTINGS_FORMAT_HEX32, (void *) &(var));
499	#define CPU_SETTINGS_ADD_REGISTER16(name, var) \
500	settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT16, \
501	SETTINGS_FORMAT_HEX16, (void *) &(var));
502	#define CPU_SETTINGS_ADD_REGISTER8(name, var) \
503	settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT8, \
504	SETTINGS_FORMAT_HEX8, (void *) &(var));
505
506
507	#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
508	struct cpu_family *fp) { \
509	/* Fill in the cpu_family struct with valid data for this arch. */ \
510	fp->name = s; \
511	fp->cpu_new = n ## _cpu_new; \
512	fp->list_available_types = n ## _cpu_list_available_types; \
513	fp->disassemble_instr = n ## _cpu_disassemble_instr; \
514	fp->register_dump = n ## _cpu_register_dump; \
515	fp->dumpinfo = n ## _cpu_dumpinfo; \
516	fp->functioncall_trace = n ## _cpu_functioncall_trace; \
517	fp->tlbdump = n ## _cpu_tlbdump; \
518	fp->init_tables = n ## _cpu_init_tables; \
519	return 1; \
520	}
521
522
523	#endif /* CPU_H */