/[gxemul]/trunk/src/include/cpu.h
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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 17880 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 #ifndef CPU_H
2 #define CPU_H
3
4 /*
5 * Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu.h,v 1.128 2007/06/14 04:53:14 debug Exp $
32 *
33 * CPU-related definitions.
34 */
35
36
37 #include <sys/types.h>
38 #include <inttypes.h>
39 #include <sys/time.h>
40
41 /* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */
42 #include "../../config.h"
43
44 #include "timer.h"
45
46
47 /*
48 * Dyntrans misc declarations, used throughout the dyntrans code.
49 *
50 * Note that there is space for all instruction calls within a page,
51 * and then 2 more. The first one of these "extra" instruction slots is
52 * the end-of-page slot. It transfers control to the first instruction
53 * slot on the next (virtual) page.
54 *
55 * The second of these extra instruction slots is an additional
56 * end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch
57 * instruction can "nullify" (skip) the delay-slot. If the end-of-page
58 * slot is skipped, then we end up one step after that. That's where the
59 * end_of_page2 slot is. :)
60 *
61 * next_ofs points to the next page in a chain of possible pages.
62 * (several pages can be in the same chain, but only one matches the
63 * specific physaddr.)
64 *
65 * translations is a tiny bitmap indicating which parts of the page have
66 * actual translations. Bit 0 corresponds to the lowest 1/32th of the page,
67 * bit 1 to the second-lowest 1/32th, and so on. This speeds up page
68 * invalidations, since only part of the page need to be reset.
69 */
70 #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \
71 arch ## _instr_call { \
72 void (*f)(struct cpu *, struct arch ## _instr_call *); \
73 size_t arg[ARCH ## _N_IC_ARGS]; \
74 }; \
75 \
76 /* Translation cache struct for each physical page: */ \
77 struct arch ## _tc_physpage { \
78 struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\
79 uint32_t next_ofs; /* (0 for end of chain) */ \
80 uint32_t translations; \
81 addrtype physaddr; \
82 }; \
83 \
84 struct arch ## _vpg_tlb_entry { \
85 uint8_t valid; \
86 uint8_t writeflag; \
87 addrtype vaddr_page; \
88 addrtype paddr_page; \
89 unsigned char *host_page; \
90 };
91
92 #define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \
93 struct arch ## _l3_64_table { \
94 unsigned char *host_load[1 << ARCH ## _L3N]; \
95 unsigned char *host_store[1 << ARCH ## _L3N]; \
96 uint64_t phys_addr[1 << ARCH ## _L3N]; \
97 tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \
98 struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \
99 struct arch ## _l3_64_table *next; \
100 int refcount; \
101 }; \
102 struct arch ## _l2_64_table { \
103 struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \
104 struct arch ## _l2_64_table *next; \
105 int refcount; \
106 };
107
108 /*
109 * Dyntrans "Instruction Translation Cache":
110 *
111 * cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to
112 * be the same as cur_ic_page, because all the instrcalls should be placed
113 * first in the physpage struct!)
114 *
115 * cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE
116 * instruction call entries.
117 *
118 * next_ic points to the next such instruction call to be executed.
119 *
120 * combination_check, when set to non-NULL, is executed automatically after
121 * an instruction has been translated. (It check for combinations of
122 * instructions; low_addr is the offset of the translated instruction in the
123 * current page, NOT shifted right.)
124 */
125 #define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \
126 struct arch ## _instr_call *cur_ic_page; \
127 struct arch ## _instr_call *next_ic; \
128 struct arch ## _tc_physpage *physpage_template;\
129 void (*combination_check)(struct cpu *, \
130 struct arch ## _instr_call *, int low_addr);
131
132 /*
133 * Virtual -> physical -> host address translation TLB entries:
134 * ------------------------------------------------------------
135 *
136 * Regardless of whether 32-bit or 64-bit address translation is used, the
137 * same TLB entry structure is used.
138 */
139 #define VPH_TLBS(arch,ARCH) \
140 struct arch ## _vpg_tlb_entry \
141 vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES];
142
143 /*
144 * 32-bit dyntrans emulated Virtual -> physical -> host address translation:
145 * -------------------------------------------------------------------------
146 *
147 * This stuff assumes that 4 KB pages are used. 20 bits to select a page
148 * means just 1 M entries needed. This is small enough that a couple of
149 * full-size tables can fit in virtual memory on modern hosts (both 32-bit
150 * and 64-bit hosts). :-)
151 *
152 * Usage: e.g. VPH32(arm,ARM)
153 * or VPH32(sparc,SPARC)
154 *
155 * The vph_tlb_entry entries are cpu dependent tlb entries.
156 *
157 * The host_load and host_store entries point to host pages; the phys_addr
158 * entries are uint32_t (emulated physical addresses).
159 *
160 * phys_page points to translation cache physpages.
161 *
162 * vaddr_to_tlbindex is a virtual address to tlb index hint table.
163 * The values in this array are the tlb index plus 1, so a value of, say,
164 * 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
165 * is not a valid index. (I.e. no hit.)
166 *
167 * The VPH32EXTENDED variant adds an additional postfix to the array
168 * names. Used so far only for usermode addresses in M88K emulation.
169 */
170 #define N_VPH32_ENTRIES 1048576
171 #define VPH32(arch,ARCH) \
172 unsigned char *host_load[N_VPH32_ENTRIES]; \
173 unsigned char *host_store[N_VPH32_ENTRIES]; \
174 uint32_t phys_addr[N_VPH32_ENTRIES]; \
175 struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \
176 uint8_t vaddr_to_tlbindex[N_VPH32_ENTRIES];
177 #define VPH32_16BITVPHENTRIES(arch,ARCH) \
178 unsigned char *host_load[N_VPH32_ENTRIES]; \
179 unsigned char *host_store[N_VPH32_ENTRIES]; \
180 uint32_t phys_addr[N_VPH32_ENTRIES]; \
181 struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \
182 uint16_t vaddr_to_tlbindex[N_VPH32_ENTRIES];
183 #define VPH32EXTENDED(arch,ARCH,ex) \
184 unsigned char *host_load_ ## ex[N_VPH32_ENTRIES]; \
185 unsigned char *host_store_ ## ex[N_VPH32_ENTRIES]; \
186 uint32_t phys_addr_ ## ex[N_VPH32_ENTRIES]; \
187 struct arch ## _tc_physpage *phys_page_ ## ex[N_VPH32_ENTRIES];\
188 uint8_t vaddr_to_tlbindex_ ## ex[N_VPH32_ENTRIES];
189
190
191 /*
192 * 64-bit dyntrans emulated Virtual -> physical -> host address translation:
193 * -------------------------------------------------------------------------
194 *
195 * Usage: e.g. VPH64(alpha,ALPHA)
196 * or VPH64(sparc,SPARC)
197 *
198 * l1_64 is an array containing poiners to l2 tables.
199 *
200 * l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL
201 * pointers in l1_64 for unused slots, a pointer to the dummy table can be
202 * used.
203 */
204 #define DYNTRANS_L1N 17
205 #define VPH64(arch,ARCH) \
206 struct arch ## _l3_64_table *l3_64_dummy; \
207 struct arch ## _l3_64_table *next_free_l3; \
208 struct arch ## _l2_64_table *l2_64_dummy; \
209 struct arch ## _l2_64_table *next_free_l2; \
210 struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N];
211
212
213 /* Include all CPUs' header files here: */
214 #include "cpu_alpha.h"
215 #include "cpu_arm.h"
216 #include "cpu_m88k.h"
217 #include "cpu_mips.h"
218 #include "cpu_ppc.h"
219 #include "cpu_sh.h"
220 #include "cpu_sparc.h"
221
222 struct cpu;
223 struct emul;
224 struct machine;
225 struct memory;
226 struct settings;
227
228
229 /*
230 * cpu_family
231 * ----------
232 *
233 * This structure consists of various pointers to functions, performing
234 * architecture-specific functions.
235 *
236 * Except for the next and arch fields at the top, all fields in the
237 * cpu_family struct are filled in by ecah CPU family's init function.
238 */
239 struct cpu_family {
240 struct cpu_family *next;
241 int arch;
242
243 /* Familty name, e.g. "MIPS", "Alpha" etc. */
244 char *name;
245
246 /* Fill in architecture specific parts of a struct cpu. */
247 int (*cpu_new)(struct cpu *cpu, struct memory *mem,
248 struct machine *machine,
249 int cpu_id, char *cpu_type_name);
250
251 /* Initialize various translation tables. */
252 void (*init_tables)(struct cpu *cpu);
253
254 /* List available CPU types for this architecture. */
255 void (*list_available_types)(void);
256
257 /* Disassemble an instruction. */
258 int (*disassemble_instr)(struct cpu *cpu,
259 unsigned char *instr, int running,
260 uint64_t dumpaddr);
261
262 /* Dump CPU registers in readable format. */
263 void (*register_dump)(struct cpu *cpu,
264 int gprs, int coprocs);
265
266 /* Dump generic CPU info in readable format. */
267 void (*dumpinfo)(struct cpu *cpu);
268
269 /* Dump TLB data for CPU id x. */
270 void (*tlbdump)(struct machine *m, int x,
271 int rawflag);
272
273 /* Print architecture-specific function call arguments.
274 (This is called for each function call, if running with -t.) */
275 void (*functioncall_trace)(struct cpu *,
276 uint64_t f, int n_args);
277 };
278
279
280 /*
281 * More dyntrans stuff:
282 *
283 * The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
284 * into the cache, for possible translation cache structs for physical pages.
285 */
286
287 /* Meaning of delay_slot: */
288 #define NOT_DELAYED 0
289 #define DELAYED 1
290 #define TO_BE_DELAYED 2
291 #define EXCEPTION_IN_DELAY_SLOT 8
292
293 #define N_SAFE_DYNTRANS_LIMIT_SHIFT 14
294 #define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)
295
296 #define MAX_DYNTRANS_READAHEAD 1024
297
298 #define DEFAULT_DYNTRANS_CACHE_SIZE (48*1048576)
299 #define DYNTRANS_CACHE_MARGIN 200000
300
301 #define N_BASE_TABLE_ENTRIES 65536
302 #define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1))
303
304 #define CPU_SAMPLE_TIMER_HZ TIMER_BASE_FREQUENCY
305 #define N_PADDR_SAMPLES 64
306
307
308 /*
309 * The generic CPU struct:
310 */
311
312 struct cpu {
313 /* Pointer back to the machine this CPU is in: */
314 struct machine *machine;
315
316 /* Settings: */
317 struct settings *settings;
318
319 /* CPU-specific name, e.g. "R2000", "21164PC", etc. */
320 char *name;
321
322 /* Full "path" to the CPU, e.g. "emul[0].machine[0].cpu[0]": */
323 char *path;
324
325 /* Nr of instructions executed, etc.: */
326 int64_t ninstrs;
327 int64_t ninstrs_show;
328 int64_t ninstrs_flush;
329 int64_t ninstrs_since_gettimeofday;
330 struct timeval starttime;
331
332 /*
333 * Periodic sampling of the physical address corresponding to the
334 * emulated program counter:
335 *
336 * (Used to decide whether or not native code generation is worth
337 * the effort.)
338 */
339 struct timer *sampling_timer;
340 uint8_t sampling; /* 1 = turned on */
341 int16_t sampling_curindex;
342 uint64_t *sampling_paddr;
343
344 /* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */
345 uint8_t byte_order;
346
347 /* 0 for emulated 64-bit CPUs, 1 for 32-bit. */
348 uint8_t is_32bit;
349
350 /* 1 while running, 0 when paused/stopped. */
351 uint8_t running;
352
353 /* See comment further up. */
354 uint8_t delay_slot;
355
356 /* 0-based CPU id, in an emulated SMP system. */
357 int cpu_id;
358
359 /* A pointer to the main memory connected to this CPU. */
360 struct memory *mem;
361
362 int (*run_instr)(struct cpu *cpu);
363 int (*memory_rw)(struct cpu *cpu,
364 struct memory *mem, uint64_t vaddr,
365 unsigned char *data, size_t len,
366 int writeflag, int cache_flags);
367 int (*translate_v2p)(struct cpu *, uint64_t vaddr,
368 uint64_t *return_paddr, int flags);
369 void (*update_translation_table)(struct cpu *,
370 uint64_t vaddr_page, unsigned char *host_page,
371 int writeflag, uint64_t paddr_page);
372 void (*invalidate_translation_caches)(struct cpu *,
373 uint64_t paddr, int flags);
374 void (*invalidate_code_translation)(struct cpu *,
375 uint64_t paddr, int flags);
376 void (*useremul_syscall)(struct cpu *cpu, uint32_t code);
377 int (*instruction_has_delayslot)(struct cpu *cpu,
378 unsigned char *ib);
379
380 /* The program counter. (For 32-bit modes, not all bits are used.) */
381 uint64_t pc;
382
383 /* The current depth of function call tracing. */
384 int trace_tree_depth;
385
386 /*
387 * If is_halted is true when an interrupt trap occurs, the pointer
388 * to the next instruction to execute will be the instruction
389 * following the halt instruction, not the halt instrucion itself.
390 *
391 * If has_been_idling is true when printing the number of executed
392 * instructions per second, "idling" is printed instead. (The number
393 * of instrs per second when idling is meaningless anyway.)
394 */
395 char is_halted;
396 char has_been_idling;
397
398 /*
399 * Dynamic translation:
400 *
401 * The number of translated instructions is assumed to be 1 per
402 * instruction call. For each case where this differs from the
403 * truth, n_translated_instrs should be modified. E.g. if 1000
404 * instruction calls are done, and n_translated_instrs is 50, then
405 * 1050 emulated instructions were actually executed.
406 *
407 * Note that it can also be adjusted negatively, that is, the way
408 * to "get out" of a dyntrans loop is to set the current instruction
409 * call pointer to the "nothing" instruction. This instruction
410 * _decreases_ n_translated_instrs by 1. That way, once the dyntrans
411 * loop exits, only real instructions will be counted, and not the
412 * "nothing" instructions.
413 *
414 * The translation cache is a relative large chunk of memory (say,
415 * 32 MB) which is used for translations. When it has been used up,
416 * everything restarts from scratch.
417 *
418 * translation_readahead is non-zero when translating instructions
419 * ahead of the current (emulated) instruction pointer.
420 */
421
422 /* Non-zero when translating ahead of the current instruction: */
423 int translation_readahead;
424
425 /* Instruction translation cache: */
426 int n_translated_instrs;
427 unsigned char *translation_cache;
428 size_t translation_cache_cur_ofs;
429
430
431 /*
432 * CPU-family dependent:
433 *
434 * These contain everything ranging from general purpose registers,
435 * control registers, memory management, status words, interrupt
436 * specifics, etc.
437 */
438 union {
439 struct alpha_cpu alpha;
440 struct arm_cpu arm;
441 struct m88k_cpu m88k;
442 struct mips_cpu mips;
443 struct ppc_cpu ppc;
444 struct sh_cpu sh;
445 struct sparc_cpu sparc;
446 } cd;
447 };
448
449
450 /* cpu.c: */
451 struct cpu *cpu_new(struct memory *mem, struct machine *machine,
452 int cpu_id, char *cpu_type_name);
453 void cpu_destroy(struct cpu *cpu);
454
455 void cpu_tlbdump(struct machine *m, int x, int rawflag);
456 void cpu_register_dump(struct machine *m, struct cpu *cpu,
457 int gprs, int coprocs);
458 int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
459 unsigned char *instr, int running, uint64_t addr);
460
461 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
462 void cpu_functioncall_trace_return(struct cpu *cpu);
463
464 void cpu_create_or_reset_tc(struct cpu *cpu);
465
466 void cpu_run_init(struct machine *machine);
467 void cpu_run_deinit(struct machine *machine);
468
469 void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
470 void cpu_list_available_types(void);
471 void cpu_show_cycles(struct machine *machine, int forced);
472
473 struct cpu_family *cpu_family_ptr_by_number(int arch);
474 void cpu_init(void);
475
476
477 #define JUST_MARK_AS_NON_WRITABLE 1
478 #define INVALIDATE_ALL 2
479 #define INVALIDATE_PADDR 4
480 #define INVALIDATE_VADDR 8
481 #define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */
482
483
484 /* Note: 64-bit processors running in 32-bit mode use a 32-bit
485 display format, even though the underlying data is 64-bits. */
486 #define CPU_SETTINGS_ADD_REGISTER64(name, var) \
487 settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT64, \
488 cpu->is_32bit? SETTINGS_FORMAT_HEX32 : SETTINGS_FORMAT_HEX64, \
489 (void *) &(var));
490 #define CPU_SETTINGS_ADD_REGISTER32(name, var) \
491 settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT32, \
492 SETTINGS_FORMAT_HEX32, (void *) &(var));
493 #define CPU_SETTINGS_ADD_REGISTER16(name, var) \
494 settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT16, \
495 SETTINGS_FORMAT_HEX16, (void *) &(var));
496 #define CPU_SETTINGS_ADD_REGISTER8(name, var) \
497 settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT8, \
498 SETTINGS_FORMAT_HEX8, (void *) &(var));
499
500
501 #define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
502 struct cpu_family *fp) { \
503 /* Fill in the cpu_family struct with valid data for this arch. */ \
504 fp->name = s; \
505 fp->cpu_new = n ## _cpu_new; \
506 fp->list_available_types = n ## _cpu_list_available_types; \
507 fp->disassemble_instr = n ## _cpu_disassemble_instr; \
508 fp->register_dump = n ## _cpu_register_dump; \
509 fp->dumpinfo = n ## _cpu_dumpinfo; \
510 fp->functioncall_trace = n ## _cpu_functioncall_trace; \
511 fp->tlbdump = n ## _cpu_tlbdump; \
512 fp->init_tables = n ## _cpu_init_tables; \
513 return 1; \
514 }
515
516
517 #endif /* CPU_H */
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