/[gxemul]/trunk/src/include/cpu.h
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Contents of /trunk/src/include/cpu.h

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Revision 26 - (show annotations)
Mon Oct 8 16:20:10 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 13510 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1264 2006/06/25 11:08:04 debug Exp $
20060624	Replacing the error-prone machine type initialization stuff
		with something more reasonable.
		Finally removing the old "cpu_run" kludge; moving around stuff
		in machine.c and emul.c to better suit the dyntrans system.
		Various minor dyntrans cleanups (renaming translate_address to
		translate_v2p, and experimenting with template physpages).
20060625	Removing the speed hack which separated the vph entries into
		two halves (code vs data); things seem a lot more stable now.
		Minor performance hack: R2000/R3000 cache isolation now only
		clears address translations when going into isolation, not
		when going out of it.
		Fixing the MIPS interrupt problems by letting mtc0 immediately
		cause interrupts.

==============  RELEASE 0.4.0.1  ==============


1 #ifndef CPU_H
2 #define CPU_H
3
4 /*
5 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu.h,v 1.79 2006/06/25 00:27:36 debug Exp $
32 *
33 * CPU-related definitions.
34 */
35
36
37 #include <sys/types.h>
38 #include <inttypes.h>
39 #include <sys/time.h>
40
41 /* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */
42 #include "../../config.h"
43
44 /*
45 * Dyntrans misc declarations, used throughout the dyntrans code.
46 *
47 * Note that there is place for all instruction calls within a page,
48 * and then 2 more. The first one of these "extra" instruction slots is
49 * the end-of-page slot. It transfers control to the first instruction
50 * slot on the next (virtual) page.
51 *
52 * The second of these extra instruction slots is an additional
53 * end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch
54 * instruction can "nullify" (skip) the delay-slot. If the end-of-page
55 * slot is skipped, then we end up one step after that. That's where the
56 * end_of_page2 slot is. :)
57 */
58 #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \
59 arch ## _instr_call { \
60 void (*f)(struct cpu *, struct arch ## _instr_call *); \
61 size_t arg[ARCH ## _N_IC_ARGS]; \
62 }; \
63 \
64 /* Translation cache struct for each physical page: */ \
65 struct arch ## _tc_physpage { \
66 struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\
67 uint32_t next_ofs; /* (0 for end of chain) */ \
68 int flags; \
69 addrtype physaddr; \
70 }; \
71 \
72 struct arch ## _vpg_tlb_entry { \
73 uint8_t valid; \
74 uint8_t writeflag; \
75 addrtype vaddr_page; \
76 addrtype paddr_page; \
77 unsigned char *host_page; \
78 int64_t timestamp; \
79 };
80
81 #define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \
82 struct arch ## _l3_64_table { \
83 unsigned char *host_load[1 << ARCH ## _L3N]; \
84 unsigned char *host_store[1 << ARCH ## _L3N]; \
85 uint64_t phys_addr[1 << ARCH ## _L3N]; \
86 tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \
87 struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \
88 struct arch ## _l3_64_table *next; \
89 int refcount; \
90 }; \
91 struct arch ## _l2_64_table { \
92 struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \
93 struct arch ## _l2_64_table *next; \
94 int refcount; \
95 };
96
97 /*
98 * Dyntrans "Instruction Translation Cache":
99 *
100 * cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to
101 * be the same as cur_ic_page, because all the instrcalls should be placed
102 * first in the physpage struct!)
103 *
104 * cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE
105 * instruction call entries.
106 *
107 * next_ic points to the next such instruction call to be executed.
108 *
109 * combination_check, when set to non-NULL, is executed automatically after
110 * an instruction has been translated. (It check for combinations of
111 * instructions; low_addr is the offset of the translated instruction in the
112 * current page, NOT shifted right.)
113 */
114 #define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \
115 struct arch ## _instr_call *cur_ic_page; \
116 struct arch ## _instr_call *next_ic; \
117 struct arch ## _tc_physpage *physpage_template;\
118 void (*combination_check)(struct cpu *, \
119 struct arch ## _instr_call *, int low_addr);
120
121 /*
122 * Virtual -> physical -> host address translation TLB entries:
123 * ------------------------------------------------------------
124 *
125 * Regardless of whether 32-bit or 64-bit address translation is used, the
126 * same TLB entry structure is used.
127 */
128 #define VPH_TLBS(arch,ARCH) \
129 struct arch ## _vpg_tlb_entry \
130 vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES];
131
132 /*
133 * 32-bit dyntrans emulated Virtual -> physical -> host address translation:
134 * -------------------------------------------------------------------------
135 *
136 * This stuff assumes that 4 KB pages are used. 20 bits to select a page
137 * means just 1 M entries needed. This is small enough that a couple of
138 * full-size tables can fit in virtual memory on modern hosts (both 32-bit
139 * and 64-bit hosts). :-)
140 *
141 * Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t)
142 * or VPH32(sparc,SPARC,uint64_t,uint16_t)
143 *
144 * The vph_tlb_entry entries are cpu dependent tlb entries.
145 *
146 * The host_load and host_store entries point to host pages; the phys_addr
147 * entries are uint32_t or uint64_t (emulated physical addresses).
148 *
149 * phys_page points to translation cache physpages.
150 *
151 * phystranslation is a bitmap which tells us whether a physical page has
152 * a code translation.
153 *
154 * vaddr_to_tlbindex is a virtual address to tlb index hint table.
155 * The values in this array are the tlb index plus 1, so a value of, say,
156 * 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
157 * is not a valid index. (I.e. no hit.)
158 */
159 #define N_VPH32_ENTRIES 1048576
160 #define VPH32(arch,ARCH,paddrtype,tlbindextype) \
161 unsigned char *host_load[N_VPH32_ENTRIES]; \
162 unsigned char *host_store[N_VPH32_ENTRIES]; \
163 paddrtype phys_addr[N_VPH32_ENTRIES]; \
164 struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \
165 uint32_t phystranslation[N_VPH32_ENTRIES/32]; \
166 tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES];
167
168 /*
169 * 64-bit dyntrans emulated Virtual -> physical -> host address translation:
170 * -------------------------------------------------------------------------
171 *
172 * Usage: e.g. VPH64(alpha,ALPHA,uint8_t)
173 * or VPH64(sparc,SPARC,uint16_t)
174 *
175 * l1_64 is an array containing poiners to l2 tables.
176 *
177 * l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL
178 * pointers in l1_64 for unused slots, a pointer to the dummy table can be
179 * used.
180 */
181 #define DYNTRANS_L1N 17
182 #define VPH64(arch,ARCH,tlbindextype) \
183 struct arch ## _l3_64_table *l3_64_dummy; \
184 struct arch ## _l3_64_table *next_free_l3; \
185 struct arch ## _l2_64_table *l2_64_dummy; \
186 struct arch ## _l2_64_table *next_free_l2; \
187 struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N];
188
189
190 /* Include all CPUs' header files here: */
191 #include "cpu_alpha.h"
192 #include "cpu_arm.h"
193 #include "cpu_avr.h"
194 #include "cpu_hppa.h"
195 #include "cpu_i960.h"
196 #include "cpu_ia64.h"
197 #include "cpu_m68k.h"
198 #include "cpu_mips.h"
199 #include "cpu_ppc.h"
200 #include "cpu_sh.h"
201 #include "cpu_sparc.h"
202 #include "cpu_x86.h"
203
204 struct cpu;
205 struct emul;
206 struct machine;
207 struct memory;
208
209
210 struct cpu_family {
211 struct cpu_family *next;
212 int arch;
213
214 /* These are filled in by each CPU family's init function: */
215 char *name;
216 int (*cpu_new)(struct cpu *cpu, struct memory *mem,
217 struct machine *machine,
218 int cpu_id, char *cpu_type_name);
219 void (*list_available_types)(void);
220 void (*register_match)(struct machine *m,
221 char *name, int writeflag,
222 uint64_t *valuep, int *match_register);
223 int (*disassemble_instr)(struct cpu *cpu,
224 unsigned char *instr, int running,
225 uint64_t dumpaddr);
226 void (*register_dump)(struct cpu *cpu,
227 int gprs, int coprocs);
228 int (*run_instr)(struct emul *emul,
229 struct cpu *cpu);
230 void (*dumpinfo)(struct cpu *cpu);
231 void (*tlbdump)(struct machine *m, int x,
232 int rawflag);
233 int (*interrupt)(struct cpu *cpu, uint64_t irq_nr);
234 int (*interrupt_ack)(struct cpu *cpu,
235 uint64_t irq_nr);
236 void (*functioncall_trace)(struct cpu *,
237 uint64_t f, int n_args);
238 char *(*gdb_stub)(struct cpu *, char *cmd);
239 void (*init_tables)(struct cpu *cpu);
240 };
241
242
243 /*
244 * More dyntrans stuff:
245 *
246 * The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
247 * into the cache, for possible translation cache structs for physical pages.
248 */
249
250 /* Physpage flags: */
251 #define TRANSLATIONS 1
252 #define COMBINATIONS 2
253
254 /* Meaning of delay_slot: */
255 #define NOT_DELAYED 0
256 #define DELAYED 1
257 #define TO_BE_DELAYED 2
258 #define EXCEPTION_IN_DELAY_SLOT 0x100
259
260 #define N_SAFE_DYNTRANS_LIMIT_SHIFT 14
261 #define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)
262
263 #define DYNTRANS_CACHE_SIZE (24*1048576)
264 #define DYNTRANS_CACHE_MARGIN 350000
265
266 #define N_BASE_TABLE_ENTRIES 32768
267 #define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1))
268
269
270 /*
271 * The generic CPU struct:
272 */
273
274 struct cpu {
275 /* Pointer back to the machine this CPU is in: */
276 struct machine *machine;
277
278 int byte_order;
279 int running;
280 int dead;
281 int bootstrap_cpu_flag;
282 int cpu_id;
283 int is_32bit; /* 0 for 64-bit, 1 for 32-bit */
284 char *name;
285
286 struct memory *mem;
287 int (*memory_rw)(struct cpu *cpu,
288 struct memory *mem, uint64_t vaddr,
289 unsigned char *data, size_t len,
290 int writeflag, int cache_flags);
291 int (*translate_v2p)(struct cpu *, uint64_t vaddr,
292 uint64_t *return_paddr, int flags);
293 void (*update_translation_table)(struct cpu *,
294 uint64_t vaddr_page, unsigned char *host_page,
295 int writeflag, uint64_t paddr_page);
296 void (*invalidate_translation_caches)(struct cpu *,
297 uint64_t paddr, int flags);
298 void (*invalidate_code_translation)(struct cpu *,
299 uint64_t paddr, int flags);
300 void (*useremul_syscall)(struct cpu *cpu, uint32_t code);
301 int (*instruction_has_delayslot)(struct cpu *cpu,
302 unsigned char *ib);
303
304 uint64_t pc;
305
306 int trace_tree_depth;
307
308 /*
309 * Dynamic translation:
310 */
311 int running_translated;
312 int n_translated_instrs;
313 unsigned char *translation_cache;
314 size_t translation_cache_cur_ofs;
315
316 uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */
317 int delay_slot;
318
319 /*
320 * CPU-family dependent:
321 */
322 union {
323 struct alpha_cpu alpha;
324 struct arm_cpu arm;
325 struct avr_cpu avr;
326 struct hppa_cpu hppa;
327 struct i960_cpu i960;
328 struct ia64_cpu ia64;
329 struct m68k_cpu m68k;
330 struct mips_cpu mips;
331 struct ppc_cpu ppc;
332 struct sh_cpu sh;
333 struct sparc_cpu sparc;
334 struct x86_cpu x86;
335 } cd;
336 };
337
338
339 /* cpu.c: */
340 struct cpu *cpu_new(struct memory *mem, struct machine *machine,
341 int cpu_id, char *cpu_type_name);
342 void cpu_tlbdump(struct machine *m, int x, int rawflag);
343 void cpu_register_match(struct machine *m, char *name,
344 int writeflag, uint64_t *valuep, int *match_register);
345 void cpu_register_dump(struct machine *m, struct cpu *cpu,
346 int gprs, int coprocs);
347 int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
348 unsigned char *instr, int running, uint64_t addr);
349 char *cpu_gdb_stub(struct cpu *cpu, char *cmd);
350 int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
351 int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
352 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
353 void cpu_functioncall_trace_return(struct cpu *cpu);
354 void cpu_create_or_reset_tc(struct cpu *cpu);
355 void cpu_run_init(struct machine *machine);
356 void cpu_run_deinit(struct machine *machine);
357 void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
358 void cpu_list_available_types(void);
359 void cpu_show_cycles(struct machine *machine, int forced);
360 struct cpu_family *cpu_family_ptr_by_number(int arch);
361 void cpu_init(void);
362
363
364 #define JUST_MARK_AS_NON_WRITABLE 1
365 #define INVALIDATE_ALL 2
366 #define INVALIDATE_PADDR 4
367 #define INVALIDATE_VADDR 8
368 #define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */
369
370
371 #define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
372 struct cpu_family *fp) { \
373 /* Fill in the cpu_family struct with valid data for this arch. */ \
374 fp->name = s; \
375 fp->cpu_new = n ## _cpu_new; \
376 fp->list_available_types = n ## _cpu_list_available_types; \
377 fp->register_match = n ## _cpu_register_match; \
378 fp->disassemble_instr = n ## _cpu_disassemble_instr; \
379 fp->register_dump = n ## _cpu_register_dump; \
380 fp->dumpinfo = n ## _cpu_dumpinfo; \
381 fp->interrupt = n ## _cpu_interrupt; \
382 fp->interrupt_ack = n ## _cpu_interrupt_ack; \
383 fp->functioncall_trace = n ## _cpu_functioncall_trace; \
384 fp->gdb_stub = n ## _cpu_gdb_stub; \
385 fp->tlbdump = n ## _cpu_tlbdump; \
386 fp->run_instr = n ## _cpu_run_instr; \
387 fp->init_tables = n ## _cpu_init_tables; \
388 return 1; \
389 }
390
391
392 #endif /* CPU_H */

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