/[gxemul]/trunk/src/include/cpu.h
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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 13446 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 #ifndef CPU_H
2 #define CPU_H
3
4 /*
5 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cpu.h,v 1.75 2006/06/16 18:31:26 debug Exp $
32 *
33 * CPU-related definitions.
34 */
35
36
37 #include <sys/types.h>
38 #include <inttypes.h>
39 #include <sys/time.h>
40
41 /* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */
42 #include "../../config.h"
43
44 /*
45 * Dyntrans misc declarations, used throughout the dyntrans code.
46 *
47 * Note that there is place for all instruction calls within a page,
48 * and then 2 more. The first one of these "extra" instruction slots is
49 * the end-of-page slot. It transfers control to the first instruction
50 * slot on the next (virtual) page.
51 *
52 * The second of these extra instruction slots is an additional
53 * end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch
54 * instruction can "nullify" (skip) the delay-slot. If the end-of-page
55 * slot is skipped, then we end up one step after that. That's where the
56 * end_of_page2 slot is. :)
57 */
58 #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \
59 arch ## _instr_call { \
60 void (*f)(struct cpu *, struct arch ## _instr_call *); \
61 size_t arg[ARCH ## _N_IC_ARGS]; \
62 }; \
63 \
64 /* Translation cache struct for each physical page: */ \
65 struct arch ## _tc_physpage { \
66 struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\
67 uint32_t next_ofs; /* (0 for end of chain) */ \
68 int flags; \
69 addrtype physaddr; \
70 }; \
71 \
72 struct arch ## _vpg_tlb_entry { \
73 uint8_t valid; \
74 uint8_t writeflag; \
75 addrtype vaddr_page; \
76 addrtype paddr_page; \
77 unsigned char *host_page; \
78 int64_t timestamp; \
79 };
80
81 #define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \
82 struct arch ## _l3_64_table { \
83 unsigned char *host_load[1 << ARCH ## _L3N]; \
84 unsigned char *host_store[1 << ARCH ## _L3N]; \
85 uint64_t phys_addr[1 << ARCH ## _L3N]; \
86 tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \
87 struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \
88 struct arch ## _l3_64_table *next; \
89 int refcount; \
90 }; \
91 struct arch ## _l2_64_table { \
92 struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \
93 struct arch ## _l2_64_table *next; \
94 int refcount; \
95 };
96
97 /*
98 * Dyntrans "Instruction Translation Cache":
99 *
100 * cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to
101 * be the same as cur_ic_page, because all the instrcalls should be placed
102 * first in the physpage struct!)
103 *
104 * cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE
105 * instruction call entries.
106 *
107 * next_ic points to the next such instruction call to be executed.
108 *
109 * combination_check, when set to non-NULL, is executed automatically after
110 * an instruction has been translated. (It check for combinations of
111 * instructions; low_addr is the offset of the translated instruction in the
112 * current page, NOT shifted right.)
113 */
114 #define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \
115 struct arch ## _instr_call *cur_ic_page; \
116 struct arch ## _instr_call *next_ic; \
117 void (*combination_check)(struct cpu *, \
118 struct arch ## _instr_call *, int low_addr);
119
120 /*
121 * Virtual -> physical -> host address translation TLB entries:
122 * ------------------------------------------------------------
123 *
124 * Regardless of whether 32-bit or 64-bit address translation is used, the
125 * same TLB entry structure is used.
126 */
127 #define VPH_TLBS(arch,ARCH) \
128 struct arch ## _vpg_tlb_entry \
129 vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES];
130
131 /*
132 * 32-bit dyntrans emulated Virtual -> physical -> host address translation:
133 * -------------------------------------------------------------------------
134 *
135 * This stuff assumes that 4 KB pages are used. 20 bits to select a page
136 * means just 1 M entries needed. This is small enough that a couple of
137 * full-size tables can fit in virtual memory on modern hosts (both 32-bit
138 * and 64-bit hosts). :-)
139 *
140 * Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t)
141 * or VPH32(sparc,SPARC,uint64_t,uint16_t)
142 *
143 * The vph_tlb_entry entries are cpu dependent tlb entries.
144 *
145 * The host_load and host_store entries point to host pages; the phys_addr
146 * entries are uint32_t or uint64_t (emulated physical addresses).
147 *
148 * phys_page points to translation cache physpages.
149 *
150 * phystranslation is a bitmap which tells us whether a physical page has
151 * a code translation.
152 *
153 * vaddr_to_tlbindex is a virtual address to tlb index hint table.
154 * The values in this array are the tlb index plus 1, so a value of, say,
155 * 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
156 * is not a valid index. (I.e. no hit.)
157 */
158 #define N_VPH32_ENTRIES 1048576
159 #define VPH32(arch,ARCH,paddrtype,tlbindextype) \
160 unsigned char *host_load[N_VPH32_ENTRIES]; \
161 unsigned char *host_store[N_VPH32_ENTRIES]; \
162 paddrtype phys_addr[N_VPH32_ENTRIES]; \
163 struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \
164 uint32_t phystranslation[N_VPH32_ENTRIES/32]; \
165 tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES];
166
167 /*
168 * 64-bit dyntrans emulated Virtual -> physical -> host address translation:
169 * -------------------------------------------------------------------------
170 *
171 * Usage: e.g. VPH64(alpha,ALPHA,uint8_t)
172 * or VPH64(sparc,SPARC,uint16_t)
173 *
174 * l1_64 is an array containing poiners to l2 tables.
175 *
176 * l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL
177 * pointers in l1_64 for unused slots, a pointer to the dummy table can be
178 * used.
179 */
180 #define DYNTRANS_L1N 17
181 #define VPH64(arch,ARCH,tlbindextype) \
182 struct arch ## _l3_64_table *l3_64_dummy; \
183 struct arch ## _l3_64_table *next_free_l3; \
184 struct arch ## _l2_64_table *l2_64_dummy; \
185 struct arch ## _l2_64_table *next_free_l2; \
186 struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N];
187
188
189 /* Include all CPUs' header files here: */
190 #include "cpu_alpha.h"
191 #include "cpu_arm.h"
192 #include "cpu_avr.h"
193 #include "cpu_hppa.h"
194 #include "cpu_i960.h"
195 #include "cpu_ia64.h"
196 #include "cpu_m68k.h"
197 #include "cpu_mips.h"
198 #include "cpu_ppc.h"
199 #include "cpu_sh.h"
200 #include "cpu_sparc.h"
201 #include "cpu_x86.h"
202
203 struct cpu;
204 struct emul;
205 struct machine;
206 struct memory;
207
208
209 struct cpu_family {
210 struct cpu_family *next;
211 int arch;
212
213 /* These are filled in by each CPU family's init function: */
214 char *name;
215 int (*cpu_new)(struct cpu *cpu, struct memory *mem,
216 struct machine *machine,
217 int cpu_id, char *cpu_type_name);
218 void (*list_available_types)(void);
219 void (*register_match)(struct machine *m,
220 char *name, int writeflag,
221 uint64_t *valuep, int *match_register);
222 int (*disassemble_instr)(struct cpu *cpu,
223 unsigned char *instr, int running,
224 uint64_t dumpaddr);
225 void (*register_dump)(struct cpu *cpu,
226 int gprs, int coprocs);
227 int (*run)(struct emul *emul,
228 struct machine *machine);
229 void (*dumpinfo)(struct cpu *cpu);
230 void (*tlbdump)(struct machine *m, int x,
231 int rawflag);
232 int (*interrupt)(struct cpu *cpu, uint64_t irq_nr);
233 int (*interrupt_ack)(struct cpu *cpu,
234 uint64_t irq_nr);
235 void (*functioncall_trace)(struct cpu *,
236 uint64_t f, int n_args);
237 char *(*gdb_stub)(struct cpu *, char *cmd);
238 };
239
240
241 /*
242 * More dyntrans stuff:
243 *
244 * The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
245 * into the cache, for possible translation cache structs for physical pages.
246 */
247
248 /* Physpage flags: */
249 #define TRANSLATIONS 1
250 #define COMBINATIONS 2
251
252 /* Meaning of delay_slot: */
253 #define NOT_DELAYED 0
254 #define DELAYED 1
255 #define TO_BE_DELAYED 2
256 #define EXCEPTION_IN_DELAY_SLOT 0x100
257
258 #define N_SAFE_DYNTRANS_LIMIT_SHIFT 14
259 #define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)
260
261 #define DYNTRANS_CACHE_SIZE (16*1048576)
262 #define DYNTRANS_CACHE_MARGIN 300000
263
264 #define N_BASE_TABLE_ENTRIES 32768
265 #define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1))
266
267
268 /*
269 * The generic CPU struct:
270 */
271
272 struct cpu {
273 /* Pointer back to the machine this CPU is in: */
274 struct machine *machine;
275
276 int byte_order;
277 int running;
278 int dead;
279 int bootstrap_cpu_flag;
280 int cpu_id;
281 int is_32bit; /* 0 for 64-bit, 1 for 32-bit */
282 char *name;
283
284 struct memory *mem;
285 int (*memory_rw)(struct cpu *cpu,
286 struct memory *mem, uint64_t vaddr,
287 unsigned char *data, size_t len,
288 int writeflag, int cache_flags);
289 int (*translate_address)(struct cpu *, uint64_t vaddr,
290 uint64_t *return_addr, int flags);
291 void (*update_translation_table)(struct cpu *,
292 uint64_t vaddr_page, unsigned char *host_page,
293 int writeflag, uint64_t paddr_page);
294 void (*invalidate_translation_caches)(struct cpu *,
295 uint64_t paddr, int flags);
296 void (*invalidate_code_translation)(struct cpu *,
297 uint64_t paddr, int flags);
298 void (*useremul_syscall)(struct cpu *cpu, uint32_t code);
299 int (*instruction_has_delayslot)(struct cpu *cpu,
300 unsigned char *ib);
301
302 uint64_t pc;
303
304 int trace_tree_depth;
305
306 /*
307 * Dynamic translation:
308 */
309 int running_translated;
310 int n_translated_instrs;
311 unsigned char *translation_cache;
312 size_t translation_cache_cur_ofs;
313
314 uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */
315 int delay_slot;
316
317 /*
318 * CPU-family dependent:
319 */
320 union {
321 struct alpha_cpu alpha;
322 struct arm_cpu arm;
323 struct avr_cpu avr;
324 struct hppa_cpu hppa;
325 struct i960_cpu i960;
326 struct ia64_cpu ia64;
327 struct m68k_cpu m68k;
328 struct mips_cpu mips;
329 struct ppc_cpu ppc;
330 struct sh_cpu sh;
331 struct sparc_cpu sparc;
332 struct x86_cpu x86;
333 } cd;
334 };
335
336
337 /* cpu.c: */
338 struct cpu *cpu_new(struct memory *mem, struct machine *machine,
339 int cpu_id, char *cpu_type_name);
340 void cpu_tlbdump(struct machine *m, int x, int rawflag);
341 void cpu_register_match(struct machine *m, char *name,
342 int writeflag, uint64_t *valuep, int *match_register);
343 void cpu_register_dump(struct machine *m, struct cpu *cpu,
344 int gprs, int coprocs);
345 int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
346 unsigned char *instr, int running, uint64_t addr);
347 char *cpu_gdb_stub(struct cpu *cpu, char *cmd);
348 int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
349 int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
350 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
351 void cpu_functioncall_trace_return(struct cpu *cpu);
352 void cpu_create_or_reset_tc(struct cpu *cpu);
353 void cpu_run_init(struct machine *machine);
354 int cpu_run(struct emul *emul, struct machine *machine);
355 void cpu_run_deinit(struct machine *machine);
356 void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
357 void cpu_list_available_types(void);
358 void cpu_show_cycles(struct machine *machine, int forced);
359 struct cpu_family *cpu_family_ptr_by_number(int arch);
360 void cpu_init(void);
361
362
363 #define JUST_MARK_AS_NON_WRITABLE 1
364 #define INVALIDATE_ALL 2
365 #define INVALIDATE_PADDR 4
366 #define INVALIDATE_VADDR 8
367 #define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */
368
369 #define TLB_CODE 0x02
370
371
372 #define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
373 struct cpu_family *fp) { \
374 /* Fill in the cpu_family struct with valid data for this arch. */ \
375 fp->name = s; \
376 fp->cpu_new = n ## _cpu_new; \
377 fp->list_available_types = n ## _cpu_list_available_types; \
378 fp->register_match = n ## _cpu_register_match; \
379 fp->disassemble_instr = n ## _cpu_disassemble_instr; \
380 fp->register_dump = n ## _cpu_register_dump; \
381 fp->run = n ## _cpu_run; \
382 fp->dumpinfo = n ## _cpu_dumpinfo; \
383 fp->interrupt = n ## _cpu_interrupt; \
384 fp->interrupt_ack = n ## _cpu_interrupt_ack; \
385 fp->functioncall_trace = n ## _cpu_functioncall_trace; \
386 fp->gdb_stub = n ## _cpu_gdb_stub; \
387 fp->tlbdump = n ## _cpu_tlbdump; \
388 return 1; \
389 }
390
391
392 #endif /* CPU_H */

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