28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu.h,v 1.128 2007/06/14 04:53:14 debug Exp $ |
* $Id: cpu.h,v 1.143 2007/08/29 20:36:49 debug Exp $ |
32 |
* |
* |
33 |
* CPU-related definitions. |
* CPU-related definitions. |
34 |
*/ |
*/ |
47 |
/* |
/* |
48 |
* Dyntrans misc declarations, used throughout the dyntrans code. |
* Dyntrans misc declarations, used throughout the dyntrans code. |
49 |
* |
* |
50 |
* Note that there is space for all instruction calls within a page, |
* Note that there is space for all instruction calls within a page, and then |
51 |
* and then 2 more. The first one of these "extra" instruction slots is |
* two more. The first one of these "extra" instruction slots is the end-of- |
52 |
* the end-of-page slot. It transfers control to the first instruction |
* page slot. It transfers control to the first instruction slot on the next |
53 |
* slot on the next (virtual) page. |
* (virtual) page. |
54 |
* |
* |
55 |
* The second of these extra instruction slots is an additional |
* The second of these extra instruction slots is an additional end-of-page |
56 |
* end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch |
* slot for delay-slot architectures. On e.g. MIPS, a branch instruction can |
57 |
* instruction can "nullify" (skip) the delay-slot. If the end-of-page |
* "nullify" (skip) the delay-slot. If the end-of-page slot is skipped, then |
58 |
* slot is skipped, then we end up one step after that. That's where the |
* we end up one step after that. That's where the end_of_page2 slot is. :) |
59 |
* end_of_page2 slot is. :) |
* |
60 |
* |
* next_ofs points to the next page in a chain of possible pages. (Several |
61 |
* next_ofs points to the next page in a chain of possible pages. |
* pages can be in the same chain, but only one matches the specific physaddr.) |
62 |
* (several pages can be in the same chain, but only one matches the |
* |
63 |
* specific physaddr.) |
* translations_bitmap is a tiny bitmap indicating which parts of the page have |
64 |
* |
* actual translations. Bit 0 corresponds to the lowest 1/32th of the page, bit |
65 |
* translations is a tiny bitmap indicating which parts of the page have |
* 1 to the second-lowest 1/32th, and so on. This speeds up page invalidations, |
66 |
* actual translations. Bit 0 corresponds to the lowest 1/32th of the page, |
* since only part of the page need to be reset. |
67 |
* bit 1 to the second-lowest 1/32th, and so on. This speeds up page |
* |
68 |
* invalidations, since only part of the page need to be reset. |
* translation_ranges_ofs is an offset within the translation cache to a short |
69 |
|
* list of ranges for this physpage which contain code. The list is of fixed |
70 |
|
* length; to extend the list, the list should be made to point to another |
71 |
|
* list, and so forth. (Bad, O(n) find/insert complexity. Should be fixed some |
72 |
|
* day. TODO) See definition of physpage_ranges below. |
73 |
*/ |
*/ |
74 |
#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
75 |
arch ## _instr_call { \ |
arch ## _instr_call { \ |
81 |
struct arch ## _tc_physpage { \ |
struct arch ## _tc_physpage { \ |
82 |
struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\ |
struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\ |
83 |
uint32_t next_ofs; /* (0 for end of chain) */ \ |
uint32_t next_ofs; /* (0 for end of chain) */ \ |
84 |
uint32_t translations; \ |
uint32_t translations_bitmap; \ |
85 |
|
uint32_t translation_ranges_ofs; \ |
86 |
addrtype physaddr; \ |
addrtype physaddr; \ |
87 |
}; \ |
}; \ |
88 |
\ |
\ |
110 |
int refcount; \ |
int refcount; \ |
111 |
}; |
}; |
112 |
|
|
113 |
|
|
114 |
|
/* |
115 |
|
* This structure contains a list of ranges within an emulated |
116 |
|
* physical page that contain translatable code. |
117 |
|
*/ |
118 |
|
#define PHYSPAGE_RANGES_ENTRIES_PER_LIST 20 |
119 |
|
struct physpage_ranges { |
120 |
|
uint32_t next_ofs; /* 0 for end of chain */ |
121 |
|
uint32_t n_entries_used; |
122 |
|
uint16_t base[PHYSPAGE_RANGES_ENTRIES_PER_LIST]; |
123 |
|
uint16_t length[PHYSPAGE_RANGES_ENTRIES_PER_LIST]; |
124 |
|
uint16_t count[PHYSPAGE_RANGES_ENTRIES_PER_LIST]; |
125 |
|
}; |
126 |
|
|
127 |
|
|
128 |
/* |
/* |
129 |
* Dyntrans "Instruction Translation Cache": |
* Dyntrans "Instruction Translation Cache": |
130 |
* |
* |
233 |
/* Include all CPUs' header files here: */ |
/* Include all CPUs' header files here: */ |
234 |
#include "cpu_alpha.h" |
#include "cpu_alpha.h" |
235 |
#include "cpu_arm.h" |
#include "cpu_arm.h" |
236 |
|
#include "cpu_m32r.h" |
237 |
#include "cpu_m88k.h" |
#include "cpu_m88k.h" |
238 |
#include "cpu_mips.h" |
#include "cpu_mips.h" |
239 |
#include "cpu_ppc.h" |
#include "cpu_ppc.h" |
314 |
#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14 |
#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14 |
315 |
#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1) |
#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1) |
316 |
|
|
317 |
#define MAX_DYNTRANS_READAHEAD 1024 |
#define MAX_DYNTRANS_READAHEAD 128 |
318 |
|
|
319 |
#define DEFAULT_DYNTRANS_CACHE_SIZE (48*1048576) |
#define DEFAULT_DYNTRANS_CACHE_SIZE (48*1048576) |
320 |
#define DYNTRANS_CACHE_MARGIN 200000 |
#define DYNTRANS_CACHE_MARGIN 200000 |
322 |
#define N_BASE_TABLE_ENTRIES 65536 |
#define N_BASE_TABLE_ENTRIES 65536 |
323 |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
324 |
|
|
|
#define CPU_SAMPLE_TIMER_HZ TIMER_BASE_FREQUENCY |
|
|
#define N_PADDR_SAMPLES 64 |
|
|
|
|
325 |
|
|
326 |
/* |
/* |
327 |
* The generic CPU struct: |
* The generic CPU struct: |
337 |
/* CPU-specific name, e.g. "R2000", "21164PC", etc. */ |
/* CPU-specific name, e.g. "R2000", "21164PC", etc. */ |
338 |
char *name; |
char *name; |
339 |
|
|
340 |
/* Full "path" to the CPU, e.g. "emul[0].machine[0].cpu[0]": */ |
/* Full "path" to the CPU, e.g. "machine[0].cpu[0]": */ |
341 |
char *path; |
char *path; |
342 |
|
|
343 |
/* Nr of instructions executed, etc.: */ |
/* Nr of instructions executed, etc.: */ |
347 |
int64_t ninstrs_since_gettimeofday; |
int64_t ninstrs_since_gettimeofday; |
348 |
struct timeval starttime; |
struct timeval starttime; |
349 |
|
|
|
/* |
|
|
* Periodic sampling of the physical address corresponding to the |
|
|
* emulated program counter: |
|
|
* |
|
|
* (Used to decide whether or not native code generation is worth |
|
|
* the effort.) |
|
|
*/ |
|
|
struct timer *sampling_timer; |
|
|
uint8_t sampling; /* 1 = turned on */ |
|
|
int16_t sampling_curindex; |
|
|
uint64_t *sampling_paddr; |
|
|
|
|
350 |
/* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */ |
/* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */ |
351 |
uint8_t byte_order; |
uint8_t byte_order; |
352 |
|
|
425 |
* ahead of the current (emulated) instruction pointer. |
* ahead of the current (emulated) instruction pointer. |
426 |
*/ |
*/ |
427 |
|
|
|
/* Non-zero when translating ahead of the current instruction: */ |
|
428 |
int translation_readahead; |
int translation_readahead; |
429 |
|
|
430 |
/* Instruction translation cache: */ |
/* Instruction translation cache: */ |
443 |
union { |
union { |
444 |
struct alpha_cpu alpha; |
struct alpha_cpu alpha; |
445 |
struct arm_cpu arm; |
struct arm_cpu arm; |
446 |
|
struct m32r_cpu m32r; |
447 |
struct m88k_cpu m88k; |
struct m88k_cpu m88k; |
448 |
struct mips_cpu mips; |
struct mips_cpu mips; |
449 |
struct ppc_cpu ppc; |
struct ppc_cpu ppc; |