/[gxemul]/trunk/src/include/cpu.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/src/include/cpu.h

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 20 by dpavlin, Mon Oct 8 16:19:23 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define CPU_H  #define CPU_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu.h,v 1.54 2005/11/16 21:15:19 debug Exp $   *  $Id: cpu.h,v 1.62 2006/02/09 22:40:27 debug Exp $
32   *   *
33   *  See cpu.c.   *  CPU-related definitions.
34   */   */
35    
36    
# Line 38  Line 38 
38  #include <inttypes.h>  #include <inttypes.h>
39  #include <sys/time.h>  #include <sys/time.h>
40    
41  /*  This is needed for undefining 'mips' or 'ppc', on weird systems:  */  /*  This is needed for undefining 'mips', 'ppc' etc. on weird systems:  */
42  #include "../../config.h"  #include "../../config.h"
43    
44    /*
45     *  Dyntrans misc declarations, used throughout the dyntrans code.
46     */
47    #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype)  struct \
48            arch ## _instr_call {                                   \
49                    void    (*f)(struct cpu *, struct arch ## _instr_call *); \
50                    size_t  arg[ARCH ## _N_IC_ARGS];                        \
51            };                                                              \
52                                                                            \
53            /*  Translation cache struct for each physical page:  */        \
54            struct arch ## _tc_physpage {                                   \
55                    struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+1];\
56                    uint32_t        next_ofs;       /*  (0 for end of chain)  */ \
57                    int             flags;                                  \
58                    addrtype        physaddr;                               \
59            };                                                              \
60                                                                            \
61            struct arch ## _vpg_tlb_entry {                                 \
62                    uint8_t         valid;                                  \
63                    uint8_t         writeflag;                              \
64                    addrtype        vaddr_page;                             \
65                    addrtype        paddr_page;                             \
66                    unsigned char   *host_page;                             \
67                    int64_t         timestamp;                              \
68            };
69    
70    /*
71     *  Dyntrans "Instruction Translation Cache":
72     *
73     *  cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to
74     *  be the same as cur_ic_page, because all the instrcalls should be placed
75     *  first in the physpage struct!)
76     *
77     *  cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE
78     *  instruction call entries.
79     *
80     *  next_ic points to the next such instruction call to be executed.
81     *
82     *  combination_check, when set to non-NULL, is executed automatically after
83     *  an instruction has been translated. (It check for combinations of
84     *  instructions; low_addr is the offset of the translated instruction in the
85     *  current page, NOT shifted right.)
86     */
87    #define DYNTRANS_ITC(arch)      struct arch ## _tc_physpage *cur_physpage;  \
88                                    struct arch ## _instr_call  *cur_ic_page;   \
89                                    struct arch ## _instr_call  *next_ic;       \
90                                    void (*combination_check)(struct cpu *,     \
91                                        struct arch ## _instr_call *, int low_addr);
92    
93    /*
94     *  Virtual -> physical -> host address translation TLB entries:
95     *  ------------------------------------------------------------
96     *
97     *  Regardless of whether 32-bit or 64-bit address translation is used, the
98     *  same TLB entry structure is used.
99     */
100    #define VPH_TLBS(arch,ARCH)                                             \
101            struct arch ## _vpg_tlb_entry                                   \
102                vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES];
103    
104    /*
105     *  32-bit dyntrans emulated Virtual -> physical -> host address translation:
106     *  -------------------------------------------------------------------------
107     *
108     *  This stuff assumes that 4 KB pages are used. 20 bits to select a page
109     *  means just 1 M entries needed. This is small enough that a couple of
110     *  full-size tables can fit in virtual memory on modern hosts (both 32-bit
111     *  and 64-bit hosts). :-)
112     *
113     *  Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t)
114     *           or VPH32(sparc,SPARC,uint64_t,uint16_t)
115     *
116     *  The vph_tlb_entry entries are cpu dependent tlb entries.
117     *
118     *  The host_load and host_store entries point to host pages; the phys_addr
119     *  entries are uint32_t or uint64_t (emulated physical addresses).
120     *
121     *  phys_page points to translation cache physpages.
122     *
123     *  phystranslation is a bitmap which tells us whether a physical page has
124     *  a code translation.
125     *
126     *  vaddr_to_tlbindex is a virtual address to tlb index hint table.
127     *  The values in this array are the tlb index plus 1, so a value of, say,
128     *  3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
129     *  is not a valid index. (I.e. no hit.)
130     */
131    #define N_VPH32_ENTRIES         1048576
132    #define VPH32(arch,ARCH,paddrtype,tlbindextype)                         \
133            unsigned char           *host_load[N_VPH32_ENTRIES];            \
134            unsigned char           *host_store[N_VPH32_ENTRIES];           \
135            paddrtype               phys_addr[N_VPH32_ENTRIES];             \
136            struct arch ## _tc_physpage  *phys_page[N_VPH32_ENTRIES];       \
137            uint32_t                phystranslation[N_VPH32_ENTRIES/32];    \
138            tlbindextype            vaddr_to_tlbindex[N_VPH32_ENTRIES];
139    
140    /*
141     *  64-bit dyntrans emulated Virtual -> physical -> host address translation:
142     *  -------------------------------------------------------------------------
143     *
144     *  Usage: e.g. VPH64(alpha,ALPHA,uint8_t)
145     *           or VPH64(sparc,SPARC,uint16_t)
146     *
147     *  TODO
148     */
149    #define VPH64(arch,ARCH,tlbindextype)                   \
150            int dummy;
151    
152  #include "cpu_alpha.h"  #include "cpu_alpha.h"
153  #include "cpu_arm.h"  #include "cpu_arm.h"
154  #include "cpu_avr.h"  #include "cpu_avr.h"
# Line 49  Line 157 
157  #include "cpu_ia64.h"  #include "cpu_ia64.h"
158  #include "cpu_m68k.h"  #include "cpu_m68k.h"
159  #include "cpu_mips.h"  #include "cpu_mips.h"
 #include "cpu_newmips.h"  
160  #include "cpu_ppc.h"  #include "cpu_ppc.h"
161  #include "cpu_sh.h"  #include "cpu_sh.h"
162  #include "cpu_sparc.h"  #include "cpu_sparc.h"
# Line 92  struct cpu_family { Line 199  struct cpu_family {
199                                      uint64_t f, int n_args);                                      uint64_t f, int n_args);
200  };  };
201    
 #ifdef TRACE_NULL_CRASHES  
 #define TRACE_NULL_N_ENTRIES            16  
 #endif  
   
202    
203  /*  /*
204   *  Dynamic translation definitions:   *  More dyntrans stuff:
205   *   *
206   *  The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets   *  The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
207   *  into the cache, for possible translation cache structs for physical pages.   *  into the cache, for possible translation cache structs for physical pages.
# Line 108  struct cpu_family { Line 211  struct cpu_family {
211  #define TRANSLATIONS                    1  #define TRANSLATIONS                    1
212  #define COMBINATIONS                    2  #define COMBINATIONS                    2
213    
214  #define DYNTRANS_CACHE_SIZE             (20*1048576)  #define DYNTRANS_CACHE_SIZE             (16*1048576)
215  #define DYNTRANS_CACHE_MARGIN           300000  #define DYNTRANS_CACHE_MARGIN           300000
216    
217  #define N_BASE_TABLE_ENTRIES            32768  #define N_BASE_TABLE_ENTRIES            32768
218  #define PAGENR_TO_TABLE_INDEX(a)        ((a) & (N_BASE_TABLE_ENTRIES-1))  #define PAGENR_TO_TABLE_INDEX(a)        ((a) & (N_BASE_TABLE_ENTRIES-1))
219    
220    
221    #ifdef DYNTRANS_BACKEND
222    
223    /*  TODO: convert this into a fixed-size array? Might increase performace.  */
224    struct dtb_fixup {
225            struct dtb_fixup        *next;
226            int                     type;   /*  Fixup type [optional]  */
227            void                    *addr;  /*  Address of the instruction
228                                                (in host memory)  */
229            size_t                  data;   /*  Emulation data.  */
230    };
231    
232    struct translation_context {
233            /*  Current address of where to emit host instructions:  */
234            /*  (NULL means no translation is currently being done.)  */
235            void                    *p;
236    
237            /*  index of the instr_call of the first translated instruction:  */
238            void                    *ic_page;
239            int                     start_instr_call_index;
240    
241            /*  Fixups needed after first translation pass:  */
242            struct dtb_fixup        *fixups;
243    
244            int                     n_simple;
245    
246            /*  translation_buffer should have room for max_size bytes,
247                plus some margin.  */
248            unsigned char           *translation_buffer;
249            size_t                  cur_size;
250    };
251    
252    #define DTB_TRANSLATION_SIZE_MAX        3072
253    #define DTB_TRANSLATION_SIZE_MARGIN     1024
254    
255    void cpu_dtb_add_fixup(struct cpu *cpu, int type, void *addr, size_t data);
256    void cpu_dtb_do_fixups(struct cpu *cpu);
257    
258    void dtb_host_cacheinvalidate(void *p, size_t len);
259    int dtb_function_prologue(struct translation_context *ctx, size_t *sizep);
260    int dtb_function_epilogue(struct translation_context *ctx, size_t *sizep);
261    int dtb_generate_fcall(struct cpu *cpu, struct translation_context *ctx,
262            size_t *sizep, size_t f, size_t instr_call_ptr);
263    int dtb_generate_ptr_inc(struct cpu *cpu, struct translation_context *ctx,
264            size_t *sizep, void *ptr, int amount);
265    
266    #endif  /*  DYNTRANS_BACKEND  */
267    
268    
269    
270  /*  /*
271   *  The generic CPU struct:   *  The generic CPU struct:
272   */   */
# Line 164  struct cpu { Line 316  struct cpu {
316          int             n_translated_instrs;          int             n_translated_instrs;
317          unsigned char   *translation_cache;          unsigned char   *translation_cache;
318          size_t          translation_cache_cur_ofs;          size_t          translation_cache_cur_ofs;
319    #ifdef DYNTRANS_BACKEND
320            struct translation_context translation_context;
321    #endif
322    
323          /*          /*
324           *  CPU-family dependent:           *  CPU-family dependent:
# Line 177  struct cpu { Line 332  struct cpu {
332                  struct ia64_cpu    ia64;                  struct ia64_cpu    ia64;
333                  struct m68k_cpu    m68k;                  struct m68k_cpu    m68k;
334                  struct mips_cpu    mips;                  struct mips_cpu    mips;
                 struct newmips_cpu newmips;  
335                  struct ppc_cpu     ppc;                  struct ppc_cpu     ppc;
336                  struct sh_cpu      sh;                  struct sh_cpu      sh;
337                  struct sparc_cpu   sparc;                  struct sparc_cpu   sparc;
# Line 216  void cpu_init(void); Line 370  void cpu_init(void);
370  #define INVALIDATE_ALL                  2  #define INVALIDATE_ALL                  2
371  #define INVALIDATE_PADDR                4  #define INVALIDATE_PADDR                4
372  #define INVALIDATE_VADDR                8  #define INVALIDATE_VADDR                8
373    #define INVALIDATE_VADDR_UPPER4         16      /*  useful for PPC emulation  */
374    
375  #define TLB_CODE                        0x02  #define TLB_CODE                        0x02
376    
# Line 246  void cpu_init(void); Line 401  void cpu_init(void);
401          fp->register_match = n ## _cpu_register_match;                  \          fp->register_match = n ## _cpu_register_match;                  \
402          fp->disassemble_instr = n ## _cpu_disassemble_instr;            \          fp->disassemble_instr = n ## _cpu_disassemble_instr;            \
403          fp->register_dump = n ## _cpu_register_dump;                    \          fp->register_dump = n ## _cpu_register_dump;                    \
404          fp->run = n ## _cpu_run;                                        \          fp->run = n ## _OLD_cpu_run;                                    \
405          fp->dumpinfo = n ## _cpu_dumpinfo;                              \          fp->dumpinfo = n ## _cpu_dumpinfo;                              \
406          fp->show_full_statistics = n ## _cpu_show_full_statistics;      \          fp->show_full_statistics = n ## _cpu_show_full_statistics;      \
407          fp->tlbdump = n ## _cpu_tlbdump;                                \          fp->tlbdump = n ## _cpu_tlbdump;                                \

Legend:
Removed from v.20  
changed lines
  Added in v.22

  ViewVC Help
Powered by ViewVC 1.1.26