2 |
#define CPU_H |
#define CPU_H |
3 |
|
|
4 |
/* |
/* |
5 |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
6 |
* |
* |
7 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
8 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu.h,v 1.90 2006/08/12 11:43:13 debug Exp $ |
* $Id: cpu.h,v 1.143 2007/08/29 20:36:49 debug Exp $ |
32 |
* |
* |
33 |
* CPU-related definitions. |
* CPU-related definitions. |
34 |
*/ |
*/ |
41 |
/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */ |
/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */ |
42 |
#include "../../config.h" |
#include "../../config.h" |
43 |
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44 |
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#include "timer.h" |
45 |
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46 |
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47 |
/* |
/* |
48 |
* Dyntrans misc declarations, used throughout the dyntrans code. |
* Dyntrans misc declarations, used throughout the dyntrans code. |
49 |
* |
* |
50 |
* Note that there is place for all instruction calls within a page, |
* Note that there is space for all instruction calls within a page, and then |
51 |
* and then 2 more. The first one of these "extra" instruction slots is |
* two more. The first one of these "extra" instruction slots is the end-of- |
52 |
* the end-of-page slot. It transfers control to the first instruction |
* page slot. It transfers control to the first instruction slot on the next |
53 |
* slot on the next (virtual) page. |
* (virtual) page. |
54 |
* |
* |
55 |
* The second of these extra instruction slots is an additional |
* The second of these extra instruction slots is an additional end-of-page |
56 |
* end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch |
* slot for delay-slot architectures. On e.g. MIPS, a branch instruction can |
57 |
* instruction can "nullify" (skip) the delay-slot. If the end-of-page |
* "nullify" (skip) the delay-slot. If the end-of-page slot is skipped, then |
58 |
* slot is skipped, then we end up one step after that. That's where the |
* we end up one step after that. That's where the end_of_page2 slot is. :) |
59 |
* end_of_page2 slot is. :) |
* |
60 |
* |
* next_ofs points to the next page in a chain of possible pages. (Several |
61 |
* next_ofs points to the next page in a chain of possible pages. |
* pages can be in the same chain, but only one matches the specific physaddr.) |
62 |
* (several pages can be in the same chain, but only one matches the |
* |
63 |
* specific physaddr.) |
* translations_bitmap is a tiny bitmap indicating which parts of the page have |
64 |
* |
* actual translations. Bit 0 corresponds to the lowest 1/32th of the page, bit |
65 |
* translations is a tiny bitmap indicating which parts of the page have |
* 1 to the second-lowest 1/32th, and so on. This speeds up page invalidations, |
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* actual translations. Bit 0 corresponds to the lowest 1/32th of the page, |
* since only part of the page need to be reset. |
67 |
* bit 1 to the second-lowest 1/32th, and so on. |
* |
68 |
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* translation_ranges_ofs is an offset within the translation cache to a short |
69 |
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* list of ranges for this physpage which contain code. The list is of fixed |
70 |
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* length; to extend the list, the list should be made to point to another |
71 |
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* list, and so forth. (Bad, O(n) find/insert complexity. Should be fixed some |
72 |
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* day. TODO) See definition of physpage_ranges below. |
73 |
*/ |
*/ |
74 |
#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
75 |
arch ## _instr_call { \ |
arch ## _instr_call { \ |
81 |
struct arch ## _tc_physpage { \ |
struct arch ## _tc_physpage { \ |
82 |
struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\ |
struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\ |
83 |
uint32_t next_ofs; /* (0 for end of chain) */ \ |
uint32_t next_ofs; /* (0 for end of chain) */ \ |
84 |
uint32_t translations; \ |
uint32_t translations_bitmap; \ |
85 |
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uint32_t translation_ranges_ofs; \ |
86 |
addrtype physaddr; \ |
addrtype physaddr; \ |
87 |
}; \ |
}; \ |
88 |
\ |
\ |
110 |
int refcount; \ |
int refcount; \ |
111 |
}; |
}; |
112 |
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113 |
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114 |
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/* |
115 |
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* This structure contains a list of ranges within an emulated |
116 |
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* physical page that contain translatable code. |
117 |
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*/ |
118 |
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#define PHYSPAGE_RANGES_ENTRIES_PER_LIST 20 |
119 |
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struct physpage_ranges { |
120 |
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uint32_t next_ofs; /* 0 for end of chain */ |
121 |
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uint32_t n_entries_used; |
122 |
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uint16_t base[PHYSPAGE_RANGES_ENTRIES_PER_LIST]; |
123 |
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uint16_t length[PHYSPAGE_RANGES_ENTRIES_PER_LIST]; |
124 |
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uint16_t count[PHYSPAGE_RANGES_ENTRIES_PER_LIST]; |
125 |
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}; |
126 |
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127 |
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128 |
/* |
/* |
129 |
* Dyntrans "Instruction Translation Cache": |
* Dyntrans "Instruction Translation Cache": |
130 |
* |
* |
169 |
* full-size tables can fit in virtual memory on modern hosts (both 32-bit |
* full-size tables can fit in virtual memory on modern hosts (both 32-bit |
170 |
* and 64-bit hosts). :-) |
* and 64-bit hosts). :-) |
171 |
* |
* |
172 |
* Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t) |
* Usage: e.g. VPH32(arm,ARM) |
173 |
* or VPH32(sparc,SPARC,uint64_t,uint16_t) |
* or VPH32(sparc,SPARC) |
174 |
* |
* |
175 |
* The vph_tlb_entry entries are cpu dependent tlb entries. |
* The vph_tlb_entry entries are cpu dependent tlb entries. |
176 |
* |
* |
177 |
* The host_load and host_store entries point to host pages; the phys_addr |
* The host_load and host_store entries point to host pages; the phys_addr |
178 |
* entries are uint32_t or uint64_t (emulated physical addresses). |
* entries are uint32_t (emulated physical addresses). |
179 |
* |
* |
180 |
* phys_page points to translation cache physpages. |
* phys_page points to translation cache physpages. |
181 |
* |
* |
183 |
* The values in this array are the tlb index plus 1, so a value of, say, |
* The values in this array are the tlb index plus 1, so a value of, say, |
184 |
* 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which |
* 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which |
185 |
* is not a valid index. (I.e. no hit.) |
* is not a valid index. (I.e. no hit.) |
186 |
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* |
187 |
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* The VPH32EXTENDED variant adds an additional postfix to the array |
188 |
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* names. Used so far only for usermode addresses in M88K emulation. |
189 |
*/ |
*/ |
190 |
#define N_VPH32_ENTRIES 1048576 |
#define N_VPH32_ENTRIES 1048576 |
191 |
#define VPH32(arch,ARCH,paddrtype,tlbindextype) \ |
#define VPH32(arch,ARCH) \ |
192 |
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unsigned char *host_load[N_VPH32_ENTRIES]; \ |
193 |
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unsigned char *host_store[N_VPH32_ENTRIES]; \ |
194 |
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uint32_t phys_addr[N_VPH32_ENTRIES]; \ |
195 |
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struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
196 |
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uint8_t vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
197 |
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#define VPH32_16BITVPHENTRIES(arch,ARCH) \ |
198 |
unsigned char *host_load[N_VPH32_ENTRIES]; \ |
unsigned char *host_load[N_VPH32_ENTRIES]; \ |
199 |
unsigned char *host_store[N_VPH32_ENTRIES]; \ |
unsigned char *host_store[N_VPH32_ENTRIES]; \ |
200 |
paddrtype phys_addr[N_VPH32_ENTRIES]; \ |
uint32_t phys_addr[N_VPH32_ENTRIES]; \ |
201 |
struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
202 |
tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
uint16_t vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
203 |
|
#define VPH32EXTENDED(arch,ARCH,ex) \ |
204 |
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unsigned char *host_load_ ## ex[N_VPH32_ENTRIES]; \ |
205 |
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unsigned char *host_store_ ## ex[N_VPH32_ENTRIES]; \ |
206 |
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uint32_t phys_addr_ ## ex[N_VPH32_ENTRIES]; \ |
207 |
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struct arch ## _tc_physpage *phys_page_ ## ex[N_VPH32_ENTRIES];\ |
208 |
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uint8_t vaddr_to_tlbindex_ ## ex[N_VPH32_ENTRIES]; |
209 |
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210 |
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211 |
/* |
/* |
212 |
* 64-bit dyntrans emulated Virtual -> physical -> host address translation: |
* 64-bit dyntrans emulated Virtual -> physical -> host address translation: |
213 |
* ------------------------------------------------------------------------- |
* ------------------------------------------------------------------------- |
214 |
* |
* |
215 |
* Usage: e.g. VPH64(alpha,ALPHA,uint8_t) |
* Usage: e.g. VPH64(alpha,ALPHA) |
216 |
* or VPH64(sparc,SPARC,uint16_t) |
* or VPH64(sparc,SPARC) |
217 |
* |
* |
218 |
* l1_64 is an array containing poiners to l2 tables. |
* l1_64 is an array containing poiners to l2 tables. |
219 |
* |
* |
222 |
* used. |
* used. |
223 |
*/ |
*/ |
224 |
#define DYNTRANS_L1N 17 |
#define DYNTRANS_L1N 17 |
225 |
#define VPH64(arch,ARCH,tlbindextype) \ |
#define VPH64(arch,ARCH) \ |
226 |
struct arch ## _l3_64_table *l3_64_dummy; \ |
struct arch ## _l3_64_table *l3_64_dummy; \ |
227 |
struct arch ## _l3_64_table *next_free_l3; \ |
struct arch ## _l3_64_table *next_free_l3; \ |
228 |
struct arch ## _l2_64_table *l2_64_dummy; \ |
struct arch ## _l2_64_table *l2_64_dummy; \ |
233 |
/* Include all CPUs' header files here: */ |
/* Include all CPUs' header files here: */ |
234 |
#include "cpu_alpha.h" |
#include "cpu_alpha.h" |
235 |
#include "cpu_arm.h" |
#include "cpu_arm.h" |
236 |
#include "cpu_avr.h" |
#include "cpu_m32r.h" |
237 |
#include "cpu_hppa.h" |
#include "cpu_m88k.h" |
|
#include "cpu_i960.h" |
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#include "cpu_ia64.h" |
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#include "cpu_m68k.h" |
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238 |
#include "cpu_mips.h" |
#include "cpu_mips.h" |
239 |
#include "cpu_ppc.h" |
#include "cpu_ppc.h" |
240 |
#include "cpu_sh.h" |
#include "cpu_sh.h" |
241 |
#include "cpu_sparc.h" |
#include "cpu_sparc.h" |
|
#include "cpu_transputer.h" |
|
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#include "cpu_x86.h" |
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242 |
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243 |
struct cpu; |
struct cpu; |
244 |
struct emul; |
struct emul; |
245 |
struct machine; |
struct machine; |
246 |
struct memory; |
struct memory; |
247 |
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struct settings; |
248 |
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249 |
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250 |
/* |
/* |
275 |
/* List available CPU types for this architecture. */ |
/* List available CPU types for this architecture. */ |
276 |
void (*list_available_types)(void); |
void (*list_available_types)(void); |
277 |
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/* Read or write a CPU register, given a name. */ |
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void (*register_match)(struct machine *m, |
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char *name, int writeflag, |
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uint64_t *valuep, int *match_register); |
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278 |
/* Disassemble an instruction. */ |
/* Disassemble an instruction. */ |
279 |
int (*disassemble_instr)(struct cpu *cpu, |
int (*disassemble_instr)(struct cpu *cpu, |
280 |
unsigned char *instr, int running, |
unsigned char *instr, int running, |
291 |
void (*tlbdump)(struct machine *m, int x, |
void (*tlbdump)(struct machine *m, int x, |
292 |
int rawflag); |
int rawflag); |
293 |
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/* Assert an interrupt. */ |
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int (*interrupt)(struct cpu *cpu, uint64_t irq_nr); |
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/* De-assert an interrupt. */ |
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int (*interrupt_ack)(struct cpu *cpu, |
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uint64_t irq_nr); |
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294 |
/* Print architecture-specific function call arguments. |
/* Print architecture-specific function call arguments. |
295 |
(This is called for each function call, if running with -t.) */ |
(This is called for each function call, if running with -t.) */ |
296 |
void (*functioncall_trace)(struct cpu *, |
void (*functioncall_trace)(struct cpu *, |
297 |
uint64_t f, int n_args); |
uint64_t f, int n_args); |
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/* GDB command handler. */ |
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char *(*gdb_stub)(struct cpu *, char *cmd); |
|
298 |
}; |
}; |
299 |
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300 |
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314 |
#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14 |
#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14 |
315 |
#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1) |
#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1) |
316 |
|
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317 |
#define DYNTRANS_CACHE_SIZE (24*1048576) |
#define MAX_DYNTRANS_READAHEAD 128 |
318 |
#define DYNTRANS_CACHE_MARGIN 300000 |
|
319 |
|
#define DEFAULT_DYNTRANS_CACHE_SIZE (48*1048576) |
320 |
|
#define DYNTRANS_CACHE_MARGIN 200000 |
321 |
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322 |
#define N_BASE_TABLE_ENTRIES 32768 |
#define N_BASE_TABLE_ENTRIES 65536 |
323 |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
324 |
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325 |
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331 |
/* Pointer back to the machine this CPU is in: */ |
/* Pointer back to the machine this CPU is in: */ |
332 |
struct machine *machine; |
struct machine *machine; |
333 |
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334 |
|
/* Settings: */ |
335 |
|
struct settings *settings; |
336 |
|
|
337 |
/* CPU-specific name, e.g. "R2000", "21164PC", etc. */ |
/* CPU-specific name, e.g. "R2000", "21164PC", etc. */ |
338 |
char *name; |
char *name; |
339 |
|
|
340 |
/* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */ |
/* Full "path" to the CPU, e.g. "machine[0].cpu[0]": */ |
341 |
int byte_order; |
char *path; |
342 |
|
|
343 |
/* 0-based CPU id, in an emulated SMP system. */ |
/* Nr of instructions executed, etc.: */ |
344 |
int cpu_id; |
int64_t ninstrs; |
345 |
|
int64_t ninstrs_show; |
346 |
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int64_t ninstrs_flush; |
347 |
|
int64_t ninstrs_since_gettimeofday; |
348 |
|
struct timeval starttime; |
349 |
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350 |
|
/* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */ |
351 |
|
uint8_t byte_order; |
352 |
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353 |
/* 0 for emulated 64-bit CPUs, 1 for 32-bit. */ |
/* 0 for emulated 64-bit CPUs, 1 for 32-bit. */ |
354 |
int is_32bit; |
uint8_t is_32bit; |
355 |
|
|
356 |
/* 1 while running, 0 when paused/stopped. */ |
/* 1 while running, 0 when paused/stopped. */ |
357 |
int running; |
uint8_t running; |
358 |
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359 |
|
/* See comment further up. */ |
360 |
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uint8_t delay_slot; |
361 |
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362 |
|
/* 0-based CPU id, in an emulated SMP system. */ |
363 |
|
int cpu_id; |
364 |
|
|
365 |
/* A pointer to the main memory connected to this CPU. */ |
/* A pointer to the main memory connected to this CPU. */ |
366 |
struct memory *mem; |
struct memory *mem; |
386 |
/* The program counter. (For 32-bit modes, not all bits are used.) */ |
/* The program counter. (For 32-bit modes, not all bits are used.) */ |
387 |
uint64_t pc; |
uint64_t pc; |
388 |
|
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|
/* See comment further up. */ |
|
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int delay_slot; |
|
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|
|
389 |
/* The current depth of function call tracing. */ |
/* The current depth of function call tracing. */ |
390 |
int trace_tree_depth; |
int trace_tree_depth; |
391 |
|
|
393 |
* If is_halted is true when an interrupt trap occurs, the pointer |
* If is_halted is true when an interrupt trap occurs, the pointer |
394 |
* to the next instruction to execute will be the instruction |
* to the next instruction to execute will be the instruction |
395 |
* following the halt instruction, not the halt instrucion itself. |
* following the halt instruction, not the halt instrucion itself. |
396 |
|
* |
397 |
|
* If has_been_idling is true when printing the number of executed |
398 |
|
* instructions per second, "idling" is printed instead. (The number |
399 |
|
* of instrs per second when idling is meaningless anyway.) |
400 |
*/ |
*/ |
401 |
int is_halted; |
char is_halted; |
402 |
|
char has_been_idling; |
403 |
|
|
404 |
/* |
/* |
405 |
* Dynamic translation: |
* Dynamic translation: |
413 |
* Note that it can also be adjusted negatively, that is, the way |
* Note that it can also be adjusted negatively, that is, the way |
414 |
* to "get out" of a dyntrans loop is to set the current instruction |
* to "get out" of a dyntrans loop is to set the current instruction |
415 |
* call pointer to the "nothing" instruction. This instruction |
* call pointer to the "nothing" instruction. This instruction |
416 |
* _decreases_ n_translated_instrs. That way, once the dyntrans loop |
* _decreases_ n_translated_instrs by 1. That way, once the dyntrans |
417 |
* exits, only real instructions will be counted, and not the |
* loop exits, only real instructions will be counted, and not the |
418 |
* "nothing" instructions. |
* "nothing" instructions. |
419 |
|
* |
420 |
|
* The translation cache is a relative large chunk of memory (say, |
421 |
|
* 32 MB) which is used for translations. When it has been used up, |
422 |
|
* everything restarts from scratch. |
423 |
|
* |
424 |
|
* translation_readahead is non-zero when translating instructions |
425 |
|
* ahead of the current (emulated) instruction pointer. |
426 |
*/ |
*/ |
427 |
|
|
428 |
|
int translation_readahead; |
429 |
|
|
430 |
|
/* Instruction translation cache: */ |
431 |
int n_translated_instrs; |
int n_translated_instrs; |
432 |
unsigned char *translation_cache; |
unsigned char *translation_cache; |
433 |
size_t translation_cache_cur_ofs; |
size_t translation_cache_cur_ofs; |
434 |
|
|
435 |
|
|
436 |
/* |
/* |
437 |
* CPU-family dependent: |
* CPU-family dependent: |
438 |
* |
* |
439 |
* These contain everything ranging from registers, memory management, |
* These contain everything ranging from general purpose registers, |
440 |
* status words, etc. |
* control registers, memory management, status words, interrupt |
441 |
|
* specifics, etc. |
442 |
*/ |
*/ |
443 |
union { |
union { |
444 |
struct alpha_cpu alpha; |
struct alpha_cpu alpha; |
445 |
struct arm_cpu arm; |
struct arm_cpu arm; |
446 |
struct avr_cpu avr; |
struct m32r_cpu m32r; |
447 |
struct hppa_cpu hppa; |
struct m88k_cpu m88k; |
|
struct i960_cpu i960; |
|
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struct ia64_cpu ia64; |
|
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struct m68k_cpu m68k; |
|
448 |
struct mips_cpu mips; |
struct mips_cpu mips; |
449 |
struct ppc_cpu ppc; |
struct ppc_cpu ppc; |
450 |
struct sh_cpu sh; |
struct sh_cpu sh; |
451 |
struct sparc_cpu sparc; |
struct sparc_cpu sparc; |
|
struct transputer_cpu transputer; |
|
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struct x86_cpu x86; |
|
452 |
} cd; |
} cd; |
453 |
}; |
}; |
454 |
|
|
456 |
/* cpu.c: */ |
/* cpu.c: */ |
457 |
struct cpu *cpu_new(struct memory *mem, struct machine *machine, |
struct cpu *cpu_new(struct memory *mem, struct machine *machine, |
458 |
int cpu_id, char *cpu_type_name); |
int cpu_id, char *cpu_type_name); |
459 |
|
void cpu_destroy(struct cpu *cpu); |
460 |
|
|
461 |
void cpu_tlbdump(struct machine *m, int x, int rawflag); |
void cpu_tlbdump(struct machine *m, int x, int rawflag); |
|
void cpu_register_match(struct machine *m, char *name, |
|
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int writeflag, uint64_t *valuep, int *match_register); |
|
462 |
void cpu_register_dump(struct machine *m, struct cpu *cpu, |
void cpu_register_dump(struct machine *m, struct cpu *cpu, |
463 |
int gprs, int coprocs); |
int gprs, int coprocs); |
464 |
int cpu_disassemble_instr(struct machine *m, struct cpu *cpu, |
int cpu_disassemble_instr(struct machine *m, struct cpu *cpu, |
465 |
unsigned char *instr, int running, uint64_t addr); |
unsigned char *instr, int running, uint64_t addr); |
466 |
char *cpu_gdb_stub(struct cpu *cpu, char *cmd); |
|
|
int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
|
|
int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
|
467 |
void cpu_functioncall_trace(struct cpu *cpu, uint64_t f); |
void cpu_functioncall_trace(struct cpu *cpu, uint64_t f); |
468 |
void cpu_functioncall_trace_return(struct cpu *cpu); |
void cpu_functioncall_trace_return(struct cpu *cpu); |
469 |
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470 |
void cpu_create_or_reset_tc(struct cpu *cpu); |
void cpu_create_or_reset_tc(struct cpu *cpu); |
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472 |
void cpu_run_init(struct machine *machine); |
void cpu_run_init(struct machine *machine); |
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void cpu_run_deinit(struct machine *machine); |
void cpu_run_deinit(struct machine *machine); |
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475 |
void cpu_dumpinfo(struct machine *m, struct cpu *cpu); |
void cpu_dumpinfo(struct machine *m, struct cpu *cpu); |
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void cpu_list_available_types(void); |
void cpu_list_available_types(void); |
477 |
void cpu_show_cycles(struct machine *machine, int forced); |
void cpu_show_cycles(struct machine *machine, int forced); |
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struct cpu_family *cpu_family_ptr_by_number(int arch); |
struct cpu_family *cpu_family_ptr_by_number(int arch); |
480 |
void cpu_init(void); |
void cpu_init(void); |
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487 |
#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */ |
#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */ |
488 |
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489 |
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490 |
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/* Note: 64-bit processors running in 32-bit mode use a 32-bit |
491 |
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display format, even though the underlying data is 64-bits. */ |
492 |
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#define CPU_SETTINGS_ADD_REGISTER64(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT64, \ |
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cpu->is_32bit? SETTINGS_FORMAT_HEX32 : SETTINGS_FORMAT_HEX64, \ |
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(void *) &(var)); |
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#define CPU_SETTINGS_ADD_REGISTER32(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT32, \ |
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SETTINGS_FORMAT_HEX32, (void *) &(var)); |
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#define CPU_SETTINGS_ADD_REGISTER16(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT16, \ |
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SETTINGS_FORMAT_HEX16, (void *) &(var)); |
502 |
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#define CPU_SETTINGS_ADD_REGISTER8(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT8, \ |
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SETTINGS_FORMAT_HEX8, (void *) &(var)); |
505 |
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506 |
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#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
508 |
struct cpu_family *fp) { \ |
struct cpu_family *fp) { \ |
509 |
/* Fill in the cpu_family struct with valid data for this arch. */ \ |
/* Fill in the cpu_family struct with valid data for this arch. */ \ |
510 |
fp->name = s; \ |
fp->name = s; \ |
511 |
fp->cpu_new = n ## _cpu_new; \ |
fp->cpu_new = n ## _cpu_new; \ |
512 |
fp->list_available_types = n ## _cpu_list_available_types; \ |
fp->list_available_types = n ## _cpu_list_available_types; \ |
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fp->register_match = n ## _cpu_register_match; \ |
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513 |
fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
514 |
fp->register_dump = n ## _cpu_register_dump; \ |
fp->register_dump = n ## _cpu_register_dump; \ |
515 |
fp->dumpinfo = n ## _cpu_dumpinfo; \ |
fp->dumpinfo = n ## _cpu_dumpinfo; \ |
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fp->interrupt = n ## _cpu_interrupt; \ |
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fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
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516 |
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
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fp->gdb_stub = n ## _cpu_gdb_stub; \ |
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517 |
fp->tlbdump = n ## _cpu_tlbdump; \ |
fp->tlbdump = n ## _cpu_tlbdump; \ |
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fp->init_tables = n ## _cpu_init_tables; \ |
fp->init_tables = n ## _cpu_init_tables; \ |
519 |
return 1; \ |
return 1; \ |