/[gxemul]/trunk/src/include/cpu.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 40 by dpavlin, Mon Oct 8 16:22:11 2007 UTC revision 44 by dpavlin, Mon Oct 8 16:22:56 2007 UTC
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu.h,v 1.116 2007/04/19 15:18:16 debug Exp $   *  $Id: cpu.h,v 1.143 2007/08/29 20:36:49 debug Exp $
32   *   *
33   *  CPU-related definitions.   *  CPU-related definitions.
34   */   */
# Line 41  Line 41 
41  /*  This is needed for undefining 'mips', 'ppc' etc. on weird systems:  */  /*  This is needed for undefining 'mips', 'ppc' etc. on weird systems:  */
42  #include "../../config.h"  #include "../../config.h"
43    
44    #include "timer.h"
45    
46    
47  /*  /*
48   *  Dyntrans misc declarations, used throughout the dyntrans code.   *  Dyntrans misc declarations, used throughout the dyntrans code.
49   *   *
50   *  Note that there is place for all instruction calls within a page,   *  Note that there is space for all instruction calls within a page, and then
51   *  and then 2 more. The first one of these "extra" instruction slots is   *  two more. The first one of these "extra" instruction slots is the end-of-
52   *  the end-of-page slot. It transfers control to the first instruction   *  page slot. It transfers control to the first instruction slot on the next
53   *  slot on the next (virtual) page.   *  (virtual) page.
54   *   *
55   *  The second of these extra instruction slots is an additional   *  The second of these extra instruction slots is an additional end-of-page
56   *  end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch   *  slot for delay-slot architectures. On e.g. MIPS, a branch instruction can
57   *  instruction can "nullify" (skip) the delay-slot. If the end-of-page   *  "nullify" (skip) the delay-slot. If the end-of-page slot is skipped, then
58   *  slot is skipped, then we end up one step after that. That's where the   *  we end up one step after that. That's where the end_of_page2 slot is. :)
59   *  end_of_page2 slot is. :)   *
60   *   *  next_ofs points to the next page in a chain of possible pages. (Several
61   *  next_ofs points to the next page in a chain of possible pages.   *  pages can be in the same chain, but only one matches the specific physaddr.)
62   *  (several pages can be in the same chain, but only one matches the   *
63   *  specific physaddr.)   *  translations_bitmap is a tiny bitmap indicating which parts of the page have
64   *   *  actual translations. Bit 0 corresponds to the lowest 1/32th of the page, bit
65   *  translations is a tiny bitmap indicating which parts of the page have   *  1 to the second-lowest 1/32th, and so on. This speeds up page invalidations,
66   *  actual translations. Bit 0 corresponds to the lowest 1/32th of the page,   *  since only part of the page need to be reset.
67   *  bit 1 to the second-lowest 1/32th, and so on.   *
68     *  translation_ranges_ofs is an offset within the translation cache to a short
69     *  list of ranges for this physpage which contain code. The list is of fixed
70     *  length; to extend the list, the list should be made to point to another
71     *  list, and so forth. (Bad, O(n) find/insert complexity. Should be fixed some
72     *  day. TODO)  See definition of physpage_ranges below.
73   */   */
74  #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype)  struct \  #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype)  struct \
75          arch ## _instr_call {                                   \          arch ## _instr_call {                                   \
# Line 73  Line 81 
81          struct arch ## _tc_physpage {                                   \          struct arch ## _tc_physpage {                                   \
82                  struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\                  struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\
83                  uint32_t        next_ofs;       /*  (0 for end of chain)  */ \                  uint32_t        next_ofs;       /*  (0 for end of chain)  */ \
84                  uint32_t        translations;                           \                  uint32_t        translations_bitmap;                    \
85                    uint32_t        translation_ranges_ofs;                 \
86                  addrtype        physaddr;                               \                  addrtype        physaddr;                               \
87          };                                                              \          };                                                              \
88                                                                          \                                                                          \
# Line 101  Line 110 
110                  int                             refcount;               \                  int                             refcount;               \
111          };          };
112    
113    
114    /*
115     *  This structure contains a list of ranges within an emulated
116     *  physical page that contain translatable code.
117     */
118    #define PHYSPAGE_RANGES_ENTRIES_PER_LIST                20
119    struct physpage_ranges {
120            uint32_t        next_ofs;       /*  0 for end of chain  */
121            uint32_t        n_entries_used;
122            uint16_t        base[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
123            uint16_t        length[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
124            uint16_t        count[PHYSPAGE_RANGES_ENTRIES_PER_LIST];
125    };
126    
127    
128  /*  /*
129   *  Dyntrans "Instruction Translation Cache":   *  Dyntrans "Instruction Translation Cache":
130   *   *
# Line 145  Line 169 
169   *  full-size tables can fit in virtual memory on modern hosts (both 32-bit   *  full-size tables can fit in virtual memory on modern hosts (both 32-bit
170   *  and 64-bit hosts). :-)   *  and 64-bit hosts). :-)
171   *   *
172   *  Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t)   *  Usage: e.g. VPH32(arm,ARM)
173   *           or VPH32(sparc,SPARC,uint64_t,uint16_t)   *           or VPH32(sparc,SPARC)
174   *   *
175   *  The vph_tlb_entry entries are cpu dependent tlb entries.   *  The vph_tlb_entry entries are cpu dependent tlb entries.
176   *   *
177   *  The host_load and host_store entries point to host pages; the phys_addr   *  The host_load and host_store entries point to host pages; the phys_addr
178   *  entries are uint32_t or uint64_t (emulated physical addresses).   *  entries are uint32_t (emulated physical addresses).
179   *   *
180   *  phys_page points to translation cache physpages.   *  phys_page points to translation cache physpages.
181   *   *
# Line 159  Line 183 
183   *  The values in this array are the tlb index plus 1, so a value of, say,   *  The values in this array are the tlb index plus 1, so a value of, say,
184   *  3 means tlb index 2. A value of 0 would mean a tlb index of -1, which   *  3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
185   *  is not a valid index. (I.e. no hit.)   *  is not a valid index. (I.e. no hit.)
186     *
187     *  The VPH32EXTENDED variant adds an additional postfix to the array
188     *  names. Used so far only for usermode addresses in M88K emulation.
189   */   */
190  #define N_VPH32_ENTRIES         1048576  #define N_VPH32_ENTRIES         1048576
191  #define VPH32(arch,ARCH,paddrtype,tlbindextype)                         \  #define VPH32(arch,ARCH)                                                \
192            unsigned char           *host_load[N_VPH32_ENTRIES];            \
193            unsigned char           *host_store[N_VPH32_ENTRIES];           \
194            uint32_t                phys_addr[N_VPH32_ENTRIES];             \
195            struct arch ## _tc_physpage  *phys_page[N_VPH32_ENTRIES];       \
196            uint8_t                 vaddr_to_tlbindex[N_VPH32_ENTRIES];
197    #define VPH32_16BITVPHENTRIES(arch,ARCH)                                \
198          unsigned char           *host_load[N_VPH32_ENTRIES];            \          unsigned char           *host_load[N_VPH32_ENTRIES];            \
199          unsigned char           *host_store[N_VPH32_ENTRIES];           \          unsigned char           *host_store[N_VPH32_ENTRIES];           \
200          paddrtype               phys_addr[N_VPH32_ENTRIES];             \          uint32_t                phys_addr[N_VPH32_ENTRIES];             \
201          struct arch ## _tc_physpage  *phys_page[N_VPH32_ENTRIES];       \          struct arch ## _tc_physpage  *phys_page[N_VPH32_ENTRIES];       \
202          tlbindextype            vaddr_to_tlbindex[N_VPH32_ENTRIES];          uint16_t                vaddr_to_tlbindex[N_VPH32_ENTRIES];
203    #define VPH32EXTENDED(arch,ARCH,ex)                                     \
204            unsigned char           *host_load_ ## ex[N_VPH32_ENTRIES];     \
205            unsigned char           *host_store_ ## ex[N_VPH32_ENTRIES];    \
206            uint32_t                phys_addr_ ## ex[N_VPH32_ENTRIES];      \
207            struct arch ## _tc_physpage  *phys_page_ ## ex[N_VPH32_ENTRIES];\
208            uint8_t                 vaddr_to_tlbindex_ ## ex[N_VPH32_ENTRIES];
209    
210    
211  /*  /*
212   *  64-bit dyntrans emulated Virtual -> physical -> host address translation:   *  64-bit dyntrans emulated Virtual -> physical -> host address translation:
213   *  -------------------------------------------------------------------------   *  -------------------------------------------------------------------------
214   *   *
215   *  Usage: e.g. VPH64(alpha,ALPHA,uint8_t)   *  Usage: e.g. VPH64(alpha,ALPHA)
216   *           or VPH64(sparc,SPARC,uint16_t)   *           or VPH64(sparc,SPARC)
217   *   *
218   *  l1_64 is an array containing poiners to l2 tables.   *  l1_64 is an array containing poiners to l2 tables.
219   *   *
# Line 182  Line 222 
222   *  used.   *  used.
223   */   */
224  #define DYNTRANS_L1N            17  #define DYNTRANS_L1N            17
225  #define VPH64(arch,ARCH,tlbindextype)                                   \  #define VPH64(arch,ARCH)                                                \
226          struct arch ## _l3_64_table     *l3_64_dummy;                   \          struct arch ## _l3_64_table     *l3_64_dummy;                   \
227          struct arch ## _l3_64_table     *next_free_l3;                  \          struct arch ## _l3_64_table     *next_free_l3;                  \
228          struct arch ## _l2_64_table     *l2_64_dummy;                   \          struct arch ## _l2_64_table     *l2_64_dummy;                   \
# Line 193  Line 233 
233  /*  Include all CPUs' header files here:  */  /*  Include all CPUs' header files here:  */
234  #include "cpu_alpha.h"  #include "cpu_alpha.h"
235  #include "cpu_arm.h"  #include "cpu_arm.h"
236  #include "cpu_avr.h"  #include "cpu_m32r.h"
237  #include "cpu_m88k.h"  #include "cpu_m88k.h"
238  #include "cpu_mips.h"  #include "cpu_mips.h"
239  #include "cpu_ppc.h"  #include "cpu_ppc.h"
# Line 274  struct cpu_family { Line 314  struct cpu_family {
314  #define N_SAFE_DYNTRANS_LIMIT_SHIFT     14  #define N_SAFE_DYNTRANS_LIMIT_SHIFT     14
315  #define N_SAFE_DYNTRANS_LIMIT   ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)  #define N_SAFE_DYNTRANS_LIMIT   ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)
316    
317  #define DEFAULT_DYNTRANS_CACHE_SIZE     (40*1048576)  #define MAX_DYNTRANS_READAHEAD          128
318    
319    #define DEFAULT_DYNTRANS_CACHE_SIZE     (48*1048576)
320  #define DYNTRANS_CACHE_MARGIN           200000  #define DYNTRANS_CACHE_MARGIN           200000
321    
322  #define N_BASE_TABLE_ENTRIES            65536  #define N_BASE_TABLE_ENTRIES            65536
323  #define PAGENR_TO_TABLE_INDEX(a)        ((a) & (N_BASE_TABLE_ENTRIES-1))  #define PAGENR_TO_TABLE_INDEX(a)        ((a) & (N_BASE_TABLE_ENTRIES-1))
324    
325    
 #ifdef NATIVE_CODE_GENERATION  
 /*  
  *  Intermediate Native Representation (INR).  
  *  Used for native code generation.  
  */  
 #include "inr.h"  
 #endif  
   
   
326  /*  /*
327   *  The generic CPU struct:   *  The generic CPU struct:
328   */   */
# Line 304  struct cpu { Line 337  struct cpu {
337          /*  CPU-specific name, e.g. "R2000", "21164PC", etc.  */          /*  CPU-specific name, e.g. "R2000", "21164PC", etc.  */
338          char            *name;          char            *name;
339    
340          /*  Full "path" to the CPU, e.g. "emul[0].machine[0].cpu[0]":  */          /*  Full "path" to the CPU, e.g. "machine[0].cpu[0]":  */
341          char            *path;          char            *path;
342    
343          /*  EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN.  */          /*  Nr of instructions executed, etc.:  */
344          int             byte_order;          int64_t         ninstrs;
345            int64_t         ninstrs_show;
346            int64_t         ninstrs_flush;
347            int64_t         ninstrs_since_gettimeofday;
348            struct timeval  starttime;
349    
350          /*  0-based CPU id, in an emulated SMP system.  */          /*  EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN.  */
351          int             cpu_id;          uint8_t         byte_order;
352    
353          /*  0 for emulated 64-bit CPUs, 1 for 32-bit.  */          /*  0 for emulated 64-bit CPUs, 1 for 32-bit.  */
354          int             is_32bit;          uint8_t         is_32bit;
355    
356          /*  1 while running, 0 when paused/stopped.  */          /*  1 while running, 0 when paused/stopped.  */
357          int             running;          uint8_t         running;
358    
359            /*  See comment further up.  */
360            uint8_t         delay_slot;
361    
362            /*  0-based CPU id, in an emulated SMP system.  */
363            int             cpu_id;
364    
365          /*  A pointer to the main memory connected to this CPU.  */          /*  A pointer to the main memory connected to this CPU.  */
366          struct memory   *mem;          struct memory   *mem;
# Line 343  struct cpu { Line 386  struct cpu {
386          /*  The program counter. (For 32-bit modes, not all bits are used.)  */          /*  The program counter. (For 32-bit modes, not all bits are used.)  */
387          uint64_t        pc;          uint64_t        pc;
388    
         /*  See comment further up.  */  
         int             delay_slot;  
   
389          /*  The current depth of function call tracing.  */          /*  The current depth of function call tracing.  */
390          int             trace_tree_depth;          int             trace_tree_depth;
391    
# Line 358  struct cpu { Line 398  struct cpu {
398           *  instructions per second, "idling" is printed instead. (The number           *  instructions per second, "idling" is printed instead. (The number
399           *  of instrs per second when idling is meaningless anyway.)           *  of instrs per second when idling is meaningless anyway.)
400           */           */
401          int             is_halted;          char            is_halted;
402          int             has_been_idling;          char            has_been_idling;
403    
404          /*          /*
405           *  Dynamic translation:           *  Dynamic translation:
# Line 381  struct cpu { Line 421  struct cpu {
421           *  32 MB) which is used for translations. When it has been used up,           *  32 MB) which is used for translations. When it has been used up,
422           *  everything restarts from scratch.           *  everything restarts from scratch.
423           *           *
424           *  The INR struct contains the Intermediate Native Representation,           *  translation_readahead is non-zero when translating instructions
425           *  used during native code generation.           *  ahead of the current (emulated) instruction pointer.
426           */           */
427    
428            int             translation_readahead;
429    
430            /*  Instruction translation cache:  */
431          int             n_translated_instrs;          int             n_translated_instrs;
432          unsigned char   *translation_cache;          unsigned char   *translation_cache;
433          size_t          translation_cache_cur_ofs;          size_t          translation_cache_cur_ofs;
434    
 #ifdef NATIVE_CODE_GENERATION  
         struct inr      inr;  
 #endif  
435    
436          /*          /*
437           *  CPU-family dependent:           *  CPU-family dependent:
438           *           *
439           *  These contain everything ranging from registers, memory management,           *  These contain everything ranging from general purpose registers,
440           *  status words, etc.           *  control registers, memory management, status words, interrupt
441             *  specifics, etc.
442           */           */
443          union {          union {
444                  struct alpha_cpu      alpha;                  struct alpha_cpu      alpha;
445                  struct arm_cpu        arm;                  struct arm_cpu        arm;
446                  struct avr_cpu        avr;                  struct m32r_cpu       m32r;
447                  struct m88k_cpu       m88k;                  struct m88k_cpu       m88k;
448                  struct mips_cpu       mips;                  struct mips_cpu       mips;
449                  struct ppc_cpu        ppc;                  struct ppc_cpu        ppc;
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