/[gxemul]/trunk/src/include/cpu.h
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Revision 32 - (hide annotations)
Mon Oct 8 16:20:58 2007 UTC (16 years, 7 months ago) by dpavlin
File MIME type: text/plain
File size: 16858 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============
1 dpavlin 4 #ifndef CPU_H
2     #define CPU_H
3    
4     /*
5 dpavlin 22 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
6 dpavlin 4 *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 32 * $Id: cpu.h,v 1.100 2006/10/25 09:24:06 debug Exp $
32 dpavlin 4 *
33 dpavlin 22 * CPU-related definitions.
34 dpavlin 4 */
35    
36    
37     #include <sys/types.h>
38     #include <inttypes.h>
39     #include <sys/time.h>
40    
41 dpavlin 22 /* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */
42 dpavlin 4 #include "../../config.h"
43    
44 dpavlin 22 /*
45     * Dyntrans misc declarations, used throughout the dyntrans code.
46 dpavlin 24 *
47     * Note that there is place for all instruction calls within a page,
48     * and then 2 more. The first one of these "extra" instruction slots is
49     * the end-of-page slot. It transfers control to the first instruction
50     * slot on the next (virtual) page.
51     *
52     * The second of these extra instruction slots is an additional
53     * end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch
54     * instruction can "nullify" (skip) the delay-slot. If the end-of-page
55     * slot is skipped, then we end up one step after that. That's where the
56     * end_of_page2 slot is. :)
57 dpavlin 28 *
58     * next_ofs points to the next page in a chain of possible pages.
59     * (several pages can be in the same chain, but only one matches the
60     * specific physaddr.)
61     *
62     * translations is a tiny bitmap indicating which parts of the page have
63     * actual translations. Bit 0 corresponds to the lowest 1/32th of the page,
64     * bit 1 to the second-lowest 1/32th, and so on.
65 dpavlin 22 */
66     #define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \
67     arch ## _instr_call { \
68     void (*f)(struct cpu *, struct arch ## _instr_call *); \
69     size_t arg[ARCH ## _N_IC_ARGS]; \
70     }; \
71     \
72     /* Translation cache struct for each physical page: */ \
73     struct arch ## _tc_physpage { \
74 dpavlin 24 struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\
75 dpavlin 22 uint32_t next_ofs; /* (0 for end of chain) */ \
76 dpavlin 28 uint32_t translations; \
77 dpavlin 22 addrtype physaddr; \
78     }; \
79     \
80     struct arch ## _vpg_tlb_entry { \
81     uint8_t valid; \
82     uint8_t writeflag; \
83     addrtype vaddr_page; \
84     addrtype paddr_page; \
85     unsigned char *host_page; \
86     };
87    
88 dpavlin 24 #define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \
89     struct arch ## _l3_64_table { \
90     unsigned char *host_load[1 << ARCH ## _L3N]; \
91     unsigned char *host_store[1 << ARCH ## _L3N]; \
92     uint64_t phys_addr[1 << ARCH ## _L3N]; \
93     tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \
94     struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \
95     struct arch ## _l3_64_table *next; \
96     int refcount; \
97     }; \
98     struct arch ## _l2_64_table { \
99     struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \
100     struct arch ## _l2_64_table *next; \
101     int refcount; \
102     };
103    
104 dpavlin 22 /*
105     * Dyntrans "Instruction Translation Cache":
106     *
107     * cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to
108     * be the same as cur_ic_page, because all the instrcalls should be placed
109     * first in the physpage struct!)
110     *
111     * cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE
112     * instruction call entries.
113     *
114     * next_ic points to the next such instruction call to be executed.
115     *
116     * combination_check, when set to non-NULL, is executed automatically after
117     * an instruction has been translated. (It check for combinations of
118     * instructions; low_addr is the offset of the translated instruction in the
119     * current page, NOT shifted right.)
120     */
121     #define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \
122     struct arch ## _instr_call *cur_ic_page; \
123     struct arch ## _instr_call *next_ic; \
124 dpavlin 26 struct arch ## _tc_physpage *physpage_template;\
125 dpavlin 22 void (*combination_check)(struct cpu *, \
126     struct arch ## _instr_call *, int low_addr);
127    
128     /*
129     * Virtual -> physical -> host address translation TLB entries:
130     * ------------------------------------------------------------
131     *
132     * Regardless of whether 32-bit or 64-bit address translation is used, the
133     * same TLB entry structure is used.
134     */
135     #define VPH_TLBS(arch,ARCH) \
136     struct arch ## _vpg_tlb_entry \
137     vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES];
138    
139     /*
140     * 32-bit dyntrans emulated Virtual -> physical -> host address translation:
141     * -------------------------------------------------------------------------
142     *
143     * This stuff assumes that 4 KB pages are used. 20 bits to select a page
144     * means just 1 M entries needed. This is small enough that a couple of
145     * full-size tables can fit in virtual memory on modern hosts (both 32-bit
146     * and 64-bit hosts). :-)
147     *
148     * Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t)
149     * or VPH32(sparc,SPARC,uint64_t,uint16_t)
150     *
151     * The vph_tlb_entry entries are cpu dependent tlb entries.
152     *
153     * The host_load and host_store entries point to host pages; the phys_addr
154     * entries are uint32_t or uint64_t (emulated physical addresses).
155     *
156     * phys_page points to translation cache physpages.
157     *
158     * vaddr_to_tlbindex is a virtual address to tlb index hint table.
159     * The values in this array are the tlb index plus 1, so a value of, say,
160     * 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which
161     * is not a valid index. (I.e. no hit.)
162     */
163     #define N_VPH32_ENTRIES 1048576
164     #define VPH32(arch,ARCH,paddrtype,tlbindextype) \
165     unsigned char *host_load[N_VPH32_ENTRIES]; \
166     unsigned char *host_store[N_VPH32_ENTRIES]; \
167     paddrtype phys_addr[N_VPH32_ENTRIES]; \
168     struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \
169     tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES];
170    
171     /*
172     * 64-bit dyntrans emulated Virtual -> physical -> host address translation:
173     * -------------------------------------------------------------------------
174     *
175     * Usage: e.g. VPH64(alpha,ALPHA,uint8_t)
176     * or VPH64(sparc,SPARC,uint16_t)
177     *
178 dpavlin 24 * l1_64 is an array containing poiners to l2 tables.
179     *
180     * l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL
181     * pointers in l1_64 for unused slots, a pointer to the dummy table can be
182     * used.
183 dpavlin 22 */
184 dpavlin 24 #define DYNTRANS_L1N 17
185     #define VPH64(arch,ARCH,tlbindextype) \
186     struct arch ## _l3_64_table *l3_64_dummy; \
187     struct arch ## _l3_64_table *next_free_l3; \
188     struct arch ## _l2_64_table *l2_64_dummy; \
189     struct arch ## _l2_64_table *next_free_l2; \
190     struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N];
191 dpavlin 22
192 dpavlin 24
193     /* Include all CPUs' header files here: */
194 dpavlin 14 #include "cpu_alpha.h"
195 dpavlin 6 #include "cpu_arm.h"
196 dpavlin 14 #include "cpu_avr.h"
197 dpavlin 32 #include "cpu_avr32.h"
198 dpavlin 14 #include "cpu_hppa.h"
199     #include "cpu_i960.h"
200 dpavlin 12 #include "cpu_ia64.h"
201     #include "cpu_m68k.h"
202 dpavlin 4 #include "cpu_mips.h"
203     #include "cpu_ppc.h"
204 dpavlin 32 #include "cpu_rca180x.h"
205 dpavlin 14 #include "cpu_sh.h"
206 dpavlin 12 #include "cpu_sparc.h"
207 dpavlin 28 #include "cpu_transputer.h"
208 dpavlin 4 #include "cpu_x86.h"
209    
210     struct cpu;
211     struct emul;
212     struct machine;
213     struct memory;
214 dpavlin 32 struct settings;
215 dpavlin 4
216    
217 dpavlin 30 /*
218     * cpu_family
219     * ----------
220     *
221     * This structure consists of various pointers to functions, performing
222     * architecture-specific functions.
223     *
224     * Except for the next and arch fields at the top, all fields in the
225     * cpu_family struct are filled in by ecah CPU family's init function.
226     */
227 dpavlin 4 struct cpu_family {
228     struct cpu_family *next;
229     int arch;
230    
231 dpavlin 30 /* Familty name, e.g. "MIPS", "Alpha" etc. */
232 dpavlin 4 char *name;
233 dpavlin 30
234     /* Fill in architecture specific parts of a struct cpu. */
235 dpavlin 10 int (*cpu_new)(struct cpu *cpu, struct memory *mem,
236 dpavlin 4 struct machine *machine,
237     int cpu_id, char *cpu_type_name);
238 dpavlin 30
239     /* Initialize various translation tables. */
240     void (*init_tables)(struct cpu *cpu);
241    
242     /* List available CPU types for this architecture. */
243 dpavlin 4 void (*list_available_types)(void);
244 dpavlin 30
245     /* Disassemble an instruction. */
246 dpavlin 4 int (*disassemble_instr)(struct cpu *cpu,
247     unsigned char *instr, int running,
248 dpavlin 24 uint64_t dumpaddr);
249 dpavlin 30
250     /* Dump CPU registers in readable format. */
251 dpavlin 4 void (*register_dump)(struct cpu *cpu,
252     int gprs, int coprocs);
253 dpavlin 30
254     /* Dump generic CPU info in readable format. */
255 dpavlin 4 void (*dumpinfo)(struct cpu *cpu);
256 dpavlin 30
257     /* Dump TLB data for CPU id x. */
258 dpavlin 4 void (*tlbdump)(struct machine *m, int x,
259     int rawflag);
260 dpavlin 30
261     /* Assert an interrupt. */
262 dpavlin 4 int (*interrupt)(struct cpu *cpu, uint64_t irq_nr);
263 dpavlin 30
264     /* De-assert an interrupt. */
265 dpavlin 4 int (*interrupt_ack)(struct cpu *cpu,
266     uint64_t irq_nr);
267 dpavlin 30
268     /* Print architecture-specific function call arguments.
269     (This is called for each function call, if running with -t.) */
270 dpavlin 12 void (*functioncall_trace)(struct cpu *,
271     uint64_t f, int n_args);
272 dpavlin 30
273     /* GDB command handler. */
274 dpavlin 24 char *(*gdb_stub)(struct cpu *, char *cmd);
275 dpavlin 4 };
276    
277    
278 dpavlin 12 /*
279 dpavlin 22 * More dyntrans stuff:
280 dpavlin 12 *
281     * The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
282     * into the cache, for possible translation cache structs for physical pages.
283     */
284    
285 dpavlin 24 /* Meaning of delay_slot: */
286     #define NOT_DELAYED 0
287     #define DELAYED 1
288     #define TO_BE_DELAYED 2
289 dpavlin 30 #define EXCEPTION_IN_DELAY_SLOT 8
290 dpavlin 24
291     #define N_SAFE_DYNTRANS_LIMIT_SHIFT 14
292     #define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1)
293    
294 dpavlin 32 #define DYNTRANS_CACHE_SIZE (32*1048576)
295     #define DYNTRANS_CACHE_MARGIN 200000
296 dpavlin 12
297     #define N_BASE_TABLE_ENTRIES 32768
298     #define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1))
299    
300    
301     /*
302     * The generic CPU struct:
303     */
304    
305 dpavlin 4 struct cpu {
306     /* Pointer back to the machine this CPU is in: */
307     struct machine *machine;
308    
309 dpavlin 32 /* Settings: */
310     struct settings *settings;
311    
312 dpavlin 30 /* CPU-specific name, e.g. "R2000", "21164PC", etc. */
313     char *name;
314    
315     /* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */
316 dpavlin 4 int byte_order;
317 dpavlin 30
318     /* 0-based CPU id, in an emulated SMP system. */
319 dpavlin 4 int cpu_id;
320    
321 dpavlin 30 /* 0 for emulated 64-bit CPUs, 1 for 32-bit. */
322     int is_32bit;
323    
324     /* 1 while running, 0 when paused/stopped. */
325     int running;
326    
327     /* A pointer to the main memory connected to this CPU. */
328 dpavlin 4 struct memory *mem;
329 dpavlin 28
330     int (*run_instr)(struct cpu *cpu);
331 dpavlin 4 int (*memory_rw)(struct cpu *cpu,
332     struct memory *mem, uint64_t vaddr,
333     unsigned char *data, size_t len,
334     int writeflag, int cache_flags);
335 dpavlin 26 int (*translate_v2p)(struct cpu *, uint64_t vaddr,
336     uint64_t *return_paddr, int flags);
337 dpavlin 12 void (*update_translation_table)(struct cpu *,
338     uint64_t vaddr_page, unsigned char *host_page,
339     int writeflag, uint64_t paddr_page);
340 dpavlin 18 void (*invalidate_translation_caches)(struct cpu *,
341 dpavlin 14 uint64_t paddr, int flags);
342     void (*invalidate_code_translation)(struct cpu *,
343     uint64_t paddr, int flags);
344 dpavlin 12 void (*useremul_syscall)(struct cpu *cpu, uint32_t code);
345 dpavlin 24 int (*instruction_has_delayslot)(struct cpu *cpu,
346     unsigned char *ib);
347 dpavlin 4
348 dpavlin 30 /* The program counter. (For 32-bit modes, not all bits are used.) */
349 dpavlin 4 uint64_t pc;
350    
351 dpavlin 30 /* See comment further up. */
352     int delay_slot;
353    
354     /* The current depth of function call tracing. */
355 dpavlin 12 int trace_tree_depth;
356    
357     /*
358 dpavlin 30 * If is_halted is true when an interrupt trap occurs, the pointer
359     * to the next instruction to execute will be the instruction
360     * following the halt instruction, not the halt instrucion itself.
361 dpavlin 32 *
362     * If has_been_idling is true when printing the number of executed
363     * instructions per second, "idling" is printed instead. (The number
364     * of instrs per second when idling is meaningless anyway.)
365 dpavlin 30 */
366     int is_halted;
367 dpavlin 32 int has_been_idling;
368 dpavlin 30
369     /*
370 dpavlin 12 * Dynamic translation:
371 dpavlin 30 *
372     * The number of translated instructions is assumed to be 1 per
373     * instruction call. For each case where this differs from the
374     * truth, n_translated_instrs should be modified. E.g. if 1000
375     * instruction calls are done, and n_translated_instrs is 50, then
376     * 1050 emulated instructions were actually executed.
377     *
378     * Note that it can also be adjusted negatively, that is, the way
379     * to "get out" of a dyntrans loop is to set the current instruction
380     * call pointer to the "nothing" instruction. This instruction
381     * _decreases_ n_translated_instrs. That way, once the dyntrans loop
382     * exits, only real instructions will be counted, and not the
383     * "nothing" instructions.
384 dpavlin 12 */
385     int n_translated_instrs;
386     unsigned char *translation_cache;
387     size_t translation_cache_cur_ofs;
388    
389     /*
390     * CPU-family dependent:
391 dpavlin 30 *
392     * These contain everything ranging from registers, memory management,
393     * status words, etc.
394 dpavlin 12 */
395 dpavlin 4 union {
396 dpavlin 28 struct alpha_cpu alpha;
397     struct arm_cpu arm;
398     struct avr_cpu avr;
399 dpavlin 32 struct avr32_cpu avr32;
400 dpavlin 28 struct hppa_cpu hppa;
401     struct i960_cpu i960;
402     struct ia64_cpu ia64;
403     struct m68k_cpu m68k;
404     struct mips_cpu mips;
405     struct ppc_cpu ppc;
406 dpavlin 32 struct rca180x_cpu rca180x;
407 dpavlin 28 struct sh_cpu sh;
408     struct sparc_cpu sparc;
409     struct transputer_cpu transputer;
410     struct x86_cpu x86;
411 dpavlin 4 } cd;
412     };
413    
414    
415     /* cpu.c: */
416     struct cpu *cpu_new(struct memory *mem, struct machine *machine,
417     int cpu_id, char *cpu_type_name);
418 dpavlin 32 void cpu_destroy(struct cpu *cpu);
419    
420 dpavlin 4 void cpu_tlbdump(struct machine *m, int x, int rawflag);
421     void cpu_register_dump(struct machine *m, struct cpu *cpu,
422     int gprs, int coprocs);
423     int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
424 dpavlin 24 unsigned char *instr, int running, uint64_t addr);
425     char *cpu_gdb_stub(struct cpu *cpu, char *cmd);
426 dpavlin 32
427 dpavlin 4 int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
428     int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
429 dpavlin 12 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
430     void cpu_functioncall_trace_return(struct cpu *cpu);
431 dpavlin 32
432 dpavlin 12 void cpu_create_or_reset_tc(struct cpu *cpu);
433 dpavlin 32
434 dpavlin 12 void cpu_run_init(struct machine *machine);
435     void cpu_run_deinit(struct machine *machine);
436 dpavlin 32
437 dpavlin 4 void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
438     void cpu_list_available_types(void);
439 dpavlin 10 void cpu_show_cycles(struct machine *machine, int forced);
440 dpavlin 32
441 dpavlin 4 struct cpu_family *cpu_family_ptr_by_number(int arch);
442     void cpu_init(void);
443    
444    
445 dpavlin 14 #define JUST_MARK_AS_NON_WRITABLE 1
446     #define INVALIDATE_ALL 2
447     #define INVALIDATE_PADDR 4
448     #define INVALIDATE_VADDR 8
449 dpavlin 22 #define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */
450 dpavlin 14
451    
452 dpavlin 32 /* Note: 64-bit processors running in 32-bit mode use a 32-bit
453     display format, even though the underlying data is 64-bits. */
454     #define CPU_SETTINGS_ADD_REGISTER64(name, var) \
455     settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT64, \
456     cpu->is_32bit? SETTINGS_FORMAT_HEX32 : SETTINGS_FORMAT_HEX64, \
457     (void *) &(var));
458     #define CPU_SETTINGS_ADD_REGISTER32(name, var) \
459     settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT32, \
460     SETTINGS_FORMAT_HEX32, (void *) &(var));
461     #define CPU_SETTINGS_ADD_REGISTER16(name, var) \
462     settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT16, \
463     SETTINGS_FORMAT_HEX16, (void *) &(var));
464     #define CPU_SETTINGS_ADD_REGISTER8(name, var) \
465     settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT8, \
466     SETTINGS_FORMAT_HEX8, (void *) &(var));
467    
468    
469 dpavlin 12 #define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
470     struct cpu_family *fp) { \
471     /* Fill in the cpu_family struct with valid data for this arch. */ \
472     fp->name = s; \
473     fp->cpu_new = n ## _cpu_new; \
474     fp->list_available_types = n ## _cpu_list_available_types; \
475     fp->disassemble_instr = n ## _cpu_disassemble_instr; \
476     fp->register_dump = n ## _cpu_register_dump; \
477     fp->dumpinfo = n ## _cpu_dumpinfo; \
478 dpavlin 20 fp->interrupt = n ## _cpu_interrupt; \
479     fp->interrupt_ack = n ## _cpu_interrupt_ack; \
480     fp->functioncall_trace = n ## _cpu_functioncall_trace; \
481 dpavlin 24 fp->gdb_stub = n ## _cpu_gdb_stub; \
482 dpavlin 12 fp->tlbdump = n ## _cpu_tlbdump; \
483 dpavlin 26 fp->init_tables = n ## _cpu_init_tables; \
484 dpavlin 12 return 1; \
485     }
486    
487    
488 dpavlin 4 #endif /* CPU_H */
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