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#ifndef CPU_H |
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#define CPU_H |
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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu.h,v 1.84 2006/07/20 21:53:00 debug Exp $ |
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* |
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* CPU-related definitions. |
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*/ |
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#include <sys/types.h> |
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#include <inttypes.h> |
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#include <sys/time.h> |
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/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */ |
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dpavlin |
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#include "../../config.h" |
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/* |
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* Dyntrans misc declarations, used throughout the dyntrans code. |
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* |
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* Note that there is place for all instruction calls within a page, |
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* and then 2 more. The first one of these "extra" instruction slots is |
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* the end-of-page slot. It transfers control to the first instruction |
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* slot on the next (virtual) page. |
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* |
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* The second of these extra instruction slots is an additional |
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* end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch |
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* instruction can "nullify" (skip) the delay-slot. If the end-of-page |
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* slot is skipped, then we end up one step after that. That's where the |
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* end_of_page2 slot is. :) |
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* |
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* next_ofs points to the next page in a chain of possible pages. |
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* (several pages can be in the same chain, but only one matches the |
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* specific physaddr.) |
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* |
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* flags contains special flags. Currently only COMBINATIONS, which indicates |
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* that the page has instruction combinations. |
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* |
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* translations is a tiny bitmap indicating which parts of the page have |
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* actual translations. Bit 0 corresponds to the lowest 1/32th of the page, |
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* bit 1 to the second-lowest 1/32th, and so on. |
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*/ |
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#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
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arch ## _instr_call { \ |
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void (*f)(struct cpu *, struct arch ## _instr_call *); \ |
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size_t arg[ARCH ## _N_IC_ARGS]; \ |
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}; \ |
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\ |
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/* Translation cache struct for each physical page: */ \ |
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struct arch ## _tc_physpage { \ |
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struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\ |
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uint32_t next_ofs; /* (0 for end of chain) */ \ |
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uint32_t translations; \ |
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int flags; \ |
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addrtype physaddr; \ |
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}; \ |
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\ |
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struct arch ## _vpg_tlb_entry { \ |
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uint8_t valid; \ |
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uint8_t writeflag; \ |
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addrtype vaddr_page; \ |
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addrtype paddr_page; \ |
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unsigned char *host_page; \ |
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int64_t timestamp; \ |
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}; |
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#define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \ |
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struct arch ## _l3_64_table { \ |
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unsigned char *host_load[1 << ARCH ## _L3N]; \ |
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unsigned char *host_store[1 << ARCH ## _L3N]; \ |
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uint64_t phys_addr[1 << ARCH ## _L3N]; \ |
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tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \ |
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struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \ |
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struct arch ## _l3_64_table *next; \ |
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int refcount; \ |
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}; \ |
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struct arch ## _l2_64_table { \ |
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struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \ |
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struct arch ## _l2_64_table *next; \ |
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int refcount; \ |
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}; |
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/* |
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* Dyntrans "Instruction Translation Cache": |
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* |
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* cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to |
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* be the same as cur_ic_page, because all the instrcalls should be placed |
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* first in the physpage struct!) |
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* |
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* cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE |
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* instruction call entries. |
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* |
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* next_ic points to the next such instruction call to be executed. |
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* |
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* combination_check, when set to non-NULL, is executed automatically after |
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* an instruction has been translated. (It check for combinations of |
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* instructions; low_addr is the offset of the translated instruction in the |
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* current page, NOT shifted right.) |
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*/ |
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#define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \ |
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struct arch ## _instr_call *cur_ic_page; \ |
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struct arch ## _instr_call *next_ic; \ |
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struct arch ## _tc_physpage *physpage_template;\ |
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void (*combination_check)(struct cpu *, \ |
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struct arch ## _instr_call *, int low_addr); |
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/* |
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* Virtual -> physical -> host address translation TLB entries: |
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* ------------------------------------------------------------ |
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* |
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* Regardless of whether 32-bit or 64-bit address translation is used, the |
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* same TLB entry structure is used. |
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*/ |
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#define VPH_TLBS(arch,ARCH) \ |
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struct arch ## _vpg_tlb_entry \ |
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vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES]; |
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/* |
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* 32-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* This stuff assumes that 4 KB pages are used. 20 bits to select a page |
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* means just 1 M entries needed. This is small enough that a couple of |
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* full-size tables can fit in virtual memory on modern hosts (both 32-bit |
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* and 64-bit hosts). :-) |
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* |
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* Usage: e.g. VPH32(arm,ARM,uint32_t,uint8_t) |
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* or VPH32(sparc,SPARC,uint64_t,uint16_t) |
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* |
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* The vph_tlb_entry entries are cpu dependent tlb entries. |
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* |
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* The host_load and host_store entries point to host pages; the phys_addr |
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* entries are uint32_t or uint64_t (emulated physical addresses). |
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* |
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* phys_page points to translation cache physpages. |
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* |
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* vaddr_to_tlbindex is a virtual address to tlb index hint table. |
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* The values in this array are the tlb index plus 1, so a value of, say, |
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* 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which |
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* is not a valid index. (I.e. no hit.) |
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*/ |
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#define N_VPH32_ENTRIES 1048576 |
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#define VPH32(arch,ARCH,paddrtype,tlbindextype) \ |
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unsigned char *host_load[N_VPH32_ENTRIES]; \ |
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unsigned char *host_store[N_VPH32_ENTRIES]; \ |
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paddrtype phys_addr[N_VPH32_ENTRIES]; \ |
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struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
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tlbindextype vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
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/* |
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* 64-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* Usage: e.g. VPH64(alpha,ALPHA,uint8_t) |
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* or VPH64(sparc,SPARC,uint16_t) |
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* |
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* l1_64 is an array containing poiners to l2 tables. |
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* |
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* l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL |
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* pointers in l1_64 for unused slots, a pointer to the dummy table can be |
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* used. |
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*/ |
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#define DYNTRANS_L1N 17 |
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#define VPH64(arch,ARCH,tlbindextype) \ |
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struct arch ## _l3_64_table *l3_64_dummy; \ |
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struct arch ## _l3_64_table *next_free_l3; \ |
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struct arch ## _l2_64_table *l2_64_dummy; \ |
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struct arch ## _l2_64_table *next_free_l2; \ |
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struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N]; |
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/* Include all CPUs' header files here: */ |
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#include "cpu_alpha.h" |
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#include "cpu_arm.h" |
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#include "cpu_avr.h" |
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#include "cpu_hppa.h" |
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#include "cpu_i960.h" |
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#include "cpu_ia64.h" |
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#include "cpu_m68k.h" |
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#include "cpu_mips.h" |
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#include "cpu_ppc.h" |
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#include "cpu_sh.h" |
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#include "cpu_sparc.h" |
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#include "cpu_transputer.h" |
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#include "cpu_x86.h" |
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struct cpu; |
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struct emul; |
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struct machine; |
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struct memory; |
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struct cpu_family { |
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struct cpu_family *next; |
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int arch; |
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/* These are filled in by each CPU family's init function: */ |
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char *name; |
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int (*cpu_new)(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, |
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int cpu_id, char *cpu_type_name); |
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void (*list_available_types)(void); |
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void (*register_match)(struct machine *m, |
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char *name, int writeflag, |
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uint64_t *valuep, int *match_register); |
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int (*disassemble_instr)(struct cpu *cpu, |
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unsigned char *instr, int running, |
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uint64_t dumpaddr); |
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dpavlin |
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void (*register_dump)(struct cpu *cpu, |
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int gprs, int coprocs); |
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void (*dumpinfo)(struct cpu *cpu); |
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void (*tlbdump)(struct machine *m, int x, |
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int rawflag); |
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int (*interrupt)(struct cpu *cpu, uint64_t irq_nr); |
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int (*interrupt_ack)(struct cpu *cpu, |
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uint64_t irq_nr); |
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dpavlin |
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void (*functioncall_trace)(struct cpu *, |
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uint64_t f, int n_args); |
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dpavlin |
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char *(*gdb_stub)(struct cpu *, char *cmd); |
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dpavlin |
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void (*init_tables)(struct cpu *cpu); |
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dpavlin |
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}; |
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dpavlin |
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/* |
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* More dyntrans stuff: |
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* |
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* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets |
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* into the cache, for possible translation cache structs for physical pages. |
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*/ |
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/* Physpage flags: */ |
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#define COMBINATIONS 1 |
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dpavlin |
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/* Meaning of delay_slot: */ |
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#define NOT_DELAYED 0 |
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#define DELAYED 1 |
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#define TO_BE_DELAYED 2 |
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#define EXCEPTION_IN_DELAY_SLOT 0x100 |
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#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14 |
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#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1) |
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#define DYNTRANS_CACHE_SIZE (32*1048576) |
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#define DYNTRANS_CACHE_MARGIN 350000 |
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#define N_BASE_TABLE_ENTRIES 32768 |
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#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
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/* |
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* The generic CPU struct: |
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*/ |
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struct cpu { |
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/* Pointer back to the machine this CPU is in: */ |
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struct machine *machine; |
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int byte_order; |
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int running; |
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int dead; |
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int bootstrap_cpu_flag; |
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int cpu_id; |
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dpavlin |
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int is_32bit; /* 0 for 64-bit, 1 for 32-bit */ |
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char *name; |
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struct memory *mem; |
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dpavlin |
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int (*run_instr)(struct cpu *cpu); |
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dpavlin |
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int (*memory_rw)(struct cpu *cpu, |
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struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, |
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int writeflag, int cache_flags); |
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dpavlin |
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int (*translate_v2p)(struct cpu *, uint64_t vaddr, |
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uint64_t *return_paddr, int flags); |
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dpavlin |
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void (*update_translation_table)(struct cpu *, |
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uint64_t vaddr_page, unsigned char *host_page, |
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int writeflag, uint64_t paddr_page); |
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dpavlin |
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void (*invalidate_translation_caches)(struct cpu *, |
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uint64_t paddr, int flags); |
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void (*invalidate_code_translation)(struct cpu *, |
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uint64_t paddr, int flags); |
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dpavlin |
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void (*useremul_syscall)(struct cpu *cpu, uint32_t code); |
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dpavlin |
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int (*instruction_has_delayslot)(struct cpu *cpu, |
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unsigned char *ib); |
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dpavlin |
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uint64_t pc; |
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dpavlin |
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int trace_tree_depth; |
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/* |
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* Dynamic translation: |
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*/ |
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int running_translated; |
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int n_translated_instrs; |
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unsigned char *translation_cache; |
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size_t translation_cache_cur_ofs; |
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dpavlin |
24 |
uint64_t delay_jmpaddr; /* only used if delay_slot > 0 */ |
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int delay_slot; |
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dpavlin |
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/* |
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* CPU-family dependent: |
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*/ |
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dpavlin |
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union { |
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dpavlin |
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struct alpha_cpu alpha; |
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struct arm_cpu arm; |
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struct avr_cpu avr; |
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struct hppa_cpu hppa; |
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struct i960_cpu i960; |
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struct ia64_cpu ia64; |
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struct m68k_cpu m68k; |
| 338 |
|
|
struct mips_cpu mips; |
| 339 |
|
|
struct ppc_cpu ppc; |
| 340 |
|
|
struct sh_cpu sh; |
| 341 |
|
|
struct sparc_cpu sparc; |
| 342 |
|
|
struct transputer_cpu transputer; |
| 343 |
|
|
struct x86_cpu x86; |
| 344 |
dpavlin |
4 |
} cd; |
| 345 |
|
|
}; |
| 346 |
|
|
|
| 347 |
|
|
|
| 348 |
|
|
/* cpu.c: */ |
| 349 |
|
|
struct cpu *cpu_new(struct memory *mem, struct machine *machine, |
| 350 |
|
|
int cpu_id, char *cpu_type_name); |
| 351 |
|
|
void cpu_tlbdump(struct machine *m, int x, int rawflag); |
| 352 |
|
|
void cpu_register_match(struct machine *m, char *name, |
| 353 |
|
|
int writeflag, uint64_t *valuep, int *match_register); |
| 354 |
|
|
void cpu_register_dump(struct machine *m, struct cpu *cpu, |
| 355 |
|
|
int gprs, int coprocs); |
| 356 |
|
|
int cpu_disassemble_instr(struct machine *m, struct cpu *cpu, |
| 357 |
dpavlin |
24 |
unsigned char *instr, int running, uint64_t addr); |
| 358 |
|
|
char *cpu_gdb_stub(struct cpu *cpu, char *cmd); |
| 359 |
dpavlin |
4 |
int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
| 360 |
|
|
int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
| 361 |
dpavlin |
12 |
void cpu_functioncall_trace(struct cpu *cpu, uint64_t f); |
| 362 |
|
|
void cpu_functioncall_trace_return(struct cpu *cpu); |
| 363 |
|
|
void cpu_create_or_reset_tc(struct cpu *cpu); |
| 364 |
|
|
void cpu_run_init(struct machine *machine); |
| 365 |
|
|
void cpu_run_deinit(struct machine *machine); |
| 366 |
dpavlin |
4 |
void cpu_dumpinfo(struct machine *m, struct cpu *cpu); |
| 367 |
|
|
void cpu_list_available_types(void); |
| 368 |
dpavlin |
10 |
void cpu_show_cycles(struct machine *machine, int forced); |
| 369 |
dpavlin |
4 |
struct cpu_family *cpu_family_ptr_by_number(int arch); |
| 370 |
|
|
void cpu_init(void); |
| 371 |
|
|
|
| 372 |
|
|
|
| 373 |
dpavlin |
14 |
#define JUST_MARK_AS_NON_WRITABLE 1 |
| 374 |
|
|
#define INVALIDATE_ALL 2 |
| 375 |
|
|
#define INVALIDATE_PADDR 4 |
| 376 |
|
|
#define INVALIDATE_VADDR 8 |
| 377 |
dpavlin |
22 |
#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */ |
| 378 |
dpavlin |
14 |
|
| 379 |
|
|
|
| 380 |
dpavlin |
12 |
#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
| 381 |
|
|
struct cpu_family *fp) { \ |
| 382 |
|
|
/* Fill in the cpu_family struct with valid data for this arch. */ \ |
| 383 |
|
|
fp->name = s; \ |
| 384 |
|
|
fp->cpu_new = n ## _cpu_new; \ |
| 385 |
|
|
fp->list_available_types = n ## _cpu_list_available_types; \ |
| 386 |
|
|
fp->register_match = n ## _cpu_register_match; \ |
| 387 |
|
|
fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
| 388 |
|
|
fp->register_dump = n ## _cpu_register_dump; \ |
| 389 |
|
|
fp->dumpinfo = n ## _cpu_dumpinfo; \ |
| 390 |
dpavlin |
20 |
fp->interrupt = n ## _cpu_interrupt; \ |
| 391 |
|
|
fp->interrupt_ack = n ## _cpu_interrupt_ack; \ |
| 392 |
|
|
fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
| 393 |
dpavlin |
24 |
fp->gdb_stub = n ## _cpu_gdb_stub; \ |
| 394 |
dpavlin |
12 |
fp->tlbdump = n ## _cpu_tlbdump; \ |
| 395 |
dpavlin |
26 |
fp->init_tables = n ## _cpu_init_tables; \ |
| 396 |
dpavlin |
12 |
return 1; \ |
| 397 |
|
|
} |
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
dpavlin |
4 |
#endif /* CPU_H */ |
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