/[gxemul]/trunk/src/include/cpu.h
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Annotation of /trunk/src/include/cpu.h

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Revision 20 - (hide annotations)
Mon Oct 8 16:19:23 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8307 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============
1 dpavlin 4 #ifndef CPU_H
2     #define CPU_H
3    
4     /*
5     * Copyright (C) 2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 20 * $Id: cpu.h,v 1.54 2005/11/16 21:15:19 debug Exp $
32 dpavlin 4 *
33     * See cpu.c.
34     */
35    
36    
37     #include <sys/types.h>
38     #include <inttypes.h>
39     #include <sys/time.h>
40    
41     /* This is needed for undefining 'mips' or 'ppc', on weird systems: */
42     #include "../../config.h"
43    
44 dpavlin 14 #include "cpu_alpha.h"
45 dpavlin 6 #include "cpu_arm.h"
46 dpavlin 14 #include "cpu_avr.h"
47     #include "cpu_hppa.h"
48     #include "cpu_i960.h"
49 dpavlin 12 #include "cpu_ia64.h"
50     #include "cpu_m68k.h"
51 dpavlin 4 #include "cpu_mips.h"
52 dpavlin 20 #include "cpu_newmips.h"
53 dpavlin 4 #include "cpu_ppc.h"
54 dpavlin 14 #include "cpu_sh.h"
55 dpavlin 12 #include "cpu_sparc.h"
56 dpavlin 4 #include "cpu_x86.h"
57    
58     struct cpu;
59     struct emul;
60     struct machine;
61     struct memory;
62    
63    
64     struct cpu_family {
65     struct cpu_family *next;
66     int arch;
67    
68     /* These are filled in by each CPU family's init function: */
69     char *name;
70 dpavlin 10 int (*cpu_new)(struct cpu *cpu, struct memory *mem,
71 dpavlin 4 struct machine *machine,
72     int cpu_id, char *cpu_type_name);
73     void (*list_available_types)(void);
74     void (*register_match)(struct machine *m,
75     char *name, int writeflag,
76     uint64_t *valuep, int *match_register);
77     int (*disassemble_instr)(struct cpu *cpu,
78     unsigned char *instr, int running,
79     uint64_t dumpaddr, int bintrans);
80     void (*register_dump)(struct cpu *cpu,
81     int gprs, int coprocs);
82     int (*run)(struct emul *emul,
83     struct machine *machine);
84     void (*dumpinfo)(struct cpu *cpu);
85     void (*show_full_statistics)(struct machine *m);
86     void (*tlbdump)(struct machine *m, int x,
87     int rawflag);
88     int (*interrupt)(struct cpu *cpu, uint64_t irq_nr);
89     int (*interrupt_ack)(struct cpu *cpu,
90     uint64_t irq_nr);
91 dpavlin 12 void (*functioncall_trace)(struct cpu *,
92     uint64_t f, int n_args);
93 dpavlin 4 };
94    
95 dpavlin 8 #ifdef TRACE_NULL_CRASHES
96     #define TRACE_NULL_N_ENTRIES 16
97     #endif
98 dpavlin 4
99 dpavlin 12
100     /*
101     * Dynamic translation definitions:
102     *
103     * The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
104     * into the cache, for possible translation cache structs for physical pages.
105     */
106    
107     /* Physpage flags: */
108     #define TRANSLATIONS 1
109     #define COMBINATIONS 2
110    
111 dpavlin 18 #define DYNTRANS_CACHE_SIZE (20*1048576)
112 dpavlin 12 #define DYNTRANS_CACHE_MARGIN 300000
113    
114     #define N_BASE_TABLE_ENTRIES 32768
115     #define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1))
116    
117    
118     /*
119     * The generic CPU struct:
120     */
121    
122 dpavlin 4 struct cpu {
123     /* Pointer back to the machine this CPU is in: */
124     struct machine *machine;
125    
126     int byte_order;
127     int running;
128     int dead;
129     int bootstrap_cpu_flag;
130     int cpu_id;
131 dpavlin 12 int is_32bit; /* 0 for 64-bit, 1 for 32-bit */
132 dpavlin 4 char *name;
133    
134     struct memory *mem;
135     int (*memory_rw)(struct cpu *cpu,
136     struct memory *mem, uint64_t vaddr,
137     unsigned char *data, size_t len,
138     int writeflag, int cache_flags);
139     int (*translate_address)(struct cpu *, uint64_t vaddr,
140     uint64_t *return_addr, int flags);
141 dpavlin 12 void (*update_translation_table)(struct cpu *,
142     uint64_t vaddr_page, unsigned char *host_page,
143     int writeflag, uint64_t paddr_page);
144 dpavlin 18 void (*invalidate_translation_caches)(struct cpu *,
145 dpavlin 14 uint64_t paddr, int flags);
146     void (*invalidate_code_translation)(struct cpu *,
147     uint64_t paddr, int flags);
148 dpavlin 12 void (*useremul_syscall)(struct cpu *cpu, uint32_t code);
149 dpavlin 4
150     uint64_t pc;
151    
152 dpavlin 8 #ifdef TRACE_NULL_CRASHES
153 dpavlin 14 /* TODO: remove this, it's MIPS only */
154 dpavlin 12 int trace_null_index;
155 dpavlin 8 uint64_t trace_null_addr[TRACE_NULL_N_ENTRIES];
156     #endif
157    
158 dpavlin 12 int trace_tree_depth;
159    
160     /*
161     * Dynamic translation:
162     */
163     int running_translated;
164     int n_translated_instrs;
165     unsigned char *translation_cache;
166     size_t translation_cache_cur_ofs;
167    
168     /*
169     * CPU-family dependent:
170     */
171 dpavlin 4 union {
172 dpavlin 12 struct alpha_cpu alpha;
173 dpavlin 6 struct arm_cpu arm;
174 dpavlin 14 struct avr_cpu avr;
175     struct hppa_cpu hppa;
176     struct i960_cpu i960;
177 dpavlin 12 struct ia64_cpu ia64;
178     struct m68k_cpu m68k;
179 dpavlin 4 struct mips_cpu mips;
180 dpavlin 20 struct newmips_cpu newmips;
181 dpavlin 4 struct ppc_cpu ppc;
182 dpavlin 14 struct sh_cpu sh;
183 dpavlin 12 struct sparc_cpu sparc;
184 dpavlin 4 struct x86_cpu x86;
185     } cd;
186     };
187    
188    
189     /* cpu.c: */
190     struct cpu *cpu_new(struct memory *mem, struct machine *machine,
191     int cpu_id, char *cpu_type_name);
192     void cpu_show_full_statistics(struct machine *m);
193     void cpu_tlbdump(struct machine *m, int x, int rawflag);
194     void cpu_register_match(struct machine *m, char *name,
195     int writeflag, uint64_t *valuep, int *match_register);
196     void cpu_register_dump(struct machine *m, struct cpu *cpu,
197     int gprs, int coprocs);
198     int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
199     unsigned char *instr, int running, uint64_t addr, int bintrans);
200     int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
201     int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
202 dpavlin 12 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
203     void cpu_functioncall_trace_return(struct cpu *cpu);
204     void cpu_create_or_reset_tc(struct cpu *cpu);
205     void cpu_run_init(struct machine *machine);
206 dpavlin 4 int cpu_run(struct emul *emul, struct machine *machine);
207 dpavlin 12 void cpu_run_deinit(struct machine *machine);
208 dpavlin 4 void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
209     void cpu_list_available_types(void);
210 dpavlin 10 void cpu_show_cycles(struct machine *machine, int forced);
211 dpavlin 4 struct cpu_family *cpu_family_ptr_by_number(int arch);
212     void cpu_init(void);
213    
214    
215 dpavlin 14 #define JUST_MARK_AS_NON_WRITABLE 1
216     #define INVALIDATE_ALL 2
217     #define INVALIDATE_PADDR 4
218     #define INVALIDATE_VADDR 8
219    
220 dpavlin 18 #define TLB_CODE 0x02
221 dpavlin 14
222 dpavlin 18
223 dpavlin 12 #define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
224     struct cpu_family *fp) { \
225     /* Fill in the cpu_family struct with valid data for this arch. */ \
226     fp->name = s; \
227     fp->cpu_new = n ## _cpu_new; \
228     fp->list_available_types = n ## _cpu_list_available_types; \
229     fp->register_match = n ## _cpu_register_match; \
230     fp->disassemble_instr = n ## _cpu_disassemble_instr; \
231     fp->register_dump = n ## _cpu_register_dump; \
232     fp->run = n ## _cpu_run; \
233     fp->dumpinfo = n ## _cpu_dumpinfo; \
234 dpavlin 20 fp->interrupt = n ## _cpu_interrupt; \
235     fp->interrupt_ack = n ## _cpu_interrupt_ack; \
236     fp->functioncall_trace = n ## _cpu_functioncall_trace; \
237     return 1; \
238     }
239    
240     #define CPU_OLD_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
241     struct cpu_family *fp) { \
242     /* Fill in the cpu_family struct with valid data for this arch. */ \
243     fp->name = s; \
244     fp->cpu_new = n ## _cpu_new; \
245     fp->list_available_types = n ## _cpu_list_available_types; \
246     fp->register_match = n ## _cpu_register_match; \
247     fp->disassemble_instr = n ## _cpu_disassemble_instr; \
248     fp->register_dump = n ## _cpu_register_dump; \
249     fp->run = n ## _cpu_run; \
250     fp->dumpinfo = n ## _cpu_dumpinfo; \
251 dpavlin 12 fp->show_full_statistics = n ## _cpu_show_full_statistics; \
252     fp->tlbdump = n ## _cpu_tlbdump; \
253     fp->interrupt = n ## _cpu_interrupt; \
254     fp->interrupt_ack = n ## _cpu_interrupt_ack; \
255     fp->functioncall_trace = n ## _cpu_functioncall_trace; \
256     return 1; \
257     }
258    
259    
260 dpavlin 4 #endif /* CPU_H */
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