/[gxemul]/trunk/src/include/cpu.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/include/cpu.h

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Revision 14 - (hide annotations)
Mon Oct 8 16:18:51 2007 UTC (13 years, 3 months ago) by dpavlin
File MIME type: text/plain
File size: 7538 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.982 2005/10/07 22:45:32 debug Exp $
20050816	Some success in decoding the way the SGI O2 PROM draws graphics
		during bootup; lines/rectangles and bitmaps work, enough to
		show the bootlogo etc. :-)
		Adding more PPC instructions, and (dummy) BAT registers.
20050817	Updating the pckbc to support scancode type 3 keyboards
		(required in order to interact with the SGI O2 PROM).
		Adding more PPC instructions.
20050818	Adding more ARM instructions; general register forms.
		Importing armreg.h from NetBSD (ARM cpu ids). Adding a (dummy)
		CATS machine mode (using SA110 as the default CPU).
		Continuing on general dyntrans related stuff.
20050819	Register forms for ARM load/stores. Gaah! The Compaq C Compiler
		bug is triggered for ARM loads as well, not just PPC :-(
		Adding full support for ARM PC-relative load/stores, and load/
		stores where the PC register is the destination register.
		Adding support for ARM a.out binaries.
20050820	Continuing to add more ARM instructions, and correcting some
		bugs. Continuing on CATS emulation.
		More work on the PPC stuff.
20050821	Minor PPC and ARM updates. Adding more machine types.
20050822	All ARM "data processing instructions" are now generated
		automatically.
20050824	Beginning the work on the ARM system control coprocessor.
		Adding support for ARM halfword load/stores, and signed loads.
20050825	Fixing an important bug related to the ARM condition codes.
		OpenBSD/zaurus and NetBSD/netwinder now print some boot
		messages. :)
		Adding a dummy SH (Hitachi SuperH) cpu family.
		Beginning to add some ARM virtual address translation.
		MIPS bugfixes: unaligned PC now cause an ADEL exception (at
		least for non-bintrans execution), and ADEL/ADES (not
		TLBL/TLBS) are used if userland tries to access kernel space.
		(Thanks to Joshua Wise for making me aware of these bugs.)
20050827	More work on the ARM emulation, and various other updates.
20050828	More ARM updates.
		Finally taking the time to work on translation invalidation
		(i.e. invalidating translated code mappings when memory is
		written to). Hopefully this doesn't break anything.
20050829	Moving CPU related files from src/ to a new subdir, src/cpus/.
		Moving PROM emulation stuff from src/ to src/promemul/.
		Better debug instruction trace for ARM loads and stores.
20050830	Various ARM updates (correcting CMP flag calculation, etc).
20050831	PPC instruction updates. (Flag fixes, etc.)
20050901	Various minor PPC and ARM instruction emulation updates.
		Minor OpenFirmware emulation updates.
20050903	Adding support for adding arbitrary ARM coprocessors (with
		the i80321 I/O coprocessor as a first test).
		Various other ARM and PPC updates.
20050904	Adding some SHcompact disassembly routines.
20050907	(Re)adding a dummy HPPA CPU module, and a dummy i960 module.
20050908	Began hacking on some Apple Partition Table support.
20050909	Adding support for loading Mach-O (Darwin PPC) binaries.
20050910	Fixing an ARM bug (Carry flag was incorrectly updated for some
		data processing instructions); OpenBSD/cats and NetBSD/
		netwinder get quite a bit further now.
		Applying a patch to dev_wdc, and a one-liner to dev_pcic, to
		make them work better when emulating new versions of OpenBSD.
		(Thanks to Alexander Yurchenko for the patches.)
		Also doing some other minor updates to dev_wdc. (Some cleanup,
		and finally converting to devinit, etc.)
20050912	IRIX doesn't have u_int64_t by default (noticed by Andreas
		<avr@gnulinux.nl>); configure updated to reflect this.
		Working on ARM register bank switching, CPSR vs SPSR issues,
		and beginning the work on interrupt/exception support.
20050913	Various minor ARM updates (speeding up load/store multiple,
		and fixing a ROR bug in R(); NetBSD/cats now boots as far as
		OpenBSD/cats).
20050917	Adding a dummy Atmel AVR (8-bit) cpu family skeleton.
20050918	Various minor updates.
20050919	Symbols are now loaded from Mach-O executables.
		Continuing the work on adding ARM exception support.
20050920	More work on ARM stuff: OpenBSD/cats and NetBSD/cats reach
		userland! :-)
20050921	Some more progress on ARM interrupt specifics.
20050923	Fixing linesize for VR4121 (patch by Yurchenko). Also fixing
		linesizes/cachesizes for some other VR4xxx.
		Adding a dummy Acer Labs M1543 PCI-ISA bridge (for CATS) and a
		dummy Symphony Labs 83C553 bridge (for Netwinder), usable by 
		dev_footbridge.
20050924	Some PPC progress.
20050925	More PPC progress.
20050926	PPC progress (fixing some bugs etc); Darwin's kernel gets
		slightly further than before.
20050928	Various updates: footbridge/ISA/pciide stuff, and finally
		fixing the VGA text scroll-by-changing-the-base-offset bug.
20050930	Adding a dummy S3 ViRGE pci card for CATS emulation, which
		both NetBSD and OpenBSD detects as VGA.
		Continuing on Footbridge (timers, ISA interrupt stuff).
20051001	Continuing... there are still bugs, probably interrupt-
		related.
20051002	More work on the Footbridge (interrupt stuff).
20051003	Various minor updates. (Trying to find the bug(s).)
20051004	Continuing on the ARM stuff.
20051005	More ARM-related fixes.
20051007	FINALLY! Found and fixed 2 ARM bugs: 1 memory related, and the
		other was because of an error in the ARM manual (load multiple
		with the S-bit set should _NOT_ load usermode registers, as the
		manual says, but it should load saved registers, which may or
		may not happen to be usermode registers).
		NetBSD/cats and OpenBSD/cats seem to install fine now :-)
		except for a minor bug at the end of the OpenBSD/cats install.
		Updating the documentation, preparing for the next release.
20051008	Continuing with release testing and cleanup.

1 dpavlin 4 #ifndef CPU_H
2     #define CPU_H
3    
4     /*
5     * Copyright (C) 2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31 dpavlin 14 * $Id: cpu.h,v 1.48 2005/09/17 17:14:28 debug Exp $
32 dpavlin 4 *
33     * See cpu.c.
34     */
35    
36    
37     #include <sys/types.h>
38     #include <inttypes.h>
39     #include <sys/time.h>
40    
41     /* This is needed for undefining 'mips' or 'ppc', on weird systems: */
42     #include "../../config.h"
43    
44 dpavlin 14 #include "cpu_alpha.h"
45 dpavlin 6 #include "cpu_arm.h"
46 dpavlin 14 #include "cpu_avr.h"
47     #include "cpu_hppa.h"
48     #include "cpu_i960.h"
49 dpavlin 12 #include "cpu_ia64.h"
50     #include "cpu_m68k.h"
51 dpavlin 4 #include "cpu_mips.h"
52     #include "cpu_ppc.h"
53 dpavlin 14 #include "cpu_sh.h"
54 dpavlin 12 #include "cpu_sparc.h"
55 dpavlin 4 #include "cpu_x86.h"
56    
57     struct cpu;
58     struct emul;
59     struct machine;
60     struct memory;
61    
62    
63     struct cpu_family {
64     struct cpu_family *next;
65     int arch;
66    
67     /* These are filled in by each CPU family's init function: */
68     char *name;
69 dpavlin 10 int (*cpu_new)(struct cpu *cpu, struct memory *mem,
70 dpavlin 4 struct machine *machine,
71     int cpu_id, char *cpu_type_name);
72     void (*list_available_types)(void);
73     void (*register_match)(struct machine *m,
74     char *name, int writeflag,
75     uint64_t *valuep, int *match_register);
76     int (*disassemble_instr)(struct cpu *cpu,
77     unsigned char *instr, int running,
78     uint64_t dumpaddr, int bintrans);
79     void (*register_dump)(struct cpu *cpu,
80     int gprs, int coprocs);
81     int (*run)(struct emul *emul,
82     struct machine *machine);
83     void (*dumpinfo)(struct cpu *cpu);
84     void (*show_full_statistics)(struct machine *m);
85     void (*tlbdump)(struct machine *m, int x,
86     int rawflag);
87     int (*interrupt)(struct cpu *cpu, uint64_t irq_nr);
88     int (*interrupt_ack)(struct cpu *cpu,
89     uint64_t irq_nr);
90 dpavlin 12 void (*functioncall_trace)(struct cpu *,
91     uint64_t f, int n_args);
92 dpavlin 4 };
93    
94 dpavlin 8 #ifdef TRACE_NULL_CRASHES
95     #define TRACE_NULL_N_ENTRIES 16
96     #endif
97 dpavlin 4
98 dpavlin 12
99     /*
100     * Dynamic translation definitions:
101     *
102     * The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets
103     * into the cache, for possible translation cache structs for physical pages.
104     */
105    
106     /* Physpage flags: */
107     #define TRANSLATIONS 1
108     #define COMBINATIONS 2
109    
110     #define DYNTRANS_CACHE_SIZE (16*1048576)
111     #define DYNTRANS_CACHE_MARGIN 300000
112    
113     #define N_BASE_TABLE_ENTRIES 32768
114     #define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1))
115    
116    
117     /*
118     * The generic CPU struct:
119     */
120    
121 dpavlin 4 struct cpu {
122     /* Pointer back to the machine this CPU is in: */
123     struct machine *machine;
124    
125     int byte_order;
126     int running;
127     int dead;
128     int bootstrap_cpu_flag;
129     int cpu_id;
130 dpavlin 12 int is_32bit; /* 0 for 64-bit, 1 for 32-bit */
131 dpavlin 4 char *name;
132    
133     struct memory *mem;
134     int (*memory_rw)(struct cpu *cpu,
135     struct memory *mem, uint64_t vaddr,
136     unsigned char *data, size_t len,
137     int writeflag, int cache_flags);
138     int (*translate_address)(struct cpu *, uint64_t vaddr,
139     uint64_t *return_addr, int flags);
140 dpavlin 12 void (*update_translation_table)(struct cpu *,
141     uint64_t vaddr_page, unsigned char *host_page,
142     int writeflag, uint64_t paddr_page);
143     void (*invalidate_translation_caches_paddr)(struct cpu *,
144 dpavlin 14 uint64_t paddr, int flags);
145     void (*invalidate_code_translation)(struct cpu *,
146     uint64_t paddr, int flags);
147 dpavlin 12 void (*useremul_syscall)(struct cpu *cpu, uint32_t code);
148 dpavlin 4
149     uint64_t pc;
150    
151 dpavlin 8 #ifdef TRACE_NULL_CRASHES
152 dpavlin 14 /* TODO: remove this, it's MIPS only */
153 dpavlin 12 int trace_null_index;
154 dpavlin 8 uint64_t trace_null_addr[TRACE_NULL_N_ENTRIES];
155     #endif
156    
157 dpavlin 12 int trace_tree_depth;
158    
159     /*
160     * Dynamic translation:
161     */
162     int running_translated;
163     int n_translated_instrs;
164     unsigned char *translation_cache;
165     size_t translation_cache_cur_ofs;
166    
167     /*
168     * CPU-family dependent:
169     */
170 dpavlin 4 union {
171 dpavlin 12 struct alpha_cpu alpha;
172 dpavlin 6 struct arm_cpu arm;
173 dpavlin 14 struct avr_cpu avr;
174     struct hppa_cpu hppa;
175     struct i960_cpu i960;
176 dpavlin 12 struct ia64_cpu ia64;
177     struct m68k_cpu m68k;
178 dpavlin 4 struct mips_cpu mips;
179     struct ppc_cpu ppc;
180 dpavlin 14 struct sh_cpu sh;
181 dpavlin 12 struct sparc_cpu sparc;
182 dpavlin 4 struct x86_cpu x86;
183     } cd;
184     };
185    
186    
187     /* cpu.c: */
188     struct cpu *cpu_new(struct memory *mem, struct machine *machine,
189     int cpu_id, char *cpu_type_name);
190     void cpu_show_full_statistics(struct machine *m);
191     void cpu_tlbdump(struct machine *m, int x, int rawflag);
192     void cpu_register_match(struct machine *m, char *name,
193     int writeflag, uint64_t *valuep, int *match_register);
194     void cpu_register_dump(struct machine *m, struct cpu *cpu,
195     int gprs, int coprocs);
196     int cpu_disassemble_instr(struct machine *m, struct cpu *cpu,
197     unsigned char *instr, int running, uint64_t addr, int bintrans);
198     int cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
199     int cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
200 dpavlin 12 void cpu_functioncall_trace(struct cpu *cpu, uint64_t f);
201     void cpu_functioncall_trace_return(struct cpu *cpu);
202     void cpu_create_or_reset_tc(struct cpu *cpu);
203     void cpu_run_init(struct machine *machine);
204 dpavlin 4 int cpu_run(struct emul *emul, struct machine *machine);
205 dpavlin 12 void cpu_run_deinit(struct machine *machine);
206 dpavlin 4 void cpu_dumpinfo(struct machine *m, struct cpu *cpu);
207     void cpu_list_available_types(void);
208 dpavlin 10 void cpu_show_cycles(struct machine *machine, int forced);
209 dpavlin 4 struct cpu_family *cpu_family_ptr_by_number(int arch);
210     void cpu_init(void);
211    
212    
213 dpavlin 14 #define JUST_MARK_AS_NON_WRITABLE 1
214     #define INVALIDATE_ALL 2
215     #define INVALIDATE_PADDR 4
216     #define INVALIDATE_VADDR 8
217    
218    
219 dpavlin 12 #define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \
220     struct cpu_family *fp) { \
221     /* Fill in the cpu_family struct with valid data for this arch. */ \
222     fp->name = s; \
223     fp->cpu_new = n ## _cpu_new; \
224     fp->list_available_types = n ## _cpu_list_available_types; \
225     fp->register_match = n ## _cpu_register_match; \
226     fp->disassemble_instr = n ## _cpu_disassemble_instr; \
227     fp->register_dump = n ## _cpu_register_dump; \
228     fp->run = n ## _cpu_run; \
229     fp->dumpinfo = n ## _cpu_dumpinfo; \
230     fp->show_full_statistics = n ## _cpu_show_full_statistics; \
231     fp->tlbdump = n ## _cpu_tlbdump; \
232     fp->interrupt = n ## _cpu_interrupt; \
233     fp->interrupt_ack = n ## _cpu_interrupt_ack; \
234     fp->functioncall_trace = n ## _cpu_functioncall_trace; \
235     return 1; \
236     }
237    
238    
239 dpavlin 4 #endif /* CPU_H */

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