/[gxemul]/trunk/src/include/cpc700reg.h
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Contents of /trunk/src/include/cpc700reg.h

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Revision 20 - (show annotations)
Mon Oct 8 16:19:23 2007 UTC (12 years ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1055 2005/11/25 22:48:36 debug Exp $
20051031	Adding disassembly support for more ARM instructions (clz,
		smul* etc), and adding a hack to support "new tiny" pages
		for StrongARM.
20051101	Minor documentation updates (NetBSD 2.0.2 -> 2.1, and OpenBSD
		3.7 -> 3.8, and lots of testing).
		Changing from 1-sector PIO mode 0 transfers to 128-sector PIO
		mode 3 (in dev_wdc).
		Various minor ARM dyntrans updates (pc-relative loads from
		within the same page as the instruction are now treated as
		constant "mov").
20051102	Re-enabling instruction combinations (they were accidentally
		disabled).
		Dyntrans TLB entries are now overwritten using a round-robin
		scheme instead of randomly. This increases performance.
		Fixing a typo in file.c (thanks to Chuan-Hua Chang for
		noticing it).
		Experimenting with adding ATAPI support to dev_wdc (to make
		emulated *BSD detect cdroms as cdroms, not harddisks).
20051104	Various minor updates.
20051105	Continuing on the ATAPI emulation. Seems to work well enough
		for a NetBSD/cats installation, but not OpenBSD/cats.
		Various other updates.
20051106	Modifying the -Y command line option to allow scaleup with
		certain graphic controllers (only dev_vga so far), not just
		scaledown.
		Some minor dyntrans cleanups.
20051107	Beginning a cleanup up the PCI subsystem (removing the
		read_register hack, etc).
20051108	Continuing the cleanup; splitting up some pci devices into a
		normal autodev device and some separate pci glue code.
20051109	Continuing on the PCI bus stuff; all old pci_*.c have been
		incorporated into normal devices and/or rewritten as glue code
		only, adding a dummy Intel 82371AB PIIX4 for Malta (not really
		tested yet).
		Minor pckbc fix so that Linux doesn't complain.
		Working on the DEC 21143 NIC (ethernet mac rom stuff mostly).
		Various other minor fixes.
20051110	Some more ARM dyntrans fine-tuning (e.g. some instruction
		combinations (cmps followed by conditional branch within the
		same page) and special cases for DPIs with regform when the
		shifter isn't used).
20051111	ARM dyntrans updates: O(n)->O(1) for just-mark-as-non-
		writable in the generic pc_to_pointers function, and some other
		minor hacks.
		Merging Cobalt and evbmips (Malta) ISA interrupt handling,
		and some minor fixes to allow Linux to accept harddisk irqs.
20051112	Minor device updates (pckbc, dec21143, lpt, ...), most
		importantly fixing the ALI M1543/M5229 so that harddisk irqs
		work with Linux/CATS.
20051113	Some more generalizations of the PCI subsystem.
		Finally took the time to add a hack for SCSI CDROM TOCs; this
		enables OpenBSD to use partition 'a' (as needed by the OpenBSD
		installer), and Windows NT's installer to get a bit further.
		Also fixing dev_wdc to allow Linux to detect ATAPI CDROMs.
		Continuing on the DEC 21143.
20051114	Minor ARM dyntrans tweaks; ARM cmps+branch optimization when
		comparing with 0, and generalizing the xchg instr. comb.
		Adding disassembly of ARM mrrc/mcrr and q{,d}{add,sub}.
20051115	Continuing on various PPC things (BATs, other address trans-
		lation things, various loads/stores, BeBox emulation, etc.).
		Beginning to work on PPC interrupt/exception support.
20051116	Factoring out some code which initializes legacy ISA devices
		from those machines that use them (bus_isa).
		Continuing on PPC interrupt/exception support.
20051117	Minor Malta fixes: RTC year offset = 80, disabling a speed hack
		which caused NetBSD to detect a too fast cpu, and adding a new
		hack to make Linux detect a faster cpu.
		Continuing on the Artesyn PM/PPC emulation mode.
		Adding an Algor emulation skeleton (P4032 and P5064);
		implementing some of the basics.
		Continuing on PPC emulation in general; usage of unimplemented
		SPRs is now easier to track, continuing on memory/exception
		related issues, etc.
20051118	More work on PPC emulation (tgpr0..3, exception handling,
		memory stuff, syscalls, etc.).
20051119	Changing the ARM dyntrans code to mostly use cpu->pc, and not
		necessarily use arm reg 15. Seems to work.
		Various PPC updates; continuing on the PReP emulation mode.
20051120	Adding a workaround/hack to dev_mc146818 to allow NetBSD/prep
		to detect the clock.
20051121	More cleanup of the PCI bus (memory and I/O bases, etc).
		Continuing on various PPC things (decrementer and timebase,
		WDCs on obio (on PReP) use irq 13, not 14/15).
20051122	Continuing on the CPC700 controller (interrupts etc) for PMPPC,
		and on PPC stuff in general.
		Finally! After some bug fixes to the virtual to physical addr
		translation, NetBSD/{prep,pmppc} 2.1 reach userland and are
		stable enough to be interacted with.
		More PCI updates; reverse-endian device access for PowerPC etc.
20051123	Generalizing the IEEE floating point subsystem (moving it out
		from src/cpus/cpu_mips_coproc.c into a new src/float_emul.c).
		Input via slave xterms was sometimes not really working; fixing
		this for ns16550, and a warning message is now displayed if
		multiple non-xterm consoles are active.
		Adding some PPC floating point support, etc.
		Various interrupt related updates (dev_wdc, _ns16550, _8259,
		and the isa32 common code in machine.c).
		NetBSD/prep can now be installed! :-) (Well, with some manual
		commands necessary before running sysinst.) Updating the
		documentation and various other things to reflect this.
20051124	Various minor documentation updates.
		Continuing the work on the DEC 21143 NIC.
20051125	LOTS of work on the 21143. Both OpenBSD and NetBSD work fine
		with it now, except that OpenBSD sometimes gives a time-out
		warning.
		Minor documentation updates.

==============  RELEASE 0.3.7  ==============


1 /* GXemul: $Id: cpc700reg.h,v 1.2 2005/11/23 23:31:37 debug Exp $ */
2 /* $NetBSD: cpc700reg.h,v 1.3 2003/11/07 17:03:42 augustss Exp $ */
3
4 #ifndef CPC700REG_H
5 #define CPC700REG_H
6
7 /*
8 * Copyright (c) 2002 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to The NetBSD Foundation
12 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the NetBSD
25 * Foundation, Inc. and its contributors.
26 * 4. Neither the name of The NetBSD Foundation nor the names of its
27 * contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
31 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
34 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43 /* PCI memory space */
44 #define CPC_PCI_MEM_BASE 0x80000000
45 #define CPC_PCI_MEM_END 0xf7ffffff
46
47 /* PCI IO space */
48 #define CPC_PCI_IO_BASE 0xf8000000
49 #define CPC_PCI_IO_START 0xf8800000 /* for allocation */
50 #define CPC_PCI_IO_END 0xfbffffff
51
52 /* PCI config space */
53 #define CPC_PCICFGADR 0xfec00000
54 #define CPC_PCI_CONFIG_ENABLE 0x80000000
55 #define CPC_PCICFGDATA 0xfec00004
56
57 /* Config space regs */
58 #define CPC_PCI_BRDGERR 0x48
59 #define CPC_PCI_CLEARERR 0x0000ff00
60
61 #define CPC_BRIDGE_OPTIONS2 0x60
62 #define CPC_BRIDGE_O2_ILAT_MASK 0x00f8
63 #define CPC_BRIDGE_O2_ILAT_SHIFT 3
64 #define CPC_BRIDGE_O2_ILAT_PRIM_ASYNC 18
65 #define CPC_BRIDGE_O2_SLAT_MASK 0x0f00
66 #define CPC_BRIDGE_O2_SLAT_SHIFT 8
67 #define CPC_BRIDGE_O2_2LAT_PRIM_ASYNC 2
68
69 /* PCI interrupt acknowledge & special cycle */
70 #define CPC_INTR_ACK 0xfed00000
71
72 #define CPC_PMM0_LOCAL 0xff400000
73 #define CPC_PMM0_MASK_ATTR 0xff400004
74 #define CPC_PMM0_PCI_LOW 0xff400008
75 #define CPC_PMM0_PCI_HIGH 0xff40000c
76 #define CPC_PMM1_LOCAL 0xff400010
77 #define CPC_PMM1_MASK_ATTR 0xff400014
78 #define CPC_PMM1_PCI_LOW 0xff400018
79 #define CPC_PMM1_PCI_HIGH 0xff40001c
80 #define CPC_PMM2_LOCAL 0xff400020
81 #define CPC_PMM2_MASK_ATTR 0xff400024
82 #define CPC_PMM2_PCI_LOW 0xff400028
83 #define CPC_PMM2_PCI_HIGH 0xff40002c
84 #define CPC_PTM1_LOCAL 0xff400030
85 #define CPC_PTM1_MEMSIZE 0xff400034
86 #define CPC_PTM2_LOCAL 0xff400038
87 #define CPC_PTM2_MEMSIZE 0xff40003c
88
89 /* serial ports */
90 #define CPC_COM0 0xff600300ULL
91 #define CPC_COM1 0xff600400ULL
92 #define CPC_COM_SPEED(bus) ((bus) / (2 * 4))
93
94 /* processor interface registers */
95 #define CPC_PIF_CFGADR 0xff500000
96 #define CPC_PIF_CFG_PRIFOPT1 0x00
97 #define CPC_PIF_CFG_ERRDET1 0x04
98 #define CPC_PIF_CFG_ERREN1 0x08
99 #define CPC_PIF_CFG_CPUERAD 0x0c
100 #define CPC_PIF_CFG_CPUERAT 0x10
101 #define CPC_PIF_CFG_PLBMIFOPT 0x18
102 #define CPC_PIF_CFG_PLBMTLSA1 0x20
103 #define CPC_PIF_CFG_PLBMTLEA1 0x24
104 #define CPC_PIF_CFG_PLBMTLSA2 0x28
105 #define CPC_PIF_CFG_PLBMTLEA2 0x2c
106 #define CPC_PIF_CFG_PLBMTLSA3 0x30
107 #define CPC_PIF_CFG_PLBMTLEA3 0x34
108 #define CPC_PIF_CFG_PLBSNSSA0 0x38
109 #define CPC_PIF_CFG_PLBSNSEA0 0x3c
110 #define CPC_PIF_CFG_BESR 0x40
111 #define CPC_PIF_CFG_BESRSET 0x44
112 #define CPC_PIF_CFG_BEAR 0x4c
113 #define CPC_PIF_CFG_PLBSWRINT 0x80
114 #define CPC_PIF_CFGDATA 0xff500004
115
116 /* interrupt controller */
117 #define CPC_UIC_BASE 0xff500880
118 #define CPC_UIC_SIZE 0x00000024
119 #define CPC_UIC_SR 0x00000000 /* UIC status (read/clear) */
120 #define CPC_UIC_SRS 0x00000004 /* UIC status (set) */
121 #define CPC_UIC_ER 0x00000008 /* UIC enable */
122 #define CPC_UIC_CR 0x0000000c /* UIC critical */
123 #define CPC_UIC_PR 0x00000010 /* UIC polarity 0=low, 1=high*/
124 #define CPC_UIC_TR 0x00000014 /* UIC trigger 0=level; 1=edge */
125 #define CPC_UIC_MSR 0x00000018 /* UIC masked status */
126 #define CPC_UIC_VR 0x0000001c /* UIC vector */
127 #define CPC_UIC_VCR 0x00000020 /* UIC vector configuration */
128 #define CPC_UIC_CVR_PRI 0x00000001 /* 0=intr31 high, 1=intr0 high */
129 /*
130 * if intr0 high then interrupt vector at (vcr&~3) + N*512
131 * if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512
132 */
133
134 /* UIC interrupt bits. Note, MSB is bit 0 */
135 /* Internal */
136 #define CPC_IB_ECC 0
137 #define CPC_IB_PCI_WR_RANGE 1
138 #define CPC_IB_PCI_WR_CMD 2
139 #define CPC_IB_UART_0 3
140 #define CPC_IB_UART_1 4
141 #define CPC_IB_IIC_0 5
142 #define CPC_IB_IIC_1 6
143 /* 6-16 GPT compare&capture */
144 /* 20-31 external */
145 #define CPC_IB_EXT0 20
146 #define CPC_IB_EXT1 21
147 #define CPC_IB_EXT2 22
148 #define CPC_IB_EXT3 23
149 #define CPC_IB_EXT4 24
150 #define CPC_IB_EXT5 25
151 #define CPC_IB_EXT6 26
152 #define CPC_IB_EXT7 27
153 #define CPC_IB_EXT8 28
154 #define CPC_IB_EXT9 29
155 #define CPC_IB_EXT10 30
156 #define CPC_IB_EXT11 31
157
158 #define CPC_INTR_MASK(irq) (0x80000000 >> (irq))
159
160
161 /* IIC */
162 #define CPC_IIC0 0xff620000
163 #define CPC_IIC1 0xff630000
164 #define CPC_IIC_SIZE 0x00000014
165 /* offsets from base */
166 #define CPC_IIC_MDBUF 0x00000000
167 #define CPC_IIC_SDBUF 0x00000002
168 #define CPC_IIC_LMADR 0x00000004
169 #define CPC_IIC_HNADR 0x00000005
170 #define CPC_IIC_CNTL 0x00000006
171 #define CPC_IIC_MDCNTL 0x00000007
172 #define CPC_IIC_STS 0x00000008
173 #define CPC_IIC_EXTSTS 0x00000009
174 #define CPC_IIC_LSADR 0x0000000a
175 #define CPC_IIC_HSADR 0x0000000b
176 #define CPC_IIC_CLKDIV 0x0000000c
177 #define CPC_IIC_INTRMSK 0x0000000d
178 #define CPC_IIC_FRCNT 0x0000000e
179 #define CPC_IIC_TCNTLSS 0x0000000f
180 #define CPC_IIC_DIRECTCNTL 0x00000010
181
182 /* timer */
183 #define CPC_TIMER 0xff650000
184 #define CPC_GPTTBC 0x00000000
185
186 #endif /* CPC700REG_H */

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