/[gxemul]/trunk/src/include/cop0.h
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Contents of /trunk/src/include/cop0.h

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Revision 34 - (show annotations)
Mon Oct 8 16:21:17 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 8987 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1480 2007/02/19 01:34:42 debug Exp $
20061029	Changing usleep(1) calls in the debugger to usleep(10000)
20061107	Adding a new disk image option (-d o...) which sets the ISO9660
		filesystem base offset; also making some other hacks to allow
		NetBSD/dreamcast and homebrew demos/games to boot directly
		from a filesystem image.
		Moving Dreamcast-specific stuff in the documentation to its
		own page (dreamcast.html).
		Adding a border to the Dreamcast PVR framebuffer.
20061108	Adding a -T command line option (again?), for halting the
		emulator on unimplemented memory accesses.
20061109	Continuing on various SH4 and Dreamcast related things.
		The emulator should now halt on more unimplemented device
		accesses, instead of just printing a warning, forcing me to
		actually implement missing stuff :)
20061111	Continuing on SH4 and Dreamcast stuff.
		Adding a bogus Landisk (SH4) machine mode.
20061112	Implementing some parts of the Dreamcast GDROM device. With
		some ugly hacks, NetBSD can (barely) mount an ISO image.
20061113	NetBSD/dreamcast now starts booting from the Live CD image,
		but crashes randomly quite early on in the boot process.
20061122	Beginning on a skeleton interrupt.h and interrupt.c for the
		new interrupt subsystem.
20061124	Continuing on the new interrupt system; taking the first steps
		to attempt to connect CPUs (SuperH and MIPS) and devices
		(dev_cons and SH4 timer interrupts) to it. Many things will
		probably break from now on.
20061125	Converting dev_ns16550, dev_8253 to the new interrupt system.
		Attempting to begin to convert the ISA bus.
20061130	Incorporating a patch from Brian Foley for the configure
		script, which checks for X11 libs in /usr/X11R6/lib64 (which
		is used on some Linux systems).
20061227	Adding a note in the man page about booting from Dreamcast
		CDROM images (i.e. that no external kernel is needed).
20061229	Continuing on the interrupt system rewrite: beginning to
		convert more devices, adding abort() calls for legacy interrupt
		system calls so that everything now _has_ to be rewritten!
		Almost all machine modes are now completely broken.
20061230	More progress on removing old interrupt code, mostly related
		to the ISA bus + devices, the LCA bus (on AlphaBook1), and
		the Footbridge bus (for CATS). And some minor PCI stuff.
		Connecting the ARM cpu to the new interrupt system.
		The CATS, NetWinder, and QEMU_MIPS machine modes now work with
		the new interrupt system :)
20061231	Connecting PowerPC CPUs to the new interrupt system.
		Making PReP machines (IBM 6050) work again.
		Beginning to convert the GT PCI controller (for e.g. Malta
		and Cobalt emulation). Some things work, but not everything.
		Updating Copyright notices for 2007.
20070101	Converting dev_kn02 from legacy style to devinit; the 3max
		machine mode now works with the new interrupt system :-]
20070105	Beginning to convert the SGI O2 machine to the new interrupt
		system; finally converting O2 (IP32) devices to devinit, etc.
20070106	Continuing on the interrupt system redesign/rewrite; KN01
		(PMAX), KN230, and Dreamcast ASIC interrupts should work again,
		moving out stuff from machine.h and devices.h into the
		corresponding devices, beginning the rewrite of i80321
		interrupts, etc.
20070107	Beginning on the rewrite of Eagle interrupt stuff (PReP, etc).
20070117	Beginning the rewrite of Algor (V3) interrupts (finally
		changing dev_v3 into devinit style).
20070118	Removing the "bus" registry concept from machine.h, because
		it was practically meaningless.
		Continuing on the rewrite of Algor V3 ISA interrupts.
20070121	More work on Algor interrupts; they are now working again,
		well enough to run NetBSD/algor. :-)
20070122	Converting VR41xx (HPCmips) interrupts. NetBSD/hpcmips
		can be installed using the new interrupt system :-)
20070123	Making the testmips mode work with the new interrupt system.
20070127	Beginning to convert DEC5800 devices to devinit, and to the
		new interrupt system.
		Converting Playstation 2 devices to devinit, and converting
		the interrupt system. Also fixing a severe bug: the interrupt
		mask register on Playstation 2 is bitwise _toggled_ on writes.
20070128	Removing the dummy NetGear machine mode and the 8250 device
		(which was only used by the NetGear machine).
		Beginning to convert the MacPPC GC (Grand Central) interrupt
		controller to the new interrupt system.
		Converting Jazz interrupts (PICA61 etc.) to the new interrupt
		system. NetBSD/arc can be installed again :-)
		Fixing the JAZZ timer (hardcoding it at 100 Hz, works with
		NetBSD and it is better than a completely dummy timer as it
		was before).
		Converting dev_mp to the new interrupt system, although I
		haven't had time to actually test it yet.
		Completely removing src/machines/interrupts.c, cpu_interrupt
		and cpu_interrupt_ack in src/cpu.c, and
		src/include/machine_interrupts.h! Adding fatal error messages
		+ abort() in the few places that are left to fix.
		Converting dev_z8530 to the new interrupt system.
		FINALLY removing the md_int struct completely from the
		machine struct.
		SH4 fixes (adding a PADDR invalidation in the ITLB replacement
		code in memory_sh.c); the NetBSD/dreamcast LiveCD now runs
		all the way to the login prompt, and can be interacted with :-)
		Converting the CPC700 controller (PCI and interrupt controller
		for PM/PPC) to the new interrupt system.
20070129	Fixing MACE ISA interrupts (SGI IP32 emulation). Both NetBSD/
		sgimips' and OpenBSD/sgi's ramdisk kernels can now be
		interacted with again.
20070130	Moving out the MIPS multi_lw and _sw instruction combinations
		so that they are auto-generated at compile time instead.
20070131	Adding detection of amd64/x86_64 hosts in the configure script,
		for doing initial experiments (again :-) with native code
		generation.
		Adding a -k command line option to set the size of the dyntrans
		cache, and a -B command line option to disable native code
		generation, even if GXemul was compiled with support for
		native code generation for the specific host CPU architecture.
20070201	Experimenting with a skeleton for native code generation.
		Changing the default behaviour, so that native code generation
		is now disabled by default, and has to be enabled by using
		-b on the command line.
20070202	Continuing the native code generation experiments.
		Making PCI interrupts work for Footbridge again.
20070203	More native code generation experiments.
		Removing most of the native code generation experimental code,
		it does not make sense to include any quick hacks like this.
		Minor cleanup/removal of some more legacy MIPS interrupt code.
20070204	Making i80321 interrupts work again (for NetBSD/evbarm etc.),
		and fixing the timer at 100 Hz.
20070206	Experimenting with removing the wdc interrupt slowness hack.
20070207	Lowering the number of dyntrans TLB entries for MIPS from
		192 to 128, resulting in a minor speed improvement.
		Minor optimization to the code invalidation routine in
		cpu_dyntrans.c.
20070208	Increasing (experimentally) the nr of dyntrans instructions per
		loop from 60 to 120.
20070210	Commenting out (experimentally) the dyntrans_device_danger
		detection in memory_rw.c.
		Changing the testmips and baremips machines to use a revision 2
		MIPS64 CPU by default, instead of revision 1.
		Removing the dummy i960, IA64, x86, AVR32, and HP PA-RISC
		files, the PC bios emulation, and the Olivetti M700 (ARC) and
		db64360 emulation modes.
20070211	Adding an "mp" demo to the demos directory, which tests the
		SMP functionality of the testmips machine.
		Fixing PReP interrupts some more. NetBSD/prep now boots again.
20070216	Adding a "nop workaround" for booting Mach/PMAX to the
		documentation; thanks to Artur Bujdoso for the values.
		Converting more of the MacPPC interrupt stuff to the new
		system.
		Beginning to convert BeBox interrupts to the new system.
		PPC603e should NOT have the PPC_NO_DEC flag! Removing it.
		Correcting BeBox clock speed (it was set to 100 in the NetBSD
		bootinfo block, but should be 33000000/4), allowing NetBSD
		to start without using the (incorrect) PPC_NO_DEC hack.
20070217	Implementing (slow) AltiVec vector loads and stores, allowing
		NetBSD/macppc to finally boot using the GENERIC kernel :-)
		Updating the documentation with install instructions for
		NetBSD/macppc.
20070218-19	Regression testing for the release.

==============  RELEASE 0.4.4  ==============
1 #ifndef COP0_H
2 #define COP0_H
3
4 /*
5 * Copyright (C) 2003-2007 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cop0.h,v 1.13 2006/12/30 13:31:00 debug Exp $
32 *
33 * Misc. definitions for coprocessor 0.
34 */
35
36
37 /* TODO: Coproc registers are actually CPU dependent, so an R4000
38 has other bits/registers than an R3000...
39 TODO 2: CPUs like the R10000 are probably even a bit more different. */
40
41 /* Coprocessor 0's registers' names: (max 8 characters long) */
42 #define COP0_NAMES { \
43 "index", "random", "entrylo0", "entrylo1", \
44 "context", "pagemask", "wired", "reserv7", \
45 "badvaddr", "count", "entryhi", "compare", \
46 "status", "cause", "epc", "prid", \
47 "config", "lladdr", "watchlo", "watchhi", \
48 "xcontext", "reserv21", "reserv22", "debug", \
49 "depc", "perfcnt", "errctl", "cacheerr", \
50 "tagdatlo", "tagdathi", "errorepc", "desave" }
51
52 #define COP0_INDEX 0
53 #define INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */
54 #define INDEX_MASK 0x3f
55 #define R2K3K_INDEX_P 0x80000000UL
56 #define R2K3K_INDEX_MASK 0x3f00
57 #define R2K3K_INDEX_SHIFT 8
58 #define COP0_RANDOM 1
59 #define RANDOM_MASK 0x3f
60 #define R2K3K_RANDOM_MASK 0x3f00
61 #define R2K3K_RANDOM_SHIFT 8
62 #define COP0_ENTRYLO0 2
63 #define COP0_ENTRYLO1 3
64 /* R4000 ENTRYLO: */
65 #define ENTRYLO_PFN_MASK 0x3fffffc0
66 #define ENTRYLO_PFN_SHIFT 6
67 #define ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */
68 #define ENTRYLO_C_SHIFT 3
69 #define ENTRYLO_D 0x04 /* Dirty bit */
70 #define ENTRYLO_V 0x02 /* Valid bit */
71 #define ENTRYLO_G 0x01 /* Global bit */
72 /* R2000/R3000 ENTRYLO: */
73 #define R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL
74 #define R2K3K_ENTRYLO_PFN_SHIFT 12
75 #define R2K3K_ENTRYLO_N 0x800
76 #define R2K3K_ENTRYLO_D 0x400
77 #define R2K3K_ENTRYLO_V 0x200
78 #define R2K3K_ENTRYLO_G 0x100
79 #define COP0_CONTEXT 4
80 #define CONTEXT_BADVPN2_MASK 0x007ffff0
81 #define CONTEXT_BADVPN2_MASK_R4100 0x01fffff0
82 #define CONTEXT_BADVPN2_SHIFT 4
83 #define R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc
84 #define R2K3K_CONTEXT_BADVPN_SHIFT 2
85 #define COP0_PAGEMASK 5
86 #define PAGEMASK_MASK 0x01ffe000
87 #define PAGEMASK_SHIFT 13
88 #define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */
89 /* how about others? */
90 #define PAGEMASK_SHIFT_R4100 11
91 #define COP0_WIRED 6
92 #define COP0_RESERV7 7
93 #define COP0_BADVADDR 8
94 #define COP0_COUNT 9
95 #define COP0_ENTRYHI 10
96 /* R4000 ENTRYHI: */
97 #define ENTRYHI_R_MASK 0xc000000000000000ULL
98 #define ENTRYHI_R_XKPHYS 0x8000000000000000ULL
99 #define ENTRYHI_R_SHIFT 62
100 #define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL
101 #define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL
102 #define ENTRYHI_VPN2_SHIFT 13
103 #define ENTRYHI_ASID 0xff
104 #define TLB_G (1 << 12)
105 /* R2000/R3000 ENTRYHI: */
106 #define R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL
107 #define R2K3K_ENTRYHI_VPN_SHIFT 12
108 #define R2K3K_ENTRYHI_ASID_MASK 0xfc0
109 #define R2K3K_ENTRYHI_ASID_SHIFT 6
110 #define COP0_COMPARE 11
111 #define COP0_STATUS 12
112 #define STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */
113 #define STATUS_CU_SHIFT 28
114 #define STATUS_RP 0x08000000 /* reduced power */
115 #define STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */
116 #define STATUS_RE 0x02000000 /* reverse endian bit */
117 #define STATUS_BEV 0x00400000 /* boot exception vectors (?) */
118 /* STATUS_DS: TODO */
119 #define STATUS_IM_MASK 0xff00
120 #define STATUS_IM_SHIFT 8
121 #define STATUS_KX 0x80
122 #define STATUS_SX 0x40
123 #define STATUS_UX 0x20
124 #define STATUS_KSU_MASK 0x18
125 #define STATUS_KSU_SHIFT 3
126 #define STATUS_ERL 0x04
127 #define STATUS_EXL 0x02
128 #define STATUS_IE 0x01
129 #define R5900_STATUS_EDI 0x20000 /* EI/DI instruction enable */
130 #define R5900_STATUS_EIE 0x10000 /* Enable Interrupt Enable */
131 #define COP0_CAUSE 13
132 #define CAUSE_BD 0x80000000UL /* branch delay flag */
133 #define CAUSE_CE_MASK 0x30000000 /* which coprocessor */
134 #define CAUSE_CE_SHIFT 28
135 #define CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */
136 #define CAUSE_WP 0x00400000UL /* watch exception ... */
137 #define CAUSE_IP_MASK 0xff00 /* interrupt pending */
138 #define CAUSE_IP_SHIFT 8
139 #define CAUSE_EXCCODE_MASK 0x7c /* exception code */
140 #define R2K3K_CAUSE_EXCCODE_MASK 0x3c
141 #define CAUSE_EXCCODE_SHIFT 2
142 #define COP0_EPC 14
143 #define COP0_PRID 15
144 #define COP0_CONFIG 16
145 #define COP0_LLADDR 17
146 #define COP0_WATCHLO 18
147 #define COP0_WATCHHI 19
148 #define COP0_XCONTEXT 20
149 #define XCONTEXT_R_MASK 0x180000000ULL
150 #define XCONTEXT_R_SHIFT 31
151 #define XCONTEXT_BADVPN2_MASK 0x7ffffff0
152 #define XCONTEXT_BADVPN2_SHIFT 4
153 #define COP0_FRAMEMASK 21 /* R10000 */
154 #define COP0_RESERV22 22
155 #define COP0_DEBUG 23
156 #define COP0_DEPC 24
157 #define COP0_PERFCNT 25
158 #define COP0_ERRCTL 26
159 #define COP0_CACHEERR 27
160 #define COP0_TAGDATA_LO 28
161 #define COP0_TAGDATA_HI 29
162 #define COP0_ERROREPC 30
163 #define COP0_DESAVE 31
164
165 /* Coprocessor 1's registers: */
166 #define COP1_REVISION 0
167 #define COP1_REVISION_MIPS3D 0x80000 /* MIPS3D support */
168 #define COP1_REVISION_PS 0x40000 /* Paired-single support */
169 #define COP1_REVISION_DOUBLE 0x20000 /* double precision support */
170 #define COP1_REVISION_SINGLE 0x10000 /* single precision support */
171 #define COP1_CONTROLSTATUS 31
172
173 /* CP0's STATUS KSU values: */
174 #define KSU_KERNEL 0
175 #define KSU_SUPERVISOR 1
176 #define KSU_USER 2
177
178 #define EXCEPTION_NAMES { \
179 "INT", "MOD", "TLBL", "TLBS", "ADEL", "ADES", "IBE", "DBE", \
180 "SYS", "BP", "RI", "CPU", "OV", "TR", "VCEI", "FPE", \
181 "16?", "17?", "C2E", "19?", "20?", "21?", "MDMX", "WATCH", \
182 "MCHECK", "25?", "26?", "27?", "28?", "29?", "CACHEERR", "VCED" }
183
184 /* CP0's CAUSE exception codes: */
185 #define EXCEPTION_INT 0 /* Interrupt */
186 #define EXCEPTION_MOD 1 /* TLB modification exception */
187 #define EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */
188 #define EXCEPTION_TLBS 3 /* TLB exception (store) */
189 #define EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */
190 #define EXCEPTION_ADES 5 /* Address Error Exception (store) */
191 #define EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */
192 #define EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */
193 #define EXCEPTION_SYS 8 /* Syscall */
194 #define EXCEPTION_BP 9 /* Breakpoint */
195 #define EXCEPTION_RI 10 /* Reserved instruction */
196 #define EXCEPTION_CPU 11 /* CoProcessor Unusable */
197 #define EXCEPTION_OV 12 /* Arithmetic Overflow */
198 #define EXCEPTION_TR 13 /* Trap exception */
199 #define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */
200 #define EXCEPTION_FPE 15 /* Floating point exception */
201 /* 16..17: Available for "implementation dependent use" */
202 #define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */
203 /* 19..21: Reserved */
204 #define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */
205 #define EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */
206 #define EXCEPTION_MCHECK 24 /* MIPS64 Machine Check */
207 /* 25..29: Reserved */
208 #define EXCEPTION_CACHEERR 30 /* MIPS64 Cache Error */
209 #define EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */
210
211
212 #endif /* COP0_H */
213
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