/[gxemul]/trunk/src/include/cop0.h
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Contents of /trunk/src/include/cop0.h

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Revision 18 - (show annotations)
Mon Oct 8 16:19:11 2007 UTC (16 years, 6 months ago) by dpavlin
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File size: 8825 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1004 2005/10/27 14:01:10 debug Exp $
20051011        Passing -A as the default boot arg for CATS (works fine with
                OpenBSD/cats).
20051012	Fixing the VGA cursor offset bug, and speeding up framebuffer
		redraws if character cells contain the same thing as during
		the last redraw.
20051013	Adding a slow strd ARM instruction hack.
20051017	Minor updates: Adding a dummy i80321 Verde controller (for
		XScale emulation), fixing the disassembly of the ARM "ldrd"
		instruction, adding "support" for less-than-4KB pages for ARM
		(by not adding them to translation tables).
20051020	Continuing on some HPCarm stuff. A NetBSD/hpcarm kernel prints
		some boot messages on an emulated Jornada 720.
		Making dev_ram work better with dyntrans (speeds up some things
		quite a bit).
20051021	Automatically generating some of the most common ARM load/store
		multiple instructions.
20051022	Better statistics gathering for the ARM load/store multiple.
		Various other dyntrans and device updates.
20051023	Various minor updates.
20051024	Continuing; minor device and dyntrans fine-tuning. Adding the
		first "reasonable" instruction combination hacks for ARM (the
		cores of NetBSD/cats' memset and memcpy).
20051025	Fixing a dyntrans-related bug in dev_vga. Also changing the
		dyntrans low/high access notification to only be updated on
		writes, not reads. Hopefully it will be enough. (dev_vga in
		charcell mode now seems to work correctly with both reads and
		writes.)
		Experimenting with gathering dyntrans statistics (which parts
		of emulated RAM that are actually executed), and adding
		instruction combination hacks for cache cleaning and a part of
		NetBSD's scanc() function.
20051026	Adding a bitmap for ARM emulation which indicates if a page is
		(specifically) user accessible; loads and stores with the t-
		flag set can now use the translation arrays, which results in
		a measurable speedup.
20051027	Dyntrans updates; adding an extra bitmap array for 32-bit
		emulation modes, speeding up the check whether a physical page
		has any code translations or not (O(n) -> O(1)). Doing a
		similar reduction of O(n) to O(1) by avoiding the scan through
		the translation entries on a translation update (32-bit mode
		only).
		Various other minor hacks.
20051029	Quick release, without any testing at all.

==============  RELEASE 0.3.6.2  ==============
1 #ifndef COP0_H
2 #define COP0_H
3
4 /*
5 * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: cop0.h,v 1.8 2005/10/26 14:37:06 debug Exp $
32 *
33 * Misc. definitions for coprocessor 0.
34 */
35
36
37 /* TODO: Coproc registers are actually CPU dependent, so an R4000
38 has other bits/registers than an R3000...
39 TODO 2: CPUs like the R10000 are probably even a bit more different. */
40
41 /* Coprocessor 0's registers' names: (max 8 characters long) */
42 #define COP0_NAMES { \
43 "index", "random", "entrylo0", "entrylo1", \
44 "context", "pagemask", "wired", "reserv7", \
45 "badvaddr", "count", "entryhi", "compare", \
46 "status", "cause", "epc", "prid", \
47 "config", "lladdr", "watchlo", "watchhi", \
48 "xcontext", "reserv21", "reserv22", "debug", \
49 "depc", "perfcnt", "errctl", "cacheerr", \
50 "tagdatlo", "tagdathi", "errorepc", "desave" }
51
52 #define COP0_INDEX 0
53 #define INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */
54 #define INDEX_MASK 0x3f
55 #define R2K3K_INDEX_P 0x80000000UL
56 #define R2K3K_INDEX_MASK 0x3f00
57 #define R2K3K_INDEX_SHIFT 8
58 #define COP0_RANDOM 1
59 #define RANDOM_MASK 0x3f
60 #define R2K3K_RANDOM_MASK 0x3f00
61 #define R2K3K_RANDOM_SHIFT 8
62 #define COP0_ENTRYLO0 2
63 #define COP0_ENTRYLO1 3
64 /* R4000 ENTRYLO: */
65 #define ENTRYLO_PFN_MASK 0x3fffffc0
66 #define ENTRYLO_PFN_SHIFT 6
67 #define ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */
68 #define ENTRYLO_C_SHIFT 3
69 #define ENTRYLO_D 0x04 /* Dirty bit */
70 #define ENTRYLO_V 0x02 /* Valid bit */
71 #define ENTRYLO_G 0x01 /* Global bit */
72 /* R2000/R3000 ENTRYLO: */
73 #define R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL
74 #define R2K3K_ENTRYLO_PFN_SHIFT 12
75 #define R2K3K_ENTRYLO_N 0x800
76 #define R2K3K_ENTRYLO_D 0x400
77 #define R2K3K_ENTRYLO_V 0x200
78 #define R2K3K_ENTRYLO_G 0x100
79 #define COP0_CONTEXT 4
80 #define CONTEXT_BADVPN2_MASK 0x007ffff0
81 #define CONTEXT_BADVPN2_MASK_R4100 0x01fffff0
82 #define CONTEXT_BADVPN2_SHIFT 4
83 #define R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc
84 #define R2K3K_CONTEXT_BADVPN_SHIFT 2
85 #define COP0_PAGEMASK 5
86 #define PAGEMASK_MASK 0x01ffe000
87 #define PAGEMASK_SHIFT 13
88 #define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */
89 /* how about others? */
90 #define PAGEMASK_SHIFT_R4100 11
91 #define COP0_WIRED 6
92 #define COP0_RESERV7 7
93 #define COP0_BADVADDR 8
94 #define COP0_COUNT 9
95 #define COP0_ENTRYHI 10
96 /* R4000 ENTRYHI: */
97 #define ENTRYHI_R_MASK 0xc000000000000000ULL
98 #define ENTRYHI_R_SHIFT 62
99 #define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL
100 #define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL
101 #define ENTRYHI_VPN2_SHIFT 13
102 #define ENTRYHI_ASID 0xff
103 #define TLB_G (1 << 12)
104 /* R2000/R3000 ENTRYHI: */
105 #define R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL
106 #define R2K3K_ENTRYHI_VPN_SHIFT 12
107 #define R2K3K_ENTRYHI_ASID_MASK 0xfc0
108 #define R2K3K_ENTRYHI_ASID_SHIFT 6
109 #define COP0_COMPARE 11
110 #define COP0_STATUS 12
111 #define STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */
112 #define STATUS_CU_SHIFT 28
113 #define STATUS_RP 0x08000000 /* reduced power */
114 #define STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */
115 #define STATUS_RE 0x02000000 /* reverse endian bit */
116 #define STATUS_BEV 0x00400000 /* boot exception vectors (?) */
117 /* STATUS_DS: TODO */
118 #define STATUS_IM_MASK 0xff00
119 #define STATUS_IM_SHIFT 8
120 #define STATUS_KX 0x80
121 #define STATUS_SX 0x40
122 #define STATUS_UX 0x20
123 #define STATUS_KSU_MASK 0x18
124 #define STATUS_KSU_SHIFT 3
125 #define STATUS_ERL 0x04
126 #define STATUS_EXL 0x02
127 #define STATUS_IE 0x01
128 #define R5900_STATUS_EIE 0x10000
129 #define COP0_CAUSE 13
130 #define CAUSE_BD 0x80000000UL /* branch delay flag */
131 #define CAUSE_CE_MASK 0x30000000 /* which coprocessor */
132 #define CAUSE_CE_SHIFT 28
133 #define CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */
134 #define CAUSE_WP 0x00400000UL /* watch exception ... */
135 #define CAUSE_IP_MASK 0xff00 /* interrupt pending */
136 #define CAUSE_IP_SHIFT 8
137 #define CAUSE_EXCCODE_MASK 0x7c /* exception code */
138 #define R2K3K_CAUSE_EXCCODE_MASK 0x3c
139 #define CAUSE_EXCCODE_SHIFT 2
140 #define COP0_EPC 14
141 #define COP0_PRID 15
142 #define COP0_CONFIG 16
143 #define COP0_LLADDR 17
144 #define COP0_WATCHLO 18
145 #define COP0_WATCHHI 19
146 #define COP0_XCONTEXT 20
147 #define XCONTEXT_R_MASK 0x180000000ULL
148 #define XCONTEXT_R_SHIFT 31
149 #define XCONTEXT_BADVPN2_MASK 0x7ffffff0
150 #define XCONTEXT_BADVPN2_SHIFT 4
151 #define COP0_FRAMEMASK 21 /* R10000 */
152 #define COP0_RESERV22 22
153 #define COP0_DEBUG 23
154 #define COP0_DEPC 24
155 #define COP0_PERFCNT 25
156 #define COP0_ERRCTL 26
157 #define COP0_CACHEERR 27
158 #define COP0_TAGDATA_LO 28
159 #define COP0_TAGDATA_HI 29
160 #define COP0_ERROREPC 30
161 #define COP0_DESAVE 31
162
163 /* Coprocessor 1's registers: */
164 #define COP1_REVISION 0
165 #define COP1_REVISION_MIPS3D 0x80000 /* MIPS3D support */
166 #define COP1_REVISION_PS 0x40000 /* Paired-single support */
167 #define COP1_REVISION_DOUBLE 0x20000 /* double precision support */
168 #define COP1_REVISION_SINGLE 0x10000 /* single precision support */
169 #define COP1_CONTROLSTATUS 31
170
171 /* CP0's STATUS KSU values: */
172 #define KSU_KERNEL 0
173 #define KSU_SUPERVISOR 1
174 #define KSU_USER 2
175
176 #define EXCEPTION_NAMES { \
177 "INT", "MOD", "TLBL", "TLBS", "ADEL", "ADES", "IBE", "DBE", \
178 "SYS", "BP", "RI", "CPU", "OV", "TR", "VCEI", "FPE", \
179 "16?", "17?", "C2E", "19?", "20?", "21?", "MDMX", "WATCH", \
180 "MCHECK", "25?", "26?", "27?", "28?", "29?", "CACHEERR", "VCED" }
181
182 /* CP0's CAUSE exception codes: */
183 #define EXCEPTION_INT 0 /* Interrupt */
184 #define EXCEPTION_MOD 1 /* TLB modification exception */
185 #define EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */
186 #define EXCEPTION_TLBS 3 /* TLB exception (store) */
187 #define EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */
188 #define EXCEPTION_ADES 5 /* Address Error Exception (store) */
189 #define EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */
190 #define EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */
191 #define EXCEPTION_SYS 8 /* Syscall */
192 #define EXCEPTION_BP 9 /* Breakpoint */
193 #define EXCEPTION_RI 10 /* Reserved instruction */
194 #define EXCEPTION_CPU 11 /* CoProcessor Unusable */
195 #define EXCEPTION_OV 12 /* Arithmetic Overflow */
196 #define EXCEPTION_TR 13 /* Trap exception */
197 #define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */
198 #define EXCEPTION_FPE 15 /* Floating point exception */
199 /* 16..17: Available for "implementation dependant use" */
200 #define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */
201 /* 19..21: Reserved */
202 #define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */
203 #define EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */
204 #define EXCEPTION_MCHECK 24 /* MIPS64 Machine Check */
205 /* 25..29: Reserved */
206 #define EXCEPTION_CACHEERR 30 /* MIPS64 Cache Error */
207 #define EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */
208
209
210 #endif /* COP0_H */
211
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