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#ifndef COP0_H |
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#define COP0_H |
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|
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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cop0.h,v 1.7 2005/09/18 19:54:16 debug Exp $ |
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* |
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* Misc. definitions for coprocessor 0. |
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*/ |
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|
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|
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/* TODO: Coproc registers are actually CPU dependant, so an R4000 |
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has other bits/registers than an R3000... |
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TODO 2: CPUs like the R10000 are probably even a bit more different. */ |
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|
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/* Coprocessor 0's registers' names: (max 8 characters long) */ |
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#define COP0_NAMES { \ |
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"index", "random", "entrylo0", "entrylo1", \ |
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"context", "pagemask", "wired", "reserv7", \ |
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"badvaddr", "count", "entryhi", "compare", \ |
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"status", "cause", "epc", "prid", \ |
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"config", "lladdr", "watchlo", "watchhi", \ |
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"xcontext", "reserv21", "reserv22", "debug", \ |
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"depc", "perfcnt", "errctl", "cacheerr", \ |
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"tagdatlo", "tagdathi", "errorepc", "desave" } |
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|
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#define COP0_INDEX 0 |
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#define INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */ |
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#define INDEX_MASK 0x3f |
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#define R2K3K_INDEX_P 0x80000000UL |
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#define R2K3K_INDEX_MASK 0x3f00 |
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#define R2K3K_INDEX_SHIFT 8 |
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#define COP0_RANDOM 1 |
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#define RANDOM_MASK 0x3f |
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#define R2K3K_RANDOM_MASK 0x3f00 |
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#define R2K3K_RANDOM_SHIFT 8 |
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#define COP0_ENTRYLO0 2 |
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#define COP0_ENTRYLO1 3 |
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/* R4000 ENTRYLO: */ |
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#define ENTRYLO_PFN_MASK 0x3fffffc0 |
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#define ENTRYLO_PFN_SHIFT 6 |
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#define ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */ |
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#define ENTRYLO_C_SHIFT 3 |
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#define ENTRYLO_D 0x04 /* Dirty bit */ |
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#define ENTRYLO_V 0x02 /* Valid bit */ |
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#define ENTRYLO_G 0x01 /* Global bit */ |
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/* R2000/R3000 ENTRYLO: */ |
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#define R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL |
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#define R2K3K_ENTRYLO_PFN_SHIFT 12 |
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#define R2K3K_ENTRYLO_N 0x800 |
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#define R2K3K_ENTRYLO_D 0x400 |
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#define R2K3K_ENTRYLO_V 0x200 |
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#define R2K3K_ENTRYLO_G 0x100 |
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#define COP0_CONTEXT 4 |
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#define CONTEXT_BADVPN2_MASK 0x007ffff0 |
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#define CONTEXT_BADVPN2_MASK_R4100 0x01fffff0 |
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#define CONTEXT_BADVPN2_SHIFT 4 |
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#define R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc |
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#define R2K3K_CONTEXT_BADVPN_SHIFT 2 |
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#define COP0_PAGEMASK 5 |
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#define PAGEMASK_MASK 0x01ffe000 |
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#define PAGEMASK_SHIFT 13 |
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#define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */ |
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/* how about others? */ |
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#define PAGEMASK_SHIFT_R4100 11 |
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#define COP0_WIRED 6 |
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#define COP0_RESERV7 7 |
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#define COP0_BADVADDR 8 |
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#define COP0_COUNT 9 |
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#define COP0_ENTRYHI 10 |
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/* R4000 ENTRYHI: */ |
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#define ENTRYHI_R_MASK 0xc000000000000000ULL |
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#define ENTRYHI_R_SHIFT 62 |
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#define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL |
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#define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL |
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#define ENTRYHI_VPN2_SHIFT 13 |
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#define ENTRYHI_ASID 0xff |
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#define TLB_G (1 << 12) |
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/* R2000/R3000 ENTRYHI: */ |
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#define R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL |
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#define R2K3K_ENTRYHI_VPN_SHIFT 12 |
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#define R2K3K_ENTRYHI_ASID_MASK 0xfc0 |
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#define R2K3K_ENTRYHI_ASID_SHIFT 6 |
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#define COP0_COMPARE 11 |
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#define COP0_STATUS 12 |
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#define STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */ |
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#define STATUS_CU_SHIFT 28 |
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#define STATUS_RP 0x08000000 /* reduced power */ |
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#define STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */ |
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#define STATUS_RE 0x02000000 /* reverse endian bit */ |
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#define STATUS_BEV 0x00400000 /* boot exception vectors (?) */ |
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/* STATUS_DS: TODO */ |
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#define STATUS_IM_MASK 0xff00 |
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#define STATUS_IM_SHIFT 8 |
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#define STATUS_KX 0x80 |
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#define STATUS_SX 0x40 |
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#define STATUS_UX 0x20 |
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#define STATUS_KSU_MASK 0x18 |
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#define STATUS_KSU_SHIFT 3 |
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#define STATUS_ERL 0x04 |
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#define STATUS_EXL 0x02 |
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#define STATUS_IE 0x01 |
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#define R5900_STATUS_EIE 0x10000 |
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#define COP0_CAUSE 13 |
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#define CAUSE_BD 0x80000000UL /* branch delay flag */ |
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#define CAUSE_CE_MASK 0x30000000 /* which coprocessor */ |
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#define CAUSE_CE_SHIFT 28 |
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#define CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */ |
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#define CAUSE_WP 0x00400000UL /* watch exception ... */ |
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#define CAUSE_IP_MASK 0xff00 /* interrupt pending */ |
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#define CAUSE_IP_SHIFT 8 |
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#define CAUSE_EXCCODE_MASK 0x7c /* exception code */ |
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#define R2K3K_CAUSE_EXCCODE_MASK 0x3c |
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#define CAUSE_EXCCODE_SHIFT 2 |
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#define COP0_EPC 14 |
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#define COP0_PRID 15 |
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#define COP0_CONFIG 16 |
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#define COP0_LLADDR 17 |
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#define COP0_WATCHLO 18 |
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#define COP0_WATCHHI 19 |
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#define COP0_XCONTEXT 20 |
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#define XCONTEXT_R_MASK 0x180000000ULL |
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#define XCONTEXT_R_SHIFT 31 |
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#define XCONTEXT_BADVPN2_MASK 0x7ffffff0 |
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#define XCONTEXT_BADVPN2_SHIFT 4 |
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#define COP0_FRAMEMASK 21 /* R10000 */ |
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#define COP0_RESERV22 22 |
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#define COP0_DEBUG 23 |
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#define COP0_DEPC 24 |
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#define COP0_PERFCNT 25 |
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#define COP0_ERRCTL 26 |
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#define COP0_CACHEERR 27 |
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#define COP0_TAGDATA_LO 28 |
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#define COP0_TAGDATA_HI 29 |
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#define COP0_ERROREPC 30 |
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#define COP0_DESAVE 31 |
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|
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/* Coprocessor 1's registers: */ |
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#define COP1_REVISION 0 |
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#define COP1_REVISION_MIPS3D 0x80000 /* MIPS3D support */ |
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#define COP1_REVISION_PS 0x40000 /* Paired-single support */ |
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#define COP1_REVISION_DOUBLE 0x20000 /* double precision support */ |
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#define COP1_REVISION_SINGLE 0x10000 /* single precision support */ |
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#define COP1_CONTROLSTATUS 31 |
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|
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/* CP0's STATUS KSU values: */ |
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#define KSU_KERNEL 0 |
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#define KSU_SUPERVISOR 1 |
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#define KSU_USER 2 |
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|
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#define EXCEPTION_NAMES { \ |
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"INT", "MOD", "TLBL", "TLBS", "ADEL", "ADES", "IBE", "DBE", \ |
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"SYS", "BP", "RI", "CPU", "OV", "TR", "VCEI", "FPE", \ |
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"16?", "17?", "C2E", "19?", "20?", "21?", "MDMX", "WATCH", \ |
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"MCHECK", "25?", "26?", "27?", "28?", "29?", "CACHEERR", "VCED" } |
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/* CP0's CAUSE exception codes: */ |
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#define EXCEPTION_INT 0 /* Interrupt */ |
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#define EXCEPTION_MOD 1 /* TLB modification exception */ |
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#define EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */ |
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#define EXCEPTION_TLBS 3 /* TLB exception (store) */ |
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#define EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */ |
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#define EXCEPTION_ADES 5 /* Address Error Exception (store) */ |
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#define EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */ |
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#define EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */ |
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#define EXCEPTION_SYS 8 /* Syscall */ |
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#define EXCEPTION_BP 9 /* Breakpoint */ |
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#define EXCEPTION_RI 10 /* Reserved instruction */ |
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#define EXCEPTION_CPU 11 /* CoProcessor Unusable */ |
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#define EXCEPTION_OV 12 /* Arithmetic Overflow */ |
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#define EXCEPTION_TR 13 /* Trap exception */ |
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#define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */ |
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#define EXCEPTION_FPE 15 /* Floating point exception */ |
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/* 16..17: Available for "implementation dependant use" */ |
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#define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */ |
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/* 19..21: Reserved */ |
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#define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */ |
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#define EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */ |
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#define EXCEPTION_MCHECK 24 /* MIPS64 Machine Check */ |
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/* 25..29: Reserved */ |
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#define EXCEPTION_CACHEERR 30 /* MIPS64 Cache Error */ |
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#define EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */ |
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#endif /* COP0_H */ |
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