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#define COP0_H |
#define COP0_H |
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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cop0.h,v 1.6 2005/01/18 06:22:58 debug Exp $ |
* $Id: cop0.h,v 1.13 2006/12/30 13:31:00 debug Exp $ |
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* |
* |
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* Misc. definitions for coprocessor 0. |
* Misc. definitions for coprocessor 0. |
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*/ |
*/ |
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/* TODO: Coproc registers are actually CPU dependant, so an R4000 |
/* TODO: Coproc registers are actually CPU dependent, so an R4000 |
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has other bits/registers than an R3000... |
has other bits/registers than an R3000... |
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TODO 2: CPUs like the R10000 are probably even a bit more different. */ |
TODO 2: CPUs like the R10000 are probably even a bit more different. */ |
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#define COP0_PAGEMASK 5 |
#define COP0_PAGEMASK 5 |
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#define PAGEMASK_MASK 0x01ffe000 |
#define PAGEMASK_MASK 0x01ffe000 |
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#define PAGEMASK_SHIFT 13 |
#define PAGEMASK_SHIFT 13 |
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#define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, how about others? */ |
#define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */ |
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/* how about others? */ |
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#define PAGEMASK_SHIFT_R4100 11 |
#define PAGEMASK_SHIFT_R4100 11 |
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#define COP0_WIRED 6 |
#define COP0_WIRED 6 |
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#define COP0_RESERV7 7 |
#define COP0_RESERV7 7 |
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#define COP0_ENTRYHI 10 |
#define COP0_ENTRYHI 10 |
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/* R4000 ENTRYHI: */ |
/* R4000 ENTRYHI: */ |
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#define ENTRYHI_R_MASK 0xc000000000000000ULL |
#define ENTRYHI_R_MASK 0xc000000000000000ULL |
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#define ENTRYHI_R_XKPHYS 0x8000000000000000ULL |
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#define ENTRYHI_R_SHIFT 62 |
#define ENTRYHI_R_SHIFT 62 |
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#define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL |
#define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL |
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#define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL |
#define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL |
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#define STATUS_ERL 0x04 |
#define STATUS_ERL 0x04 |
127 |
#define STATUS_EXL 0x02 |
#define STATUS_EXL 0x02 |
128 |
#define STATUS_IE 0x01 |
#define STATUS_IE 0x01 |
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#define R5900_STATUS_EIE 0x10000 |
#define R5900_STATUS_EDI 0x20000 /* EI/DI instruction enable */ |
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#define R5900_STATUS_EIE 0x10000 /* Enable Interrupt Enable */ |
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#define COP0_CAUSE 13 |
#define COP0_CAUSE 13 |
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#define CAUSE_BD 0x80000000UL /* branch delay flag */ |
#define CAUSE_BD 0x80000000UL /* branch delay flag */ |
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#define CAUSE_CE_MASK 0x30000000 /* which coprocessor */ |
#define CAUSE_CE_MASK 0x30000000 /* which coprocessor */ |
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#define EXCEPTION_TR 13 /* Trap exception */ |
#define EXCEPTION_TR 13 /* Trap exception */ |
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#define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */ |
#define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */ |
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#define EXCEPTION_FPE 15 /* Floating point exception */ |
#define EXCEPTION_FPE 15 /* Floating point exception */ |
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/* 16..17: Available for "implementation dependant use" */ |
/* 16..17: Available for "implementation dependent use" */ |
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#define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */ |
#define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */ |
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/* 19..21: Reserved */ |
/* 19..21: Reserved */ |
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#define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */ |
#define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */ |