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Revision Log
++ trunk/HISTORY (local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816 Adding a framework for emulated/virtual timers (src/timer.c),
using only setitimer().
Rewriting the mc146818 to use the new timer framework.
20060817 Adding a call to gettimeofday() every now and then (once every
second, at the moment) to resynch the timer if it drifts.
Beginning to convert the ISA timer interrupt mechanism (8253
and 8259) to use the new timer framework.
Removing the -I command line option.
20060819 Adding the -I command line option again, with new semantics.
Working on Footbridge timer interrupts; NetBSD/NetWinder and
NetBSD/CATS now run at correct speed, but unfortunately with
HUGE delays during bootup.
20060821 Some minor m68k updates. Adding the first instruction: nop. :)
Minor Alpha emulation updates.
20060822 Adding a FreeBSD development specific YAMON environment
variable ("khz") (as suggested by Bruce M. Simpson).
Moving YAMON environment variable initialization from
machine_evbmips.c into promemul/yamon.c, and adding some more
variables.
Continuing on the LCA PCI bus controller (for Alpha machines).
20060823 Continuing on the timer stuff: experimenting with MIPS count/
compare interrupts connected to the timer framework.
20060825 Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
Minor updates to the LCA PCI controller.
20060827 Implementing a CHIP8 cpu mode, and a corresponding CHIP8
machine, for fun. Disassembly support for all instructions,
and most of the common instructions have been implemented: mvi,
mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828 Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
(more correct) RCA 180x cpu. (Disassembly for all 1802
instructions has been implemented, but no execution yet, and
no 1805 extended instructions.)
20060829 Minor Alpha emulation updates.
20060830 Beginning to experiment a little with PCI IDE for SGI O2.
Fixing the cursor key mappings for MobilePro 770 emulation.
Fixing the LK201 warning caused by recent NetBSD/pmax.
The MIPS R41xx standby, suspend, and hibernate instructions now
behave like the RM52xx/MIPS32/MIPS64 wait instruction.
Fixing dev_wdc so it calculates correct (64-bit) offsets before
giving them to diskimage_access().
20060831 Continuing on Alpha emulation (OSF1 PALcode).
20060901 Minor Alpha updates; beginning on virtual memory pagetables.
Removed the limit for max nr of devices (in preparation for
allowing devices' base addresses to be changed during runtime).
Adding a hack for MIPS [d]mfc0 select 0 (except the count
register), so that the coproc register is simply copied.
The MIPS suspend instruction now exits the emulator, instead
of being treated as a wait instruction (this causes NetBSD/
hpcmips to get correct 'halt' behavior).
The VR41xx RTC now returns correct time.
Connecting the VR41xx timer to the timer framework (fixed at
128 Hz, for now).
Continuing on SPARC emulation, adding more instructions:
restore, ba_xcc, ble. The rectangle drawing demo works :)
Removing the last traces of the old ENABLE_CACHE_EMULATION
MIPS stuff (not usable with dyntrans anyway).
20060902 Splitting up src/net.c into several smaller files in its own
subdirectory (src/net/).
20060903 Cleanup of the files in src/net/, to make them less ugly.
20060904 Continuing on the 'settings' subsystem.
Minor progress on the SPARC emulation mode.
20060905 Cleanup of various things, and connecting the settings
infrastructure to various subsystems (emul, machine, cpu, etc).
Changing the lk201 mouse update routine to not rely on any
emulated hardware framebuffer cursor coordinates, but instead
always do (semi-usable) relative movements.
20060906 Continuing on the lk201 mouse stuff. Mouse behaviour with
multiple framebuffers (which was working in Ultrix) is now
semi-broken (but it still works, in a way).
Moving the documentation about networking into its own file
(networking.html), and refreshing it a bit. Adding an example
of how to use ethernet frame direct-access (udp_snoop).
20060907 Continuing on the settings infrastructure.
20060908 Minor updates to SH emulation: for 32-bit emulation: delay
slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
ice, for now.
20060909-10 Implementing some more 32-bit SH instructions. Removing the
64-bit mode completely. Enough has now been implemented to run
the rectangle drawing demo. :-)
20060912 Adding more SH instructions.
20060916 Continuing on SH emulation (some more instructions: div0u,
div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
Continuing on the settings subsystem (beginning on reading/
writing settings, removing bugs, and connecting more cpus to
the framework).
20060919 More work on SH emulation; adding an ldc banked instruction,
and attaching a 640x480 framebuffer to the Dreamcast machine
mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
and then panics).
20060920 Continuing on the settings subsystem.
20060921 Fixing the Footbridge timer stuff so that NetBSD/cats and
NetBSD/netwinder boot up without the delays.
20060922 Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
'wait' support disabled, NetBSD/malta and Linux/malta run at
correct speed.
20060923 Connecting dev_gt to the timer framework, so that NetBSD/cobalt
runs at correct speed.
Moving SH4-specific memory mapped registers into its own
device (dev_sh4.c).
Running with -N now prints "idling" instead of bogus nr of
instrs/second (which isn't valid anyway) while idling.
20060924 Algor emulation should now run at correct speed.
Adding disassembly support for some MIPS64 revision 2
instructions: ext, dext, dextm, dextu.
20060926 The timer framework now works also when the MIPS wait
instruction is used.
20060928 Re-implementing checks for coprocessor availability for MIPS
cop0 instructions. (Thanks to Carl van Schaik for noticing the
lack of cop0 availability checks.)
20060929 Implementing an instruction combination hack which treats
NetBSD/pmax' idle loop as a wait-like instruction.
20060930 The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
causing TLB lookups to sometimes succeed when they should have
failed. (A big thank you to Juli Mallett for noticing the
problem.)
Adding disassembly support for more MIPS64 revision 2 opcodes
(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
implementing seb, seh, dsbh, dshd, and wsbh.
Implementing an instruction combination hack for Linux/pmax'
idle loop, similar to the NetBSD/pmax case.
20061001 Changing the NetBSD/sgimips install instructions to extract
files from an iso image, instead of downloading them via ftp.
20061002 More-than-31-bit userland addresses in memory_mips_v2p.c were
not actually working; applying a fix from Carl van Schaik to
enable them to work + making some other updates (adding kuseg
support).
Fixing hpcmips (vr41xx) timer initialization.
Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
loop. Seems to work both for R3000 and non-R3000.
20061003 Continuing a little on SH emulation (adding more control
registers; mini-cleanup of memory_sh.c).
20061004 Beginning on a dev_rtc, a clock/timer device for the test
machines; also adding a demo, and some documentation.
Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
sign-extended), and adding the addc and ldtlb instructions.
20061005 Contining on SH emulation: virtual to physical address
translation, and a skeleton exception mechanism.
20061006 Adding more SH instructions (various loads and stores, rte,
negc, muls.w, various privileged register-move instructions).
20061007 More SH instructions: various move instructions, trapa, div0s,
float, fdiv, ftrc.
Continuing on dev_rtc; removing the rtc demo.
20061008 Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
programs using KOS libs need this.)
Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
fmul, fadd, various floating-point moves, etc. A 256-byte
demo for Dreamcast runs :-)
20061012 Adding the SH "lds Rm,pr" and bsr instructions.
20061013 More SH instructions: "sts fpscr,rn", tas.b, and some more
floating point instructions, cmp/str, and more moves.
Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014 Generalizing the expression evaluator (used in the built-in
debugger) to support parentheses and +-*/%^&|.
20061015 Removing the experimental tlb index hint code in
mips_memory_v2p.c, since it didn't really have any effect.
20061017 Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
frchg, and some other instructions. Fixing missing sign-
extension in an 8-bit load instruction.
20061019 Adding a simple dev_dreamcast_rtc.
Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021 Continuing on various SH and Dreamcast things: sh4 timers,
debug messages for dev_pvr, fixing some virtual address
translation bugs, adding the bsrf instruction.
The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
Adding a dummy dev_dreamcast_asic.c (not really useful yet).
Implementing simple support for Store Queues.
Beginning on the PVR Tile Accelerator.
20061022 Generalizing the PVR framebuffer to support off-screen drawing,
multiple bit-depths, etc. (A small speed penalty, but most
likely worth it.)
Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
fschg, and some more); correcting bugs in "fsca" and "float".
20061024 Adding the SH ftrv (matrix * vector) instruction. Marcus
Comstedt's "tatest" example runs :) (wireframe only).
Correcting disassembly for SH floating point instructions that
use the xd* registers.
Adding the SH fsts instruction.
In memory_device_dyntrans_access(), only the currently used
range is now invalidated, and not the entire device range.
20061025 Adding a dummy AVR32 cpu mode skeleton.
20061026 Various Dreamcast updates; beginning on a Maple bus controller.
20061027 Continuing on the Maple bus. A bogus Controller, Keyboard, and
Mouse can now be detected by NetBSD and KOS homebrew programs.
Cleaning up the SH4 Timer Management Unit, and beginning on
SH4 interrupts.
Implementing the Dreamcast SYSASIC.
20061028 Continuing on the SYSASIC.
Adding the SH fsqrt instruction.
memory_sh.c now actually scans the ITLB.
Fixing a bug in dev_sh4.c, related to associative writes into
the memory-mapped UTLB array. NetBSD/dreamcast now reaches
userland stably, and prints the "Terminal type?" message :-]
Implementing enough of the Dreamcast keyboard to make NetBSD
accept it for input.
Enabling SuperH for stable (non-development) builds.
Adding NetBSD/dreamcast to the documentation, although it
doesn't support root-on-nfs yet.
20061029 Changing usleep(1) calls in the debugger to to usleep(10000)
(according to Brian Foley, this makes GXemul run better on
MacOS X).
Making the Maple "Controller" do something (enough to barely
interact with dcircus.elf).
20061030-31 Some progress on the PVR. More test programs start running (but
with strange output).
Various other SH4-related updates.
20061102 Various Dreamcast and SH4 updates; more KOS demos run now.
20061104 Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105 Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
Testing for the release.
============== RELEASE 0.4.3 ==============
| 1 | #ifndef COP0_H |
| 2 | #define COP0_H |
| 3 | |
| 4 | /* |
| 5 | * Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions are met: |
| 9 | * |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. The name of the author may not be used to endorse or promote products |
| 16 | * derived from this software without specific prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 28 | * SUCH DAMAGE. |
| 29 | * |
| 30 | * |
| 31 | * $Id: cop0.h,v 1.12 2006/10/02 08:03:16 debug Exp $ |
| 32 | * |
| 33 | * Misc. definitions for coprocessor 0. |
| 34 | */ |
| 35 | |
| 36 | |
| 37 | /* TODO: Coproc registers are actually CPU dependent, so an R4000 |
| 38 | has other bits/registers than an R3000... |
| 39 | TODO 2: CPUs like the R10000 are probably even a bit more different. */ |
| 40 | |
| 41 | /* Coprocessor 0's registers' names: (max 8 characters long) */ |
| 42 | #define COP0_NAMES { \ |
| 43 | "index", "random", "entrylo0", "entrylo1", \ |
| 44 | "context", "pagemask", "wired", "reserv7", \ |
| 45 | "badvaddr", "count", "entryhi", "compare", \ |
| 46 | "status", "cause", "epc", "prid", \ |
| 47 | "config", "lladdr", "watchlo", "watchhi", \ |
| 48 | "xcontext", "reserv21", "reserv22", "debug", \ |
| 49 | "depc", "perfcnt", "errctl", "cacheerr", \ |
| 50 | "tagdatlo", "tagdathi", "errorepc", "desave" } |
| 51 | |
| 52 | #define COP0_INDEX 0 |
| 53 | #define INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */ |
| 54 | #define INDEX_MASK 0x3f |
| 55 | #define R2K3K_INDEX_P 0x80000000UL |
| 56 | #define R2K3K_INDEX_MASK 0x3f00 |
| 57 | #define R2K3K_INDEX_SHIFT 8 |
| 58 | #define COP0_RANDOM 1 |
| 59 | #define RANDOM_MASK 0x3f |
| 60 | #define R2K3K_RANDOM_MASK 0x3f00 |
| 61 | #define R2K3K_RANDOM_SHIFT 8 |
| 62 | #define COP0_ENTRYLO0 2 |
| 63 | #define COP0_ENTRYLO1 3 |
| 64 | /* R4000 ENTRYLO: */ |
| 65 | #define ENTRYLO_PFN_MASK 0x3fffffc0 |
| 66 | #define ENTRYLO_PFN_SHIFT 6 |
| 67 | #define ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */ |
| 68 | #define ENTRYLO_C_SHIFT 3 |
| 69 | #define ENTRYLO_D 0x04 /* Dirty bit */ |
| 70 | #define ENTRYLO_V 0x02 /* Valid bit */ |
| 71 | #define ENTRYLO_G 0x01 /* Global bit */ |
| 72 | /* R2000/R3000 ENTRYLO: */ |
| 73 | #define R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL |
| 74 | #define R2K3K_ENTRYLO_PFN_SHIFT 12 |
| 75 | #define R2K3K_ENTRYLO_N 0x800 |
| 76 | #define R2K3K_ENTRYLO_D 0x400 |
| 77 | #define R2K3K_ENTRYLO_V 0x200 |
| 78 | #define R2K3K_ENTRYLO_G 0x100 |
| 79 | #define COP0_CONTEXT 4 |
| 80 | #define CONTEXT_BADVPN2_MASK 0x007ffff0 |
| 81 | #define CONTEXT_BADVPN2_MASK_R4100 0x01fffff0 |
| 82 | #define CONTEXT_BADVPN2_SHIFT 4 |
| 83 | #define R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc |
| 84 | #define R2K3K_CONTEXT_BADVPN_SHIFT 2 |
| 85 | #define COP0_PAGEMASK 5 |
| 86 | #define PAGEMASK_MASK 0x01ffe000 |
| 87 | #define PAGEMASK_SHIFT 13 |
| 88 | #define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */ |
| 89 | /* how about others? */ |
| 90 | #define PAGEMASK_SHIFT_R4100 11 |
| 91 | #define COP0_WIRED 6 |
| 92 | #define COP0_RESERV7 7 |
| 93 | #define COP0_BADVADDR 8 |
| 94 | #define COP0_COUNT 9 |
| 95 | #define COP0_ENTRYHI 10 |
| 96 | /* R4000 ENTRYHI: */ |
| 97 | #define ENTRYHI_R_MASK 0xc000000000000000ULL |
| 98 | #define ENTRYHI_R_XKPHYS 0x8000000000000000ULL |
| 99 | #define ENTRYHI_R_SHIFT 62 |
| 100 | #define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL |
| 101 | #define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL |
| 102 | #define ENTRYHI_VPN2_SHIFT 13 |
| 103 | #define ENTRYHI_ASID 0xff |
| 104 | #define TLB_G (1 << 12) |
| 105 | /* R2000/R3000 ENTRYHI: */ |
| 106 | #define R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL |
| 107 | #define R2K3K_ENTRYHI_VPN_SHIFT 12 |
| 108 | #define R2K3K_ENTRYHI_ASID_MASK 0xfc0 |
| 109 | #define R2K3K_ENTRYHI_ASID_SHIFT 6 |
| 110 | #define COP0_COMPARE 11 |
| 111 | #define COP0_STATUS 12 |
| 112 | #define STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */ |
| 113 | #define STATUS_CU_SHIFT 28 |
| 114 | #define STATUS_RP 0x08000000 /* reduced power */ |
| 115 | #define STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */ |
| 116 | #define STATUS_RE 0x02000000 /* reverse endian bit */ |
| 117 | #define STATUS_BEV 0x00400000 /* boot exception vectors (?) */ |
| 118 | /* STATUS_DS: TODO */ |
| 119 | #define STATUS_IM_MASK 0xff00 |
| 120 | #define STATUS_IM_SHIFT 8 |
| 121 | #define STATUS_KX 0x80 |
| 122 | #define STATUS_SX 0x40 |
| 123 | #define STATUS_UX 0x20 |
| 124 | #define STATUS_KSU_MASK 0x18 |
| 125 | #define STATUS_KSU_SHIFT 3 |
| 126 | #define STATUS_ERL 0x04 |
| 127 | #define STATUS_EXL 0x02 |
| 128 | #define STATUS_IE 0x01 |
| 129 | #define R5900_STATUS_EDI 0x20000 /* EI/DI instruction enable */ |
| 130 | #define R5900_STATUS_EIE 0x10000 /* Enable Interrupt Enable */ |
| 131 | #define COP0_CAUSE 13 |
| 132 | #define CAUSE_BD 0x80000000UL /* branch delay flag */ |
| 133 | #define CAUSE_CE_MASK 0x30000000 /* which coprocessor */ |
| 134 | #define CAUSE_CE_SHIFT 28 |
| 135 | #define CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */ |
| 136 | #define CAUSE_WP 0x00400000UL /* watch exception ... */ |
| 137 | #define CAUSE_IP_MASK 0xff00 /* interrupt pending */ |
| 138 | #define CAUSE_IP_SHIFT 8 |
| 139 | #define CAUSE_EXCCODE_MASK 0x7c /* exception code */ |
| 140 | #define R2K3K_CAUSE_EXCCODE_MASK 0x3c |
| 141 | #define CAUSE_EXCCODE_SHIFT 2 |
| 142 | #define COP0_EPC 14 |
| 143 | #define COP0_PRID 15 |
| 144 | #define COP0_CONFIG 16 |
| 145 | #define COP0_LLADDR 17 |
| 146 | #define COP0_WATCHLO 18 |
| 147 | #define COP0_WATCHHI 19 |
| 148 | #define COP0_XCONTEXT 20 |
| 149 | #define XCONTEXT_R_MASK 0x180000000ULL |
| 150 | #define XCONTEXT_R_SHIFT 31 |
| 151 | #define XCONTEXT_BADVPN2_MASK 0x7ffffff0 |
| 152 | #define XCONTEXT_BADVPN2_SHIFT 4 |
| 153 | #define COP0_FRAMEMASK 21 /* R10000 */ |
| 154 | #define COP0_RESERV22 22 |
| 155 | #define COP0_DEBUG 23 |
| 156 | #define COP0_DEPC 24 |
| 157 | #define COP0_PERFCNT 25 |
| 158 | #define COP0_ERRCTL 26 |
| 159 | #define COP0_CACHEERR 27 |
| 160 | #define COP0_TAGDATA_LO 28 |
| 161 | #define COP0_TAGDATA_HI 29 |
| 162 | #define COP0_ERROREPC 30 |
| 163 | #define COP0_DESAVE 31 |
| 164 | |
| 165 | /* Coprocessor 1's registers: */ |
| 166 | #define COP1_REVISION 0 |
| 167 | #define COP1_REVISION_MIPS3D 0x80000 /* MIPS3D support */ |
| 168 | #define COP1_REVISION_PS 0x40000 /* Paired-single support */ |
| 169 | #define COP1_REVISION_DOUBLE 0x20000 /* double precision support */ |
| 170 | #define COP1_REVISION_SINGLE 0x10000 /* single precision support */ |
| 171 | #define COP1_CONTROLSTATUS 31 |
| 172 | |
| 173 | /* CP0's STATUS KSU values: */ |
| 174 | #define KSU_KERNEL 0 |
| 175 | #define KSU_SUPERVISOR 1 |
| 176 | #define KSU_USER 2 |
| 177 | |
| 178 | #define EXCEPTION_NAMES { \ |
| 179 | "INT", "MOD", "TLBL", "TLBS", "ADEL", "ADES", "IBE", "DBE", \ |
| 180 | "SYS", "BP", "RI", "CPU", "OV", "TR", "VCEI", "FPE", \ |
| 181 | "16?", "17?", "C2E", "19?", "20?", "21?", "MDMX", "WATCH", \ |
| 182 | "MCHECK", "25?", "26?", "27?", "28?", "29?", "CACHEERR", "VCED" } |
| 183 | |
| 184 | /* CP0's CAUSE exception codes: */ |
| 185 | #define EXCEPTION_INT 0 /* Interrupt */ |
| 186 | #define EXCEPTION_MOD 1 /* TLB modification exception */ |
| 187 | #define EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */ |
| 188 | #define EXCEPTION_TLBS 3 /* TLB exception (store) */ |
| 189 | #define EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */ |
| 190 | #define EXCEPTION_ADES 5 /* Address Error Exception (store) */ |
| 191 | #define EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */ |
| 192 | #define EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */ |
| 193 | #define EXCEPTION_SYS 8 /* Syscall */ |
| 194 | #define EXCEPTION_BP 9 /* Breakpoint */ |
| 195 | #define EXCEPTION_RI 10 /* Reserved instruction */ |
| 196 | #define EXCEPTION_CPU 11 /* CoProcessor Unusable */ |
| 197 | #define EXCEPTION_OV 12 /* Arithmetic Overflow */ |
| 198 | #define EXCEPTION_TR 13 /* Trap exception */ |
| 199 | #define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */ |
| 200 | #define EXCEPTION_FPE 15 /* Floating point exception */ |
| 201 | /* 16..17: Available for "implementation dependent use" */ |
| 202 | #define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */ |
| 203 | /* 19..21: Reserved */ |
| 204 | #define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */ |
| 205 | #define EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */ |
| 206 | #define EXCEPTION_MCHECK 24 /* MIPS64 Machine Check */ |
| 207 | /* 25..29: Reserved */ |
| 208 | #define EXCEPTION_CACHEERR 30 /* MIPS64 Cache Error */ |
| 209 | #define EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */ |
| 210 | |
| 211 | |
| 212 | #endif /* COP0_H */ |
| 213 |
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