/[gxemul]/trunk/src/include/cop0.h
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Annotation of /trunk/src/include/cop0.h

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Revision 4 - (hide annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 6 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============
1 dpavlin 4 #ifndef COP0_H
2     #define COP0_H
3    
4     /*
5     * Copyright (C) 2003-2005 Anders Gavare. All rights reserved.
6     *
7     * Redistribution and use in source and binary forms, with or without
8     * modification, are permitted provided that the following conditions are met:
9     *
10     * 1. Redistributions of source code must retain the above copyright
11     * notice, this list of conditions and the following disclaimer.
12     * 2. Redistributions in binary form must reproduce the above copyright
13     * notice, this list of conditions and the following disclaimer in the
14     * documentation and/or other materials provided with the distribution.
15     * 3. The name of the author may not be used to endorse or promote products
16     * derived from this software without specific prior written permission.
17     *
18     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19     * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20     * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21     * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22     * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23     * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24     * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25     * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26     * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27     * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28     * SUCH DAMAGE.
29     *
30     *
31     * $Id: cop0.h,v 1.6 2005/01/18 06:22:58 debug Exp $
32     *
33     * Misc. definitions for coprocessor 0.
34     */
35    
36    
37     /* TODO: Coproc registers are actually CPU dependant, so an R4000
38     has other bits/registers than an R3000...
39     TODO 2: CPUs like the R10000 are probably even a bit more different. */
40    
41     /* Coprocessor 0's registers' names: (max 8 characters long) */
42     #define COP0_NAMES { \
43     "index", "random", "entrylo0", "entrylo1", \
44     "context", "pagemask", "wired", "reserv7", \
45     "badvaddr", "count", "entryhi", "compare", \
46     "status", "cause", "epc", "prid", \
47     "config", "lladdr", "watchlo", "watchhi", \
48     "xcontext", "reserv21", "reserv22", "debug", \
49     "depc", "perfcnt", "errctl", "cacheerr", \
50     "tagdatlo", "tagdathi", "errorepc", "desave" }
51    
52     #define COP0_INDEX 0
53     #define INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */
54     #define INDEX_MASK 0x3f
55     #define R2K3K_INDEX_P 0x80000000UL
56     #define R2K3K_INDEX_MASK 0x3f00
57     #define R2K3K_INDEX_SHIFT 8
58     #define COP0_RANDOM 1
59     #define RANDOM_MASK 0x3f
60     #define R2K3K_RANDOM_MASK 0x3f00
61     #define R2K3K_RANDOM_SHIFT 8
62     #define COP0_ENTRYLO0 2
63     #define COP0_ENTRYLO1 3
64     /* R4000 ENTRYLO: */
65     #define ENTRYLO_PFN_MASK 0x3fffffc0
66     #define ENTRYLO_PFN_SHIFT 6
67     #define ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */
68     #define ENTRYLO_C_SHIFT 3
69     #define ENTRYLO_D 0x04 /* Dirty bit */
70     #define ENTRYLO_V 0x02 /* Valid bit */
71     #define ENTRYLO_G 0x01 /* Global bit */
72     /* R2000/R3000 ENTRYLO: */
73     #define R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL
74     #define R2K3K_ENTRYLO_PFN_SHIFT 12
75     #define R2K3K_ENTRYLO_N 0x800
76     #define R2K3K_ENTRYLO_D 0x400
77     #define R2K3K_ENTRYLO_V 0x200
78     #define R2K3K_ENTRYLO_G 0x100
79     #define COP0_CONTEXT 4
80     #define CONTEXT_BADVPN2_MASK 0x007ffff0
81     #define CONTEXT_BADVPN2_MASK_R4100 0x01fffff0
82     #define CONTEXT_BADVPN2_SHIFT 4
83     #define R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc
84     #define R2K3K_CONTEXT_BADVPN_SHIFT 2
85     #define COP0_PAGEMASK 5
86     #define PAGEMASK_MASK 0x01ffe000
87     #define PAGEMASK_SHIFT 13
88     #define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, how about others? */
89     #define PAGEMASK_SHIFT_R4100 11
90     #define COP0_WIRED 6
91     #define COP0_RESERV7 7
92     #define COP0_BADVADDR 8
93     #define COP0_COUNT 9
94     #define COP0_ENTRYHI 10
95     /* R4000 ENTRYHI: */
96     #define ENTRYHI_R_MASK 0xc000000000000000ULL
97     #define ENTRYHI_R_SHIFT 62
98     #define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL
99     #define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL
100     #define ENTRYHI_VPN2_SHIFT 13
101     #define ENTRYHI_ASID 0xff
102     #define TLB_G (1 << 12)
103     /* R2000/R3000 ENTRYHI: */
104     #define R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL
105     #define R2K3K_ENTRYHI_VPN_SHIFT 12
106     #define R2K3K_ENTRYHI_ASID_MASK 0xfc0
107     #define R2K3K_ENTRYHI_ASID_SHIFT 6
108     #define COP0_COMPARE 11
109     #define COP0_STATUS 12
110     #define STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */
111     #define STATUS_CU_SHIFT 28
112     #define STATUS_RP 0x08000000 /* reduced power */
113     #define STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */
114     #define STATUS_RE 0x02000000 /* reverse endian bit */
115     #define STATUS_BEV 0x00400000 /* boot exception vectors (?) */
116     /* STATUS_DS: TODO */
117     #define STATUS_IM_MASK 0xff00
118     #define STATUS_IM_SHIFT 8
119     #define STATUS_KX 0x80
120     #define STATUS_SX 0x40
121     #define STATUS_UX 0x20
122     #define STATUS_KSU_MASK 0x18
123     #define STATUS_KSU_SHIFT 3
124     #define STATUS_ERL 0x04
125     #define STATUS_EXL 0x02
126     #define STATUS_IE 0x01
127     #define R5900_STATUS_EIE 0x10000
128     #define COP0_CAUSE 13
129     #define CAUSE_BD 0x80000000UL /* branch delay flag */
130     #define CAUSE_CE_MASK 0x30000000 /* which coprocessor */
131     #define CAUSE_CE_SHIFT 28
132     #define CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */
133     #define CAUSE_WP 0x00400000UL /* watch exception ... */
134     #define CAUSE_IP_MASK 0xff00 /* interrupt pending */
135     #define CAUSE_IP_SHIFT 8
136     #define CAUSE_EXCCODE_MASK 0x7c /* exception code */
137     #define R2K3K_CAUSE_EXCCODE_MASK 0x3c
138     #define CAUSE_EXCCODE_SHIFT 2
139     #define COP0_EPC 14
140     #define COP0_PRID 15
141     #define COP0_CONFIG 16
142     #define COP0_LLADDR 17
143     #define COP0_WATCHLO 18
144     #define COP0_WATCHHI 19
145     #define COP0_XCONTEXT 20
146     #define XCONTEXT_R_MASK 0x180000000ULL
147     #define XCONTEXT_R_SHIFT 31
148     #define XCONTEXT_BADVPN2_MASK 0x7ffffff0
149     #define XCONTEXT_BADVPN2_SHIFT 4
150     #define COP0_FRAMEMASK 21 /* R10000 */
151     #define COP0_RESERV22 22
152     #define COP0_DEBUG 23
153     #define COP0_DEPC 24
154     #define COP0_PERFCNT 25
155     #define COP0_ERRCTL 26
156     #define COP0_CACHEERR 27
157     #define COP0_TAGDATA_LO 28
158     #define COP0_TAGDATA_HI 29
159     #define COP0_ERROREPC 30
160     #define COP0_DESAVE 31
161    
162     /* Coprocessor 1's registers: */
163     #define COP1_REVISION 0
164     #define COP1_REVISION_MIPS3D 0x80000 /* MIPS3D support */
165     #define COP1_REVISION_PS 0x40000 /* Paired-single support */
166     #define COP1_REVISION_DOUBLE 0x20000 /* double precision support */
167     #define COP1_REVISION_SINGLE 0x10000 /* single precision support */
168     #define COP1_CONTROLSTATUS 31
169    
170     /* CP0's STATUS KSU values: */
171     #define KSU_KERNEL 0
172     #define KSU_SUPERVISOR 1
173     #define KSU_USER 2
174    
175     #define EXCEPTION_NAMES { \
176     "INT", "MOD", "TLBL", "TLBS", "ADEL", "ADES", "IBE", "DBE", \
177     "SYS", "BP", "RI", "CPU", "OV", "TR", "VCEI", "FPE", \
178     "16?", "17?", "C2E", "19?", "20?", "21?", "MDMX", "WATCH", \
179     "MCHECK", "25?", "26?", "27?", "28?", "29?", "CACHEERR", "VCED" }
180    
181     /* CP0's CAUSE exception codes: */
182     #define EXCEPTION_INT 0 /* Interrupt */
183     #define EXCEPTION_MOD 1 /* TLB modification exception */
184     #define EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */
185     #define EXCEPTION_TLBS 3 /* TLB exception (store) */
186     #define EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */
187     #define EXCEPTION_ADES 5 /* Address Error Exception (store) */
188     #define EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */
189     #define EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */
190     #define EXCEPTION_SYS 8 /* Syscall */
191     #define EXCEPTION_BP 9 /* Breakpoint */
192     #define EXCEPTION_RI 10 /* Reserved instruction */
193     #define EXCEPTION_CPU 11 /* CoProcessor Unusable */
194     #define EXCEPTION_OV 12 /* Arithmetic Overflow */
195     #define EXCEPTION_TR 13 /* Trap exception */
196     #define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */
197     #define EXCEPTION_FPE 15 /* Floating point exception */
198     /* 16..17: Available for "implementation dependant use" */
199     #define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */
200     /* 19..21: Reserved */
201     #define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */
202     #define EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */
203     #define EXCEPTION_MCHECK 24 /* MIPS64 Machine Check */
204     /* 25..29: Reserved */
205     #define EXCEPTION_CACHEERR 30 /* MIPS64 Cache Error */
206     #define EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */
207    
208    
209     #endif /* COP0_H */
210    
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