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Revision Log
++ trunk/HISTORY (local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219 Various minor updates. Removing the old MIPS16 skeleton code,
because it will need to be rewritten for dyntrans anyway.
20060220-22 Removing the non-working dyntrans backend support.
Continuing on the 64-bit dyntrans virtual memory generalization.
20060223 More work on the 64-bit vm generalization.
20060225 Beginning on MIPS dyntrans load/store instructions.
Minor PPC updates (64-bit load/store, etc).
Fixes for the variable-instruction-length framework, some
minor AVR updates (a simple Hello World program works!).
Beginning on a skeleton for automatically generating documen-
tation (for devices etc.).
20060226 PPC updates (adding some more 64-bit instructions, etc).
AVR updates (more instructions).
FINALLY found and fixed the zs bug, making NetBSD/macppc
accept the serial console.
20060301 Adding more AVR instructions.
20060304 Continuing on AVR-related stuff. Beginning on a framework for
cycle-accurate device emulation. Adding an experimental "PAL
TV" device (just a dummy so far).
20060305 Adding more AVR instructions.
Adding a dummy epcom serial controller (for TS7200 emulation).
20060310 Removing the emul() command from configuration files, so only
net() and machine() are supported.
Minor progress on the MIPS dyntrans rewrite.
20060311 Continuing on the MIPS dyntrans rewrite (adding more
instructions, etc).
20060315 Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
beql, bnel, slti[u], various loads and stores).
20060316 Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
used.
Adding more MIPS dyntrans instructions, and fixing bugs.
20060318 Implementing fast loads/stores for MIPS dyntrans (big/little
endian, 32-bit and 64-bit modes).
20060320 Making MIPS dyntrans the default configure option; use
"--enable-oldmips" to use the old bintrans system.
Adding MIPS dyntrans dmult[u]; minor updates.
20060322 Continuing... adding some more instructions.
Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323 Moving src/debugger.c into a new directory (src/debugger/).
20060324 Fixing the hack used to load PPC ELFs (useful for relocated
Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26 Beginning to experiment with GDB remote serial protocol
connections; adding a -G command line option for selecting
which TCP port to listen to.
20060330 Beginning a major cleanup to replace things like "0x%016llx"
with more correct "0x%016"PRIx64, etc.
Continuing on the GDB remote serial protocol support.
20060331 More cleanup, and some minor GDB remote progress.
20060402 Adding a hack to the configure script, to allow compilation
on systems that lack PRIx64 etc.
20060406 Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
replacing it with a better fix from Olivier Houchard.
20060407 A remote debugger (gdb or ddd) can now start and stop the
emulator using the GDB remote serial protocol, and registers
and memory can be read. MIPS only for now.
20060408 More GDB progress: single-stepping also works, and also adding
support for ARM, PowerPC, and Alpha targets.
Continuing on the delay-slot-across-page-boundary issue.
20060412 Minor update: beginning to add support for the SPARC target
to the remote GDB functionality.
20060414 Various MIPS updates: adding more instructions for dyntrans
(eret, add), and making some exceptions work. Fixing a bug
in dmult[u].
Implementing the first SPARC instructions (sethi, or).
20060415 Adding "magic trap" instructions so that PROM calls can be
software emulated in MIPS dyntrans.
Adding more MIPS dyntrans instructions (ddiv, dadd) and
fixing another bug in dmult.
20060416 More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
rfi, an ugly hack for supporting R2000/R3000 style faked caches,
preliminary interrupt support, and various other updates and
bugfixes.
20060417 Adding more SPARC instructions (add, sub, sll[x], sra[x],
srl[x]), and useful SPARC header definitions.
Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
x86 updates related to variable instruction length stuff.
Adding unaligned loads/stores to the MIPS dyntrans mode (but
still using the pre-dyntrans (slow) imlementation).
20060419 Fixing a MIPS dyntrans exception-in-delay-slot bug.
Removing the old "show opcode statistics" functionality, since
it wasn't really useful and isn't implemented for dyntrans.
Single-stepping (or running with instruction trace) now looks
ok with dyntrans with delay-slot architectures.
20060420 Minor hacks (removing the -B command line option when compiled
for non-bintrans, and some other very minor updates).
Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422 Applying fixes for bugs discovered by Nils Weller's nwcc
(static DEC memmap => now per machine, and adding an extern
keyword in cpu_arm_instr.c).
Finally found one of the MIPS dyntrans bugs that I've been
looking for (copy/paste spelling error BIG vs LITTLE endian in
cpu_mips_instr_loadstore.c for 16-bit fast stores).
FINALLY found the major MIPS dyntrans bug: slti vs sltiu
signed/unsigned code in cpu_mips_instr.c. :-)
Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
NetBSD/hpcmips can now reach userland when using dyntrans :-)
Adding some more x86 dyntrans instructions.
Finally removed the old Alpha-specific virtual memory code,
and replaced it with the generic 64-bit version.
Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423 Continuing on the delay-slot-across-page-boundary issue;
adding an end_of_page2 ic slot (like I had planned before, but
had removed for some reason).
Adding a quick-and-dirty fallback to legacy coprocessor 1
code (i.e. skipping dyntrans implementation for now).
NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
R4400) can now be installed and run. :-) (Many bugs left
to fix, though.)
Adding more MIPS dyntrans instructions: madd[u], msub[u].
Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
maps somewhat (disassembly and dyntrans instruction decoding).
20060424 Adding an isa_revision field to mips_cpu_types.h, and making
sure that SPECIAL3 opcodes cause Reserved Instruction
exceptions on MIPS32/64 revisions lower than 2.
Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
instructions.
20060425 Removing the -m command line option ("run at most x
instructions") and -T ("single_step_on_bad_addr"), because
they never worked correctly with dyntrans anyway.
Freshening up the man page.
20060428 Adding more MIPS dyntrans instructions: bltzal[l], idle.
Enabling MIPS dyntrans compare interrupts.
20060429 FINALLY found the weird dyntrans bug, causing NetBSD etc. to
behave strangely: some floating point code (conditional
coprocessor branches) could not be reused from the old
non-dyntrans code. The "quick-and-dirty fallback" only appeared
to work. Fixing by implementing bc1* for MIPS dyntrans.
More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
Freshening up MIPS floating point disassembly appearance.
20060430 Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
"por" and "pextlw".
20060504 Disabling -u (userland emulation) unless compiled as unstable
development version.
Beginning on freshening up the testmachine include files,
to make it easier to reuse those files (placing them in
src/include/testmachine/), and beginning on a set of "demos"
or "tutorials" for the testmachine functionality.
Minor updates to the MIPS GDB remote protocol stub.
Refreshing doc/experiments.html and gdb_remote.html.
Enabling Alpha emulation in the stable release configuration,
even though no guest OSes for Alpha can run yet.
20060505 Adding a generic 'settings' object, which will contain
references to settable variables (which will later be possible
to access using the debugger).
20060506 Updating dev_disk and corresponding demo/documentation (and
switching from SCSI to IDE disk types, so it actually works
with current test machines :-).
20060510 Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
so that fseeko() doesn't give a warning.
Updating the section about how dyntrans works (the "runnable
IR") in doc/intro.html.
Instruction updates (some x64=1 checks, some more R5900
dyntrans stuff: better mul/mult separation from MIPS32/64,
adding ei and di).
Updating MIPS cpuregs.h to a newer one (from NetBSD).
Adding more MIPS dyntrans instructions: deret, ehb.
20060514 Adding disassembly and beginning implementation of SPARC wr
and wrpr instructions.
20060515 Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
machines. Adding the 32-bit "rd psr" instruction.
20060517 Disassembly support for the general SPARC rd instruction.
Partial implementation of the cmp (subcc) instruction.
Some other minor updates (making sure that R5900 processors
start up with the EIE bit enabled, otherwise Linux/playstation2
receives no interrupts).
20060519 Minor MIPS updates/cleanups.
20060521 Moving the MeshCube machine into evbmips; this seems to work
reasonably well with a snapshot of a NetBSD MeshCube kernel.
Cleanup/fix of MIPS config0 register initialization.
20060529 Minor MIPS fixes, including a sign-extension fix to the
unaligned load/store code, which makes NetBSD/pmax on R3000
work better with dyntrans. (Ultrix and Linux/DECstation still
don't work, though.)
20060530 Minor updates to the Alpha machine mode: adding an AlphaBook
mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531 Applying a bugfix for the MIPS dyntrans sc[d] instruction from
Ondrej Palkovsky. (Many thanks.)
20060601 Minifix to allow ARM immediate msr instruction to not give
an error for some valid values.
More Alpha updates.
20060602 Some minor Alpha updates.
20060603 Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
first boot messages :-) on an emulated Alphabook 1.
20060612 Minor updates; adding a dev_ether.h include file for the
testmachine ether device. Continuing the hunt for the dyntrans
bug which makes Linux and Ultrix on DECstation behave
strangely... FINALLY found it! It seems to be related to
invalidation of the translation cache, on tlbw{r,i}. There
also seems to be some remaining interrupt-related problems.
20060614 Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
(so that it uses 16 32-bit registers if the FR bit in the
status register is not set).
20060616 REMOVING BINTRANS COMPLETELY!
Removing the old MIPS interpretation mode.
Removing the MFHILO_DELAY and instruction delay stuff, because
they wouldn't work with dyntrans anyway.
20060617 Some documentation updates (adding "NetBSD-archive" to some
URLs, and new Debian/DECstation installation screenshots).
Removing the "tracenull" and "enable-caches" configure options.
Improving MIPS dyntrans performance somewhat (only invalidate
translations if necessary, on writes to the entryhi register,
instead of doing it for all cop0 writes).
20060618 More cleanup after the removal of the old MIPS emulation.
Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
only semi-successful so far (for R3000).
20060620 Minor update to allow clean compilation again on Tru64/Alpha.
20060622 MIPS cleanup and fixes (removing the pc_last stuff, which
doesn't make sense with dyntrans anyway, and fixing a cross-
page-delay-slot-with-exception case in end_of_page).
Removing the old max_random_cycles_per_chunk stuff, and the
concept of cycles vs instructions for MIPS emulation.
FINALLY found and fixed the bug which caused NetBSD/pmax
clocks to behave strangely (it was a load to the zero register,
which was treated as a NOP; now it is treated as a load to a
dummy scratch register).
20060623 Increasing the dyntrans chunk size back to
N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
Preparing for a quick release, even though there are known
bugs, and performance for non-R3000 MIPS emulation is very
poor. :-/
Reverting to half the dyntrans chunk size again, because
NetBSD/cats seemed less stable with full size chunks. :(
NetBSD/sgimips 3.0 can now run :-) (With release 0.3.8, only
NetBSD/sgimips 2.1 worked, not 3.0.)
============== RELEASE 0.4.0 ==============
| 1 | dpavlin | 4 | #ifndef COP0_H |
| 2 | #define COP0_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | dpavlin | 24 | * Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
| 6 | dpavlin | 4 | * |
| 7 | * Redistribution and use in source and binary forms, with or without | ||
| 8 | * modification, are permitted provided that the following conditions are met: | ||
| 9 | * | ||
| 10 | * 1. Redistributions of source code must retain the above copyright | ||
| 11 | * notice, this list of conditions and the following disclaimer. | ||
| 12 | * 2. Redistributions in binary form must reproduce the above copyright | ||
| 13 | * notice, this list of conditions and the following disclaimer in the | ||
| 14 | * documentation and/or other materials provided with the distribution. | ||
| 15 | * 3. The name of the author may not be used to endorse or promote products | ||
| 16 | * derived from this software without specific prior written permission. | ||
| 17 | * | ||
| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | ||
| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | ||
| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | ||
| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | ||
| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | ||
| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | ||
| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | ||
| 28 | * SUCH DAMAGE. | ||
| 29 | * | ||
| 30 | * | ||
| 31 | dpavlin | 24 | * $Id: cop0.h,v 1.11 2006/05/10 20:04:59 debug Exp $ |
| 32 | dpavlin | 4 | * |
| 33 | * Misc. definitions for coprocessor 0. | ||
| 34 | */ | ||
| 35 | |||
| 36 | |||
| 37 | dpavlin | 18 | /* TODO: Coproc registers are actually CPU dependent, so an R4000 |
| 38 | dpavlin | 4 | has other bits/registers than an R3000... |
| 39 | TODO 2: CPUs like the R10000 are probably even a bit more different. */ | ||
| 40 | |||
| 41 | /* Coprocessor 0's registers' names: (max 8 characters long) */ | ||
| 42 | #define COP0_NAMES { \ | ||
| 43 | "index", "random", "entrylo0", "entrylo1", \ | ||
| 44 | "context", "pagemask", "wired", "reserv7", \ | ||
| 45 | "badvaddr", "count", "entryhi", "compare", \ | ||
| 46 | "status", "cause", "epc", "prid", \ | ||
| 47 | "config", "lladdr", "watchlo", "watchhi", \ | ||
| 48 | "xcontext", "reserv21", "reserv22", "debug", \ | ||
| 49 | "depc", "perfcnt", "errctl", "cacheerr", \ | ||
| 50 | "tagdatlo", "tagdathi", "errorepc", "desave" } | ||
| 51 | |||
| 52 | #define COP0_INDEX 0 | ||
| 53 | #define INDEX_P 0x80000000UL /* Probe failure bit. Set by tlbp */ | ||
| 54 | #define INDEX_MASK 0x3f | ||
| 55 | #define R2K3K_INDEX_P 0x80000000UL | ||
| 56 | #define R2K3K_INDEX_MASK 0x3f00 | ||
| 57 | #define R2K3K_INDEX_SHIFT 8 | ||
| 58 | #define COP0_RANDOM 1 | ||
| 59 | #define RANDOM_MASK 0x3f | ||
| 60 | #define R2K3K_RANDOM_MASK 0x3f00 | ||
| 61 | #define R2K3K_RANDOM_SHIFT 8 | ||
| 62 | #define COP0_ENTRYLO0 2 | ||
| 63 | #define COP0_ENTRYLO1 3 | ||
| 64 | /* R4000 ENTRYLO: */ | ||
| 65 | #define ENTRYLO_PFN_MASK 0x3fffffc0 | ||
| 66 | #define ENTRYLO_PFN_SHIFT 6 | ||
| 67 | #define ENTRYLO_C_MASK 0x00000038 /* Coherency attribute */ | ||
| 68 | #define ENTRYLO_C_SHIFT 3 | ||
| 69 | #define ENTRYLO_D 0x04 /* Dirty bit */ | ||
| 70 | #define ENTRYLO_V 0x02 /* Valid bit */ | ||
| 71 | #define ENTRYLO_G 0x01 /* Global bit */ | ||
| 72 | /* R2000/R3000 ENTRYLO: */ | ||
| 73 | #define R2K3K_ENTRYLO_PFN_MASK 0xfffff000UL | ||
| 74 | #define R2K3K_ENTRYLO_PFN_SHIFT 12 | ||
| 75 | #define R2K3K_ENTRYLO_N 0x800 | ||
| 76 | #define R2K3K_ENTRYLO_D 0x400 | ||
| 77 | #define R2K3K_ENTRYLO_V 0x200 | ||
| 78 | #define R2K3K_ENTRYLO_G 0x100 | ||
| 79 | #define COP0_CONTEXT 4 | ||
| 80 | #define CONTEXT_BADVPN2_MASK 0x007ffff0 | ||
| 81 | #define CONTEXT_BADVPN2_MASK_R4100 0x01fffff0 | ||
| 82 | #define CONTEXT_BADVPN2_SHIFT 4 | ||
| 83 | #define R2K3K_CONTEXT_BADVPN_MASK 0x001ffffc | ||
| 84 | #define R2K3K_CONTEXT_BADVPN_SHIFT 2 | ||
| 85 | #define COP0_PAGEMASK 5 | ||
| 86 | #define PAGEMASK_MASK 0x01ffe000 | ||
| 87 | #define PAGEMASK_SHIFT 13 | ||
| 88 | dpavlin | 14 | #define PAGEMASK_MASK_R4100 0x0007f800 /* TODO: At least VR4131, */ |
| 89 | /* how about others? */ | ||
| 90 | dpavlin | 4 | #define PAGEMASK_SHIFT_R4100 11 |
| 91 | #define COP0_WIRED 6 | ||
| 92 | #define COP0_RESERV7 7 | ||
| 93 | #define COP0_BADVADDR 8 | ||
| 94 | #define COP0_COUNT 9 | ||
| 95 | #define COP0_ENTRYHI 10 | ||
| 96 | /* R4000 ENTRYHI: */ | ||
| 97 | #define ENTRYHI_R_MASK 0xc000000000000000ULL | ||
| 98 | #define ENTRYHI_R_SHIFT 62 | ||
| 99 | #define ENTRYHI_VPN2_MASK_R10K 0x00000fffffffe000ULL | ||
| 100 | #define ENTRYHI_VPN2_MASK 0x000000ffffffe000ULL | ||
| 101 | #define ENTRYHI_VPN2_SHIFT 13 | ||
| 102 | #define ENTRYHI_ASID 0xff | ||
| 103 | #define TLB_G (1 << 12) | ||
| 104 | /* R2000/R3000 ENTRYHI: */ | ||
| 105 | #define R2K3K_ENTRYHI_VPN_MASK 0xfffff000UL | ||
| 106 | #define R2K3K_ENTRYHI_VPN_SHIFT 12 | ||
| 107 | #define R2K3K_ENTRYHI_ASID_MASK 0xfc0 | ||
| 108 | #define R2K3K_ENTRYHI_ASID_SHIFT 6 | ||
| 109 | #define COP0_COMPARE 11 | ||
| 110 | #define COP0_STATUS 12 | ||
| 111 | #define STATUS_CU_MASK 0xf0000000UL /* coprocessor usable bits */ | ||
| 112 | #define STATUS_CU_SHIFT 28 | ||
| 113 | #define STATUS_RP 0x08000000 /* reduced power */ | ||
| 114 | #define STATUS_FR 0x04000000 /* 1=32 float regs, 0=16 */ | ||
| 115 | #define STATUS_RE 0x02000000 /* reverse endian bit */ | ||
| 116 | #define STATUS_BEV 0x00400000 /* boot exception vectors (?) */ | ||
| 117 | /* STATUS_DS: TODO */ | ||
| 118 | #define STATUS_IM_MASK 0xff00 | ||
| 119 | #define STATUS_IM_SHIFT 8 | ||
| 120 | #define STATUS_KX 0x80 | ||
| 121 | #define STATUS_SX 0x40 | ||
| 122 | #define STATUS_UX 0x20 | ||
| 123 | #define STATUS_KSU_MASK 0x18 | ||
| 124 | #define STATUS_KSU_SHIFT 3 | ||
| 125 | #define STATUS_ERL 0x04 | ||
| 126 | #define STATUS_EXL 0x02 | ||
| 127 | #define STATUS_IE 0x01 | ||
| 128 | dpavlin | 24 | #define R5900_STATUS_EDI 0x20000 /* EI/DI instruction enable */ |
| 129 | #define R5900_STATUS_EIE 0x10000 /* Enable Interrupt Enable */ | ||
| 130 | dpavlin | 4 | #define COP0_CAUSE 13 |
| 131 | #define CAUSE_BD 0x80000000UL /* branch delay flag */ | ||
| 132 | #define CAUSE_CE_MASK 0x30000000 /* which coprocessor */ | ||
| 133 | #define CAUSE_CE_SHIFT 28 | ||
| 134 | #define CAUSE_IV 0x00800000UL /* interrupt vector at offset 0x200 instead of 0x180 */ | ||
| 135 | #define CAUSE_WP 0x00400000UL /* watch exception ... */ | ||
| 136 | #define CAUSE_IP_MASK 0xff00 /* interrupt pending */ | ||
| 137 | #define CAUSE_IP_SHIFT 8 | ||
| 138 | #define CAUSE_EXCCODE_MASK 0x7c /* exception code */ | ||
| 139 | #define R2K3K_CAUSE_EXCCODE_MASK 0x3c | ||
| 140 | #define CAUSE_EXCCODE_SHIFT 2 | ||
| 141 | #define COP0_EPC 14 | ||
| 142 | #define COP0_PRID 15 | ||
| 143 | #define COP0_CONFIG 16 | ||
| 144 | #define COP0_LLADDR 17 | ||
| 145 | #define COP0_WATCHLO 18 | ||
| 146 | #define COP0_WATCHHI 19 | ||
| 147 | #define COP0_XCONTEXT 20 | ||
| 148 | #define XCONTEXT_R_MASK 0x180000000ULL | ||
| 149 | #define XCONTEXT_R_SHIFT 31 | ||
| 150 | #define XCONTEXT_BADVPN2_MASK 0x7ffffff0 | ||
| 151 | #define XCONTEXT_BADVPN2_SHIFT 4 | ||
| 152 | #define COP0_FRAMEMASK 21 /* R10000 */ | ||
| 153 | #define COP0_RESERV22 22 | ||
| 154 | #define COP0_DEBUG 23 | ||
| 155 | #define COP0_DEPC 24 | ||
| 156 | #define COP0_PERFCNT 25 | ||
| 157 | #define COP0_ERRCTL 26 | ||
| 158 | #define COP0_CACHEERR 27 | ||
| 159 | #define COP0_TAGDATA_LO 28 | ||
| 160 | #define COP0_TAGDATA_HI 29 | ||
| 161 | #define COP0_ERROREPC 30 | ||
| 162 | #define COP0_DESAVE 31 | ||
| 163 | |||
| 164 | /* Coprocessor 1's registers: */ | ||
| 165 | #define COP1_REVISION 0 | ||
| 166 | #define COP1_REVISION_MIPS3D 0x80000 /* MIPS3D support */ | ||
| 167 | #define COP1_REVISION_PS 0x40000 /* Paired-single support */ | ||
| 168 | #define COP1_REVISION_DOUBLE 0x20000 /* double precision support */ | ||
| 169 | #define COP1_REVISION_SINGLE 0x10000 /* single precision support */ | ||
| 170 | #define COP1_CONTROLSTATUS 31 | ||
| 171 | |||
| 172 | /* CP0's STATUS KSU values: */ | ||
| 173 | #define KSU_KERNEL 0 | ||
| 174 | #define KSU_SUPERVISOR 1 | ||
| 175 | #define KSU_USER 2 | ||
| 176 | |||
| 177 | #define EXCEPTION_NAMES { \ | ||
| 178 | "INT", "MOD", "TLBL", "TLBS", "ADEL", "ADES", "IBE", "DBE", \ | ||
| 179 | "SYS", "BP", "RI", "CPU", "OV", "TR", "VCEI", "FPE", \ | ||
| 180 | "16?", "17?", "C2E", "19?", "20?", "21?", "MDMX", "WATCH", \ | ||
| 181 | "MCHECK", "25?", "26?", "27?", "28?", "29?", "CACHEERR", "VCED" } | ||
| 182 | |||
| 183 | /* CP0's CAUSE exception codes: */ | ||
| 184 | #define EXCEPTION_INT 0 /* Interrupt */ | ||
| 185 | #define EXCEPTION_MOD 1 /* TLB modification exception */ | ||
| 186 | #define EXCEPTION_TLBL 2 /* TLB exception (load or instruction fetch) */ | ||
| 187 | #define EXCEPTION_TLBS 3 /* TLB exception (store) */ | ||
| 188 | #define EXCEPTION_ADEL 4 /* Address Error Exception (load/instr. fetch) */ | ||
| 189 | #define EXCEPTION_ADES 5 /* Address Error Exception (store) */ | ||
| 190 | #define EXCEPTION_IBE 6 /* Bus Error Exception (instruction fetch) */ | ||
| 191 | #define EXCEPTION_DBE 7 /* Bus Error Exception (data: load or store) */ | ||
| 192 | #define EXCEPTION_SYS 8 /* Syscall */ | ||
| 193 | #define EXCEPTION_BP 9 /* Breakpoint */ | ||
| 194 | #define EXCEPTION_RI 10 /* Reserved instruction */ | ||
| 195 | #define EXCEPTION_CPU 11 /* CoProcessor Unusable */ | ||
| 196 | #define EXCEPTION_OV 12 /* Arithmetic Overflow */ | ||
| 197 | #define EXCEPTION_TR 13 /* Trap exception */ | ||
| 198 | #define EXCEPTION_VCEI 14 /* Virtual Coherency Exception, Instruction */ | ||
| 199 | #define EXCEPTION_FPE 15 /* Floating point exception */ | ||
| 200 | dpavlin | 22 | /* 16..17: Available for "implementation dependent use" */ |
| 201 | dpavlin | 4 | #define EXCEPTION_C2E 18 /* MIPS64 C2E (precise coprocessor 2 exception) */ |
| 202 | /* 19..21: Reserved */ | ||
| 203 | #define EXCEPTION_MDMX 22 /* MIPS64 MDMX unusable */ | ||
| 204 | #define EXCEPTION_WATCH 23 /* Reference to WatchHi/WatchLo address */ | ||
| 205 | #define EXCEPTION_MCHECK 24 /* MIPS64 Machine Check */ | ||
| 206 | /* 25..29: Reserved */ | ||
| 207 | #define EXCEPTION_CACHEERR 30 /* MIPS64 Cache Error */ | ||
| 208 | #define EXCEPTION_VCED 31 /* Virtual Coherency Exception, Data */ | ||
| 209 | |||
| 210 | |||
| 211 | #endif /* COP0_H */ | ||
| 212 |
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