/[gxemul]/trunk/src/include/clmpccreg.h
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Contents of /trunk/src/include/clmpccreg.h

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Revision 42 - (show annotations)
Mon Oct 8 16:22:32 2007 UTC (16 years, 6 months ago) by dpavlin
File MIME type: text/plain
File size: 22645 byte(s) 
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $
20070501	Continuing a little on m88k disassembly (control registers,
		more instructions).
		Adding a dummy mvme88k machine mode.
20070502	Re-adding MIPS load/store alignment exceptions.
20070503	Implementing more of the M88K disassembly code.
20070504	Adding disassembly of some more M88K load/store instructions.
		Implementing some relatively simple M88K instructions (br.n,
		xor[.u] imm, and[.u] imm).
20070505	Implementing M88K three-register and, or, xor, and jmp[.n],
		bsr[.n] including function call trace stuff.
		Applying a patch from Bruce M. Simpson which implements the
		SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in
		the yamon PROM emulation.
20070506	Implementing M88K bb0[.n] and bb1[.n], and skeletons for
		ldcr and stcr (although no control regs are implemented yet).
20070509	Found and fixed the bug which caused Linux for QEMU_MIPS to
		stop working in 0.4.5.1: It was a faulty change to the MIPS
		'sc' and 'scd' instructions I made while going through gcc -W
		warnings on 20070428.
20070510	Updating the Linux/QEMU_MIPS section in guestoses.html to
		use mips-test-0.2.tar.gz instead of 0.1.
		A big thank you to Miod Vallat for sending me M88K manuals.
		Implementing more M88K instructions (addu, subu, div[u], mulu,
		ext[u], clr, set, cmp).
20070511	Fixing bugs in the M88K "and" and "and.u" instructions (found
		by comparing against the manual).
		Implementing more M88K instructions (mask[.u], mak, bcnd (auto-
		generated)) and some more control register details.
		Cleanup: Removing the experimental AVR emulation mode and
		corresponding devices; AVR emulation wasn't really meaningful.
		Implementing autogeneration of most M88K loads/stores. The
		rectangle drawing demo (with -O0) for M88K runs :-)
		Beginning on M88K exception handling.
		More M88K instructions: tb0, tb1, rte, sub, jsr[.n].
		Adding some skeleton MVME PROM ("BUG") emulation.
20070512	Fixing a bug in the M88K cmp instruction.
		Adding the M88K lda (scaled register) instruction.
		Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores.
		Removing the unused tick_hz stuff from the machine struct.
		Implementing the M88K xmem instruction. OpenBSD/mvme88k gets
		far enough to display the Copyright banner :-)
		Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1.
		Adding a dev_mvme187, for MVME187-specific devices/registers.
		OpenBSD/mvme88k prints more boot messages. :)
20070515	Continuing on MVME187 emulation (adding more devices, beginning
		on the CMMUs, etc).
		Adding the M88K and.c, xor.c, and or.c instructions, and making
		sure that mul, div, etc cause exceptions if executed when SFD1
		is disabled.
20070517	Continuing on M88K and MVME187 emulation in general; moving
		the CMMU registers to the CPU struct, separating dev_pcc2 from
		dev_mvme187, and beginning on memory_m88k.c (BATC and PATC).
		Fixing a bug in 64-bit (32-bit pairs) M88K fast stores.
		Implementing the clock part of dev_mk48txx.
		Implementing the M88K fstcr and xcr instructions.
		Implementing m88k_cpu_tlbdump().
		Beginning on the implementation of a separate address space
		for M88K .usr loads/stores.
20070520	Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK
		Dnard, and Zaurus machine modes.
		Experimenting with dyntrans to_be_translated read-ahead. It
		seems to give a very small performance increase for MIPS
		emulation, but a large performance degradation for SuperH. Hm.
20070522	Disabling correct SuperH ITLB emulation; it does not seem to be
		necessary in order to let SH4 guest OSes run, and it slows down
		userspace code.
		Implementing "samepage" branches for SuperH emulation, and some
		other minor speed hacks.
20070525	Continuing on M88K memory-related stuff: exceptions, memory
		transaction register contents, etc.
		Implementing the M88K subu.ci instruction.
		Removing the non-working (skeleton) Iyonix machine mode.
		OpenBSD/mvme88k reaches userland :-), starts executing
		/sbin/init's instructions, and issues a few syscalls, before
		crashing.
20070526	Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects
		the correct time-of-day.
		Implementing a generic IRQ controller for the test machines
		(dev_irqc), similar to a proposed patch from Petr Stepan.
		Experimenting some more with translation read-ahead.
		Adding an "expect" script for automated OpenBSD/landisk
		install regression/performance tests.
20070527	Adding a dummy mmEye (SH3) machine mode skeleton.
		FINALLY found the strange M88K bug I have been hunting: I had
		not emulated the SNIP value for exceptions occurring in
		branch delay slots correctly.
		Implementing correct exceptions for 64-bit M88K loads/stores.
		Address to symbol lookups are now disabled when M88K is
		running in usermode (because usermode addresses don't have
		anything to do with supervisor addresses).
20070531	Removing the mmEye machine mode skeleton.
20070604	Some minor code cleanup.
20070605	Moving src/useremul.c into a subdir (src/useremul/), and
		cleaning up some more legacy constructs.
		Adding -Wstrict-aliasing and -fstrict-aliasing detection to
		the configure script.
20070606	Adding a check for broken GCC on Solaris to the configure
		script. (GCC 3.4.3 on Solaris cannot handle static variables
		which are initialized to 0 or NULL. :-/)
		Removing the old (non-working) ARC emulation modes: NEC RD94,
		R94, R96, and R98, and the last traces of Olivetti M700 and
		Deskstation Tyne.
		Removing the non-working skeleton WDSC device (dev_wdsc).
20070607	Thinking about how to use the host's cc + ld at runtime to
		generate native code. (See experiments/native_cc_ld_test.i
		for an example.)
20070608	Adding a program counter sampling timer, which could be useful
		for native code generation experiments.
		The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR
		should always be set, to allow a 5000/200 PROM to boot.
20070609	Moving out breakpoint details from the machine struct into
		a helper struct, and removing the limit on max nr of
		breakpoints.
20070610	Moving out tick functions into a helper struct as well (which
		also gets rid of the max limit).
20070612	FINALLY figured out why Debian/DECstation stopped working when
		translation read-ahead was enabled: in src/memory_rw.c, the
		call to invalidate_code_translation was made also if the
		memory access was an instruction load (if the page was mapped
		as writable); it shouldn't be called in that case.
20070613	Implementing some more MIPS32/64 revision 2 instructions: di,
		ei, ext, dext, dextm, dextu, and ins.
20070614	Implementing an instruction combination for the NetBSD/arm
		idle loop (making the host not use any cpu if NetBSD/arm
		inside the emulator is not using any cpu).
		Increasing the nr of ARM VPH entries from 128 to 384.
20070615	Removing the ENABLE_arch stuff from the configure script, so
		that all included architectures are included in both release
		and development builds.
		Moving memory related helper functions from misc.c to memory.c.
		Adding preliminary instructions for netbooting NetBSD/pmppc to
		guestoses.html; it doesn't work yet, there are weird timeouts.
		Beginning a total rewrite of the userland emulation modes
		(removing all emulation modes, beginning from scratch with
		NetBSD/MIPS and FreeBSD/Alpha only).
20070616	After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was
		only cleared for the last segment when transmitting, not all
		segments), NetBSD/pmppc boots with root-on-nfs without the
		timeouts. Updating guestoses.html.
		Removing the skeleton PSP (Playstation Portable) mode.
		Moving X11-related stuff in the machine struct into a helper
		struct.
		Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION
		macro (which prints a meaningful error message).
		Adding a COMMENT to each machine and device (for automagic
		.index comment generation).
		Doing regression testing for the next release.

==============  RELEASE 0.4.6  ==============
1 /* GXemul: $Id: clmpccreg.h,v 1.1 2007/05/15 12:35:14 debug Exp $ */
2 /* $NetBSD: clmpccreg.h,v 1.3 1999/11/28 12:23:18 scw Exp $ */
3
4 #ifndef __clmpccreg_h
5 #define __clmpccreg_h
6
7 /*-
8 * Copyright (c) 1999 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to The NetBSD Foundation
12 * by Steve C. Woodford.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the NetBSD
25 * Foundation, Inc. and its contributors.
26 * 4. Neither the name of The NetBSD Foundation nor the names of its
27 * contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
31 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
34 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGE.
41 */
42
43 /*
44 * Register definitions for the Cirrus Logic CD2400/CD2401
45 * Four Channel Multi-Protocol Communications Controller.
46 *
47 * The values defined here are based on the August 1993 data book.
48 * At the present time, this driver supports non-DMA async. mode only.
49 */
50
51 /*
52 * Register offsets depend on the level on the chip's BYTESWAP pin.
53 * When BYTESWAP is low, Motorola byte alignment is in effect.
54 * Otherwise, Intel byte alignment is in effect.
55 * The values given here assume BYTESWAP is low. See 'sc_byteswap'
56 * <dev/ic/clmpccvar.h>.
57 */
58
59 /* Number of bytes of FIFO (Rx & Tx) */
60 #define CLMPCC_FIFO_DEPTH 16
61
62 /* Global Registers */
63 #define CLMPCC_REG_GFRCR 0x81 /* Global Firmware Revision Code Register */
64 #define CLMPCC_REG_CAR 0xee /* Channel Access Register */
65
66 /* Option Registers */
67 #define CLMPCC_REG_CMR 0x1b /* Channel Mode Register */
68 #define CLMPCC_REG_COR1 0x10 /* Channel Option Register #1 */
69 #define CLMPCC_REG_COR2 0x17 /* Channel Option Register #2 */
70 #define CLMPCC_REG_COR3 0x16 /* Channel Option Register #3 */
71 #define CLMPCC_REG_COR4 0x15 /* Channel Option Register #4 */
72 #define CLMPCC_REG_COR5 0x14 /* Channel Option Register #5 */
73 #define CLMPCC_REG_COR6 0x18 /* Channel Option Register #6 */
74 #define CLMPCC_REG_COR7 0x07 /* Channel Option Register #7 */
75 #define CLMPCC_REG_SCHR1 0x1f /* Special Character Register #1 */
76 #define CLMPCC_REG_SCHR2 0x1e /* Special Character Register #2 */
77 #define CLMPCC_REG_SCHR3 0x1d /* Special Character Register #3 */
78 #define CLMPCC_REG_SCHR4 0x1c /* Special Character Register #4 */
79 #define CLMPCC_REG_SCRl 0x23 /* Special Character Range (low) */
80 #define CLMPCC_REG_SCRh 0x22 /* Special Character Range (high) */
81 #define CLMPCC_REG_LNXT 0x2e /* LNext Character */
82 #define CLMPCC_REG_RFAR1 0x1f /* Receive Frame Address Register #1 */
83 #define CLMPCC_REG_RFAR2 0x1e /* Receive Frame Address Register #2 */
84 #define CLMPCC_REG_RFAR3 0x1d /* Receive Frame Address Register #3 */
85 #define CLMPCC_REG_RFAR4 0x1c /* Receive Frame Address Register #4 */
86 #define CLMPCC_REG_CPSR 0xd6 /* CRC Polynomial Select Register */
87
88 /* Bit Rate and Clock Option Registers */
89 #define CLMPCC_REG_RBPR 0xcb /* Receive Baud Rate Period Register */
90 #define CLMPCC_REG_RCOR 0xc8 /* Receive Clock Options Register */
91 #define CLMPCC_REG_TBPR 0xc3 /* Transmit Baud Rate Period Register */
92 #define CLMPCC_REG_TCOR 0xc0 /* Transmit Clock Options Register */
93
94 /* Channel Command and Status Registers */
95 #define CLMPCC_REG_CCR 0x13 /* Channel Command Register */
96 #define CLMPCC_REG_STCR 0x12 /* Special Transmit Command Register */
97 #define CLMPCC_REG_CSR 0x1a /* Channel Status Register */
98 #define CLMPCC_REG_MSVR 0xde /* Modem Signal Value Register */
99 #define CLMPCC_REG_MSVR_RTS 0xde /* Modem Signal Value Register (RTS) */
100 #define CLMPCC_REG_MSVR_DTR 0xdf /* Modem Signal Value Register (DTR) */
101
102 /* Interrupt Registers */
103 #define CLMPCC_REG_LIVR 0x09 /* Local Interrupt Vector Register */
104 #define CLMPCC_REG_IER 0x11 /* Interrupt Enable Register */
105 #define CLMPCC_REG_LICR 0x26 /* Local Interrupting Channel Register */
106 #define CLMPCC_REG_STK 0xe2 /* Stack Register */
107
108 /* Receive Interrupt Registers */
109 #define CLMPCC_REG_RPILR 0xe1 /* Receive Priority Interrupt Level Reg */
110 #define CLMPCC_REG_RIR 0xed /* Receive Interrupt Register */
111 #define CLMPCC_REG_RISR 0x88 /* Receive Interrupt Status Reg (16-bits) */
112 #define CLMPCC_REG_RISRl 0x89 /* Receive Interrupt Status Reg (low) */
113 #define CLMPCC_REG_RISRh 0x88 /* Receive Interrupt Status Reg (high) */
114 #define CLMPCC_REG_RFOC 0x30 /* Receive FIFO Output Count */
115 #define CLMPCC_REG_RDR 0xf8 /* Receive Data Register */
116 #define CLMPCC_REG_REOIR 0x84 /* Receive End of Interrupt Register */
117
118 /* Transmit Interrupt Registers */
119 #define CLMPCC_REG_TPILR 0xe0 /* Transmit Priority Interrupt Level Reg */
120 #define CLMPCC_REG_TIR 0xec /* Transmit Interrupt Register */
121 #define CLMPCC_REG_TISR 0x8a /* Transmit Interrupt Status Register */
122 #define CLMPCC_REG_TFTC 0x80 /* Transmit FIFO Transfer Count */
123 #define CLMPCC_REG_TDR 0xf8 /* Transmit Data Register */
124 #define CLMPCC_REG_TEOIR 0x85 /* Transmit End of Interrupt Register */
125
126 /* Modem Interrupt Registers */
127 #define CLMPCC_REG_MPILR 0xe3 /* Modem Priority Interrupt Level Reg */
128 #define CLMPCC_REG_MIR 0xef /* Modem Interrupt Register */
129 #define CLMPCC_REG_MISR 0x8b /* Modem (/Timer) Interrupt Status Reg */
130 #define CLMPCC_REG_MEOIR 0x86 /* Modem End of Interrupt Register */
131
132 /* DMA Registers */
133 #define CLMPCC_REG_DMR 0xf6 /* DMA Mode Register (write only) */
134 #define CLMPCC_REG_BERCNT 0x8e /* Bus Error Retry Count */
135 #define CLMPCC_REG_DMABSTS 0x19 /* DMA Buffer Status */
136
137 /* DMA Receive Registers */
138 #define CLMPCC_REG_ARBADRL 0x42 /* A Receive Buffer Address Lower (word) */
139 #define CLMPCC_REG_ARBADRU 0x40 /* A Receive Buffer Address Upper (word) */
140 #define CLMPCC_REG_BRBADRL 0x46 /* B Receive Buffer Address Lower (word) */
141 #define CLMPCC_REG_BRBADRU 0x44 /* B Receive Buffer Address Upper (16bit) */
142 #define CLMPCC_REG_ARBCNT 0x4a /* A Receive Buffer Byte Count (word) */
143 #define CLMPCC_REG_BRBCNT 0x48 /* B Receive Buffer Byte Count (word) */
144 #define CLMPCC_REG_ARBSTS 0x4f /* A Receive Buffer Status */
145 #define CLMPCC_REG_BRBSTS 0x4e /* B Receive Buffer Status */
146 #define CLMPCC_REG_RCBADRL 0x3e /* Receive Current Buff Addr Lower (word) */
147 #define CLMPCC_REG_RCBADRU 0x3c /* Receive Current Buff Addr Upper (word) */
148
149 /* DMA Transmit Registers */
150 #define CLMPCC_REG_ATBADRL 0x52 /* A Transmit Buffer Address Lower (word) */
151 #define CLMPCC_REG_ATBADRU 0x50 /* A Transmit Buffer Address Upper (word) */
152 #define CLMPCC_REG_BTBADRL 0x56 /* B Transmit Buffer Address Lower (word) */
153 #define CLMPCC_REG_BTBADRU 0x54 /* B Transmit Buffer Address Upper (word) */
154 #define CLMPCC_REG_ATBCNT 0x5a /* A Transmit Buffer Byte Count (word) */
155 #define CLMPCC_REG_BTBCNT 0x58 /* B Transmit Buffer Byte Count (word) */
156 #define CLMPCC_REG_ATBSTS 0x5f /* A Transmit Buffer Status */
157 #define CLMPCC_REG_BTBSTS 0x5e /* B Transmit Buffer Status */
158 #define CLMPCC_REG_TCBADRL 0x3a /* Transmit Current Buf Addr Lower (word) */
159 #define CLMPCC_REG_TCBADRU 0x38 /* Transmit Current Buf Addr Upper (word) */
160
161 /* Timer Registers */
162 #define CLMPCC_REG_TPR 0xda /* Timer Period Register */
163 #define CLMPCC_REG_RTPR 0x24 /* Receive Timeout Period Register (word) */
164 #define CLMPCC_REG_RTPRl 0x25 /* Receive Timeout Period Register (low) */
165 #define CLMPCC_REG_RTPRh 0x24 /* Receive Timeout Period Register (high) */
166 #define CLMPCC_REG_GT1 0x2a /* General Timer 1 (word) */
167 #define CLMPCC_REG_GT1l 0x2b /* General Timer 1 (low) */
168 #define CLMPCC_REG_GT1h 0x2a /* General Timer 1 (high) */
169 #define CLMPCC_REG_GT2 0x29 /* General Timer 2 */
170 #define CLMPCC_REG_TTR 0x29 /* Transmit Timer Register */
171
172
173 /* Channel Access Register */
174 #define CLMPCC_CAR_MASK 0x03 /* Channel bit mask */
175
176 /* Channel Mode Register */
177 #define CLMPCC_CMR_RX_INT (0 << 7) /* Rx using interrupts */
178 #define CLMPCC_CMR_RX_DMA (1 << 7) /* Rx using DMA */
179 #define CLMPCC_CMR_TX_INT (0 << 6) /* Tx using interrupts */
180 #define CLMPCC_CMR_TX_DMA (1 << 6) /* Tx using DMA */
181 #define CLMPCC_CMR_HDLC 0x00 /* Select HDLC mode */
182 #define CLMPCC_CMR_BISYNC 0x01 /* Select Bisync mode */
183 #define CLMPCC_CMR_ASYNC 0x02 /* Select async mode */
184 #define CLMPCC_CMR_X21 0x03 /* Select X.21 mode */
185
186 /* Channel Option Register #1 (Async options) */
187 #define CLMPCC_COR1_EVEN_PARITY (0 << 7) /* Even parity */
188 #define CLMPCC_COR1_ODD_PARITY (1 << 7) /* Odd parity */
189 #define CLMPCC_COR1_NO_PARITY (0 << 5) /* No parity */
190 #define CLMPCC_COR1_FORCE_PAR (1 << 5) /* Force parity */
191 #define CLMPCC_COR1_NORM_PARITY (2 << 5) /* Normal parity */
192 #define CLMPCC_COR1_CHECK_PAR (0 << 4) /* Check parity */
193 #define CLMPCC_COR1_IGNORE_PAR (1 << 4) /* Ignore parity */
194 #define CLMPCC_COR1_CHAR_5BITS 0x04 /* 5 bits per character */
195 #define CLMPCC_COR1_CHAR_6BITS 0x05 /* 6 bits per character */
196 #define CLMPCC_COR1_CHAR_7BITS 0x06 /* 7 bits per character */
197 #define CLMPCC_COR1_CHAR_8BITS 0x07 /* 8 bits per character */
198
199 /* Channel Option Register #2 (Async options) */
200 #define CLMPCC_COR2_IXM (1 << 7) /* Implied XON mode */
201 #define CLMPCC_COR2_TxIBE (1 << 6) /* Transmit In-Band Flow Control */
202 #define CLMPCC_COR2_ETC (1 << 5) /* Embedded Tx Command Enable */
203 #define CLMPCC_COR2_RLM (1 << 3) /* Remote Loopback Mode */
204 #define CLMPCC_COR2_RtsAO (1 << 2) /* RTS Automatic Output Enable */
205 #define CLMPCC_COR2_CtsAE (1 << 1) /* CTS Automatic Enable */
206 #define CLMPCC_COR2_DsrAE (1 << 1) /* DSR Automatic Enable */
207
208 /* Embedded transmit commands */
209 #define CLMPCC_ETC_MAGIC 0x00 /* Introduces a command */
210 #define CLMPCC_ETC_SEND_BREAK 0x81 /* Send a BREAK character */
211 #define CLMPCC_ETC_DELAY 0x82 /* Insert a delay */
212 #define CLMPCC_ETC_STOP_BREAK 0x83 /* Stop sending BREAK */
213
214 /* Channel Option Register #3 (Async options) */
215 #define CLMPCC_COR3_ESCDE (1 << 7) /* Ext Special Char Detect Enab */
216 #define CLMPCC_COR3_RngDE (1 << 6) /* Range Detect Enable */
217 #define CLMPCC_COR3_FCT (1 << 5) /* Flow Ctrl Transparency Mode */
218 #define CLMPCC_COR3_SCDE (1 << 4) /* Special Character Detection */
219 #define CLMPCC_COR3_SpIstp (1 << 3) /* Special Character I Strip */
220 #define CLMPCC_COR3_STOP_1 0x02 /* 1 Stop Bit */
221 #define CLMPCC_COR3_STOP_1_5 0x03 /* 1.5 Stop Bits */
222 #define CLMPCC_COR3_STOP_2 0x04 /* 2 Stop Bits */
223
224 /* Channel Option Register #4 */
225 #define CLMPCC_COR4_DSRzd (1 << 7) /* Detect 1->0 transition on DSR */
226 #define CLMPCC_COR4_CDzd (1 << 6) /* Detect 1->0 transition on CD */
227 #define CLMPCC_COR4_CTSzd (1 << 5) /* Detect 1->0 transition on CTS */
228 #define CLMPCC_COR4_FIFO_MASK 0x0f /* FIFO Threshold bits */
229 #define CLMPCC_COR4_FIFO_LOW 1
230 #define CLMPCC_COR4_FIFO_MED 4
231 #define CLMPCC_COR4_FIFO_HIGH 8
232
233 /* Channel Option Register #5 */
234 #define CLMPCC_COR5_DSRod (1 << 7) /* Detect 0->1 transition on DSR */
235 #define CLMPCC_COR5_CDod (1 << 6) /* Detect 0->1 transition on CD */
236 #define CLMPCC_COR5_CTSod (1 << 5) /* Detect 0->1 transition on CTS */
237 #define CLMPCC_COR5_FLOW_MASK 0x0f /* Rx Flow Control FIFO Threshold */
238 #define CLMPCC_COR5_FLOW_NORM 8
239
240 /* Channel Option Register #6 (Async options) */
241 #define CLMPCC_COR6_RX_CRNL 0x00 /* No special action on CR or NL */
242 #define CLMPCC_COR6_BRK_EXCEPT (0 << 3) /* Exception interrupt on BREAK */
243 #define CLMPCC_COR6_BRK_2_NULL (1 << 3) /* Translate BREAK to NULL char */
244 #define CLMPCC_COR6_BRK_DISCARD (3 << 3) /* Discard BREAK characters */
245 #define CLMPCC_COR6_PF_EXCEPT 0x00 /* Exception irq on parity/frame */
246 #define CLMPCC_COR6_PF_2_NULL 0x01 /* Translate parity/frame to NULL */
247 #define CLMPCC_COR6_PF_IGNORE 0x02 /* Ignore error */
248 #define CLMPCC_COR6_PF_DISCARD 0x03 /* Discard character */
249 #define CLMPCC_COR6_PF_TRANS 0x05 /* Translate to FF NULL + char */
250
251 /* Channel Option Register #7 (Async options) */
252 #define CLMPCC_COR7_ISTRIP (1 << 7) /* Strip MSB */
253 #define CLMPCC_COR7_LNE (1 << 6) /* Enable LNext Option */
254 #define CLMPCC_COR7_FCERR (1 << 5) /* Flow Control on Error Char */
255 #define CLMPCC_COR7_TX_CRNL 0x00 /* No special action on NL or CR */
256
257 /* Receive Clock Options Register */
258 #define CLMPCC_RCOR_CLK(x) (x)
259 #define CLMPCC_RCOR_TLVAL (1 << 7) /* Transmit Line Value */
260 #define CLMPCC_RCOR_DPLL_ENABLE (1 << 5) /* Phase Locked Loop Enable */
261 #define CLMPCC_RCOR_DPLL_NRZ (0 << 3) /* PLL runs in NRZ mode */
262 #define CLMPCC_RCOR_DPLL_NRZI (1 << 3) /* PLL runs in NRZI mode */
263 #define CLMPCC_RCOR_DPLL_MAN (2 << 3) /* PLL runs in Manchester mode */
264 #define CLMPCC_RCOR_CLK_0 0x0 /* Rx Clock Source 'Clk0' */
265 #define CLMPCC_RCOR_CLK_1 0x1 /* Rx Clock Source 'Clk1' */
266 #define CLMPCC_RCOR_CLK_2 0x2 /* Rx Clock Source 'Clk2' */
267 #define CLMPCC_RCOR_CLK_3 0x3 /* Rx Clock Source 'Clk3' */
268 #define CLMPCC_RCOR_CLK_4 0x4 /* Rx Clock Source 'Clk4' */
269 #define CLMPCC_RCOR_CLK_EXT 0x6 /* Rx Clock Source 'External' */
270
271 /* Transmit Clock Options Register */
272 #define CLMPCC_TCOR_CLK(x) ((x) << 5)
273 #define CLMPCC_TCOR_CLK_0 (0 << 5) /* Tx Clock Source 'Clk0' */
274 #define CLMPCC_TCOR_CLK_1 (1 << 5) /* Tx Clock Source 'Clk1' */
275 #define CLMPCC_TCOR_CLK_2 (2 << 5) /* Tx Clock Source 'Clk2' */
276 #define CLMPCC_TCOR_CLK_3 (3 << 5) /* Tx Clock Source 'Clk3' */
277 #define CLMPCC_TCOR_CLK_4 (4 << 5) /* Tx Clock Source 'Clk4' */
278 #define CLMPCC_TCOR_CLK_EXT (6 << 5) /* Tx Clock Source 'External' */
279 #define CLMPCC_TCOR_CLK_RX (7 << 5) /* Tx Clock Source 'Same as Rx' */
280 #define CLMPCC_TCOR_EXT_1X (1 << 3) /* Times 1 External Clock */
281 #define CLMPCC_TCOR_LOCAL_LOOP (1 << 1) /* Enable Local Loopback */
282
283 /* Special Transmit Command Register */
284 #define CLMPCC_STCR_SSPC(n) ((n) & 0x7) /* Send special character 'n' */
285 #define CLMPCC_STCR_SND_SPC (1 << 3) /* Initiate send special char */
286 #define CLMPCC_STCR_APPEND_COMP (1 << 5) /* Append complete (Async DMA) */
287 #define CLMPCC_STCR_ABORT_TX (1 << 6) /* Abort Tx (HDLC Mode only) */
288
289 /* Channel Command Register */
290 #define CLMPCC_CCR_T0_CLEAR 0x40 /* Type 0: Clear Channel */
291 #define CLMPCC_CCR_T0_INIT 0x20 /* Type 0: Initialise Channel */
292 #define CLMPCC_CCR_T0_RESET_ALL 0x10 /* Type 0: Reset All */
293 #define CLMPCC_CCR_T0_TX_EN 0x08 /* Type 0: Transmitter Enable */
294 #define CLMPCC_CCR_T0_TX_DIS 0x04 /* Type 0: Transmitter Disable */
295 #define CLMPCC_CCR_T0_RX_EN 0x02 /* Type 0: Receiver Enable */
296 #define CLMPCC_CCR_T0_RX_DIS 0x01 /* Type 0: Receiver Disable */
297 #define CLMPCC_CCR_T1_CLR_TMR1 0xc0 /* Type 1: Clear Timer 1 */
298 #define CLMPCC_CCR_T1_CLR_TMR2 0xa0 /* Type 1: Clear Timer 5 */
299 #define CLMPCC_CCR_T1_CLR_RECV 0x90 /* Type 1: Clear Receiver */
300
301 /* Channel Status Register (Async Mode) */
302 #define CLMPCC_CSR_RX_ENABLED (1 << 7) /* Receiver Enabled */
303 #define CLMPCC_CSR_RX_FLOW_OFF (1 << 6) /* Receive Flow Off */
304 #define CLMPCC_CSR_RX_FLOW_ON (1 << 5) /* Receive Flow On */
305 #define CLMPCC_CSR_TX_ENABLED (1 << 3) /* Transmitter Enabled */
306 #define CLMPCC_CSR_TX_FLOW_OFF (1 << 2) /* Transmit Flow Off */
307 #define CLMPCC_CSR_TX_FLOW_ON (1 << 1) /* Transmit Flow On */
308
309 /* Modem Signal Value Register */
310 #define CLMPCC_MSVR_DSR (1 << 7) /* Current State of DSR Input */
311 #define CLMPCC_MSVR_CD (1 << 6) /* Current State of CD Input */
312 #define CLMPCC_MSVR_CTS (1 << 5) /* Current State of CTS Input */
313 #define CLMPCC_MSVR_DTR_OPT (1 << 4) /* DTR Option Select */
314 #define CLMPCC_MSVR_PORT_ID (1 << 2) /* Device Type (2400 / 2401) */
315 #define CLMPCC_MSVR_DTR (1 << 1) /* Current State of DTR Output */
316 #define CLMPCC_MSVR_RTS (1 << 0) /* Current State of RTS Output */
317
318 /* Local Interrupt Vector Register */
319 #define CLMPCC_LIVR_TYPE_MASK 0x03 /* Type of Interrupt */
320 #define CLMPCC_LIVR_EXCEPTION 0x0 /* Exception (DMA Completion) */
321 #define CLMPCC_LIVR_MODEM 0x1 /* Modem Signal Change */
322 #define CLMPCC_LIVR_TX 0x2 /* Transmit Data Interrupt */
323 #define CLMPCC_LIVR_RX 0x3 /* Receive Data Interrupt */
324
325 /* Interrupt Enable Register */
326 #define CLMPCC_IER_MODEM (1 << 7) /* Modem Pin Change Detect */
327 #define CLMPCC_IER_RET (1 << 5) /* Receive Exception Timeout */
328 #define CLMPCC_IER_RX_FIFO (1 << 3) /* Rx FIFO Threshold Reached */
329 #define CLMPCC_IER_TIMER (1 << 2) /* General Timer(s) Timeout */
330 #define CLMPCC_IER_TX_EMPTY (1 << 1) /* Tx Empty */
331 #define CLMPCC_IER_TX_FIFO (1 << 0) /* Tx FIFO Threshold Reached */
332
333 /* Local Interrupting Channel Register */
334 #define CLMPCC_LICR_MASK 0x0c /* Mask for channel number */
335 #define CLMPCC_LICR_CHAN(v) (((v) & CLMPCC_LICR_MASK) >> 2)
336
337 /* Receive Interrupt Register */
338 #define CLMPCC_RIR_REN (1 << 7) /* Receive Enable */
339 #define CLMPCC_RIR_RACT (1 << 6) /* Receive Active */
340 #define CLMPCC_RIR_REOI (1 << 5) /* Receive End of Interrupt */
341 #define CLMPCC_RIR_RCVT_MASK 0x0c
342 #define CLMPCC_RIR_RCN_MASK 0x03
343
344 /* Receive Interrupt Status Register, Low (Async option) */
345 #define CLMPCC_RISR_TIMEOUT (1 << 7) /* Rx FIFO Empty and Timeout */
346 #define CLMPCC_RISR_OVERRUN (1 << 3) /* Rx Overrun Error */
347 #define CLMPCC_RISR_PARITY (1 << 2) /* Rx Parity Error */
348 #define CLMPCC_RISR_FRAMING (1 << 1) /* Rx Framing Error */
349 #define CLMPCC_RISR_BREAK (1 << 0) /* BREAK Detected */
350
351 /* Receive FIFO Counter Register */
352 #define CLMPCC_RFOC_MASK 0x1f /* Mask for valid bits */
353
354 /* Receive End of Interrupt Register */
355 #define CLMPCC_REOIR_TERMBUFF (1 << 7) /* Terminate Current DMA Buffer */
356 #define CLMPCC_REOIR_DIS_EX_CHR (1 << 6) /* Discard Exception Char (DMA) */
357 #define CLMPCC_REOIR_TMR2_SYNC (1 << 5) /* Set Timer 2 in Sync Mode */
358 #define CLMPCC_REOIR_TMR1_SYNC (1 << 4) /* Set Timer 1 in Sync Mode */
359 #define CLMPCC_REOIR_NO_TRANS (1 << 3) /* No Transfer of Data */
360
361 /* Transmit Interrupt Register */
362 #define CLMPCC_TIR_TEN (1 << 7) /* Transmit Enable */
363 #define CLMPCC_TIR_TACT (1 << 6) /* Transmit Active */
364 #define CLMPCC_TIR_TEOI (1 << 5) /* Transmit End of Interrupt */
365 #define CLMPCC_TIR_TCVT_MASK 0x0c
366 #define CLMPCC_TIR_TCN_MASK 0x03
367
368 /* Transmit Interrupt Status Register (Async option) */
369 #define CLMPCC_TISR_BERR (1 << 7) /* Bus Error (DMA) */
370 #define CLMPCC_TISR_EOF (1 << 6) /* Transmit End of Frame (DMA) */
371 #define CLMPCC_TISR_EOB (1 << 5) /* Transmit End of Buffer (DMA) */
372 #define CLMPCC_TISR_UNDERRUN (1 << 4) /* Transmit Underrun (sync only) */
373 #define CLMPCC_TISR_BUFF_ID (1 << 3) /* Buffer that has exception */
374 #define CLMPCC_TISR_TX_EMPTY (1 << 1) /* Transmitter Empty */
375 #define CLMPCC_TISR_TX_FIFO (1 << 0) /* Transmit FIFO Below Threshold */
376
377 /* Transmit FIFO Transfer Count Register */
378 #define CLMPCC_TFTC_MASK 0x1f /* Mask for valid bits */
379
380 /* Transmit End of Interrupt Register */
381 #define CLMPCC_TEOIR_TERMBUFF (1 << 7) /* Terminate Current DMA Buffer */
382 #define CLMPCC_TEOIR_END_OF_FRM (1 << 6) /* End of Frame (sync mode) */
383 #define CLMPCC_TEOIR_TMR2_SYNC (1 << 5) /* Set Timer 2 in Sync Mode */
384 #define CLMPCC_TEOIR_TMR1_SYNC (1 << 4) /* Set Timer 1 in Sync Mode */
385 #define CLMPCC_TEOIR_NO_TRANS (1 << 3) /* No Transfer of Data */
386
387 /* Modem Interrupt Register */
388 #define CLMPCC_MIR_MEN (1 << 7) /* Modem Enable */
389 #define CLMPCC_MIR_MACT (1 << 6) /* Modem Active */
390 #define CLMPCC_MIR_MEOI (1 << 5) /* Modem End of Interrupt */
391 #define CLMPCC_MIR_MCVT_MASK 0x0c
392 #define CLMPCC_MIR_MCN_MASK 0x03
393
394 /* Modem/Timer Interrupt Status Register */
395 #define CLMPCC_MISR_DSR (1 << 7) /* DSR Changed State */
396 #define CLMPCC_MISR_CD (1 << 6) /* CD Changed State */
397 #define CLMPCC_MISR_CTS (1 << 5) /* CTS Changed State */
398 #define CLMPCC_MISR_TMR2 (1 << 1) /* Timer 2 Timed Out */
399 #define CLMPCC_MISR_TMR1 (1 << 0) /* Timer 1 Timed Out */
400
401 /* Modem End of Interrupt Register */
402 #define CLMPCC_MEOIR_TMR2_SYNC (1 << 5) /* Set Timer 2 in Sync Mode */
403 #define CLMPCC_MEOIR_TMR1_SYNC (1 << 4) /* Set Timer 1 in Sync Mode */
404
405 /* Default value for CLMPCC_REG_RTPRl */
406 #define CLMPCC_RTPR_DEFAULT 2 /* 2mS timeout period */
407
408 /*
409 * Return a value for the Receive Timer Prescaler register
410 * for a given clock rate and number of milliseconds.
411 * The minimum recommended value for this register is 0x0a.
412 */
413 #define CLMPCC_MSEC_TO_TPR(c,m) (((((c)/2048)/(1000/(m))) > 0x0a) ? \
414 (((c)/2048)/(1000/(m))) : 0x0a)
415
416 #endif /* __clmpccreg_h */
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