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#ifndef BUS_PCI_H |
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#define BUS_PCI_H |
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|
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/* |
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* Copyright (C) 2004-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: bus_pci.h,v 1.30 2006/08/12 19:32:20 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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#include "pcireg.h" |
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|
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struct machine; |
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struct memory; |
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|
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struct pci_device; |
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|
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|
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#ifndef BUS_PCI_C |
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|
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struct pci_data; |
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|
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#else |
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|
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struct pci_data { |
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/* IRQ nr of the controller itself. */ |
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int irq_nr; |
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|
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/* |
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* Default I/O port, memory, and irq bases for PCI and legacy ISA |
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* devices, and the base address for actual (emulated) devices: |
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* |
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* pci_portbase etc are what is stored in the device configuration |
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* registers. This address + pci_actual_{io,mem}_offset is where the |
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* emulated device should be registered. |
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*/ |
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uint64_t pci_actual_io_offset; |
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uint64_t pci_actual_mem_offset; |
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|
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uint64_t pci_portbase; |
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uint64_t pci_membase; |
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int pci_irqbase; |
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|
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uint64_t isa_portbase; |
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uint64_t isa_membase; |
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int isa_irqbase; |
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|
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/* Current base when allocating space for PCI devices: */ |
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uint64_t cur_pci_portbase; |
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uint64_t cur_pci_membase; |
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|
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/* Current register access: */ |
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int cur_bus, cur_device, cur_func, cur_reg; |
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int last_was_write_ffffffff; |
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|
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struct pci_device *first_device; |
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}; |
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|
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#define PCI_CFG_MEM_SIZE 0x100 |
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|
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struct pci_device { |
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/* Pointer to the next PCI device on this bus: */ |
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struct pci_device *next; |
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|
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/* Pointer back to the bus this device is connected to: */ |
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struct pci_data *pcibus; |
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|
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/* Short device name, and bus/device/function value: */ |
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char *name; |
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int bus, device, function; |
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|
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/* Configuration memory: */ |
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unsigned char cfg_mem[PCI_CFG_MEM_SIZE]; |
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unsigned char cfg_mem_size[PCI_CFG_MEM_SIZE]; |
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|
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/* Used when setting up the configuration registers: */ |
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int cur_mapreg_offset; |
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|
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/* Function to handle device-specific cfg register writes: */ |
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int (*cfg_reg_write)(struct pci_device *pd, |
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int reg, uint32_t value); |
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void *extra; |
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}; |
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|
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#define PCIINIT(name) void pciinit_ ## name(struct machine *machine, \ |
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struct memory *mem, struct pci_device *pd) |
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|
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/* |
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* Store little-endian config data in the pci_data struct's cfg_mem[] |
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* or cfg_mem_size[], respectively. |
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*/ |
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#define PCI_SET_DATA(ofs,value) { \ |
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pd->cfg_mem[(ofs)] = (value) & 255; \ |
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pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255; \ |
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pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255; \ |
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pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255; \ |
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} |
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#define PCI_SET_DATA_SIZE(ofs,value) { \ |
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pd->cfg_mem_size[(ofs)] = (value) & 255; \ |
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pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255; \ |
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pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255; \ |
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pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255; \ |
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} |
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|
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#endif |
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|
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#define BUS_PCI_ADDR 0xcf8 |
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#define BUS_PCI_DATA 0xcfc |
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|
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|
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/* |
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* bus_pci.c: |
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*/ |
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|
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/* Run-time access: */ |
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void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg); |
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void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, |
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int bus, int device, int function, int reg); |
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void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, |
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uint64_t *data, int len, int writeflag); |
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|
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/* Initialization: */ |
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struct pci_data *bus_pci_init(struct machine *machine, int irq_nr, |
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uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, |
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uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase, |
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uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase); |
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|
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/* Add a PCI device to a PCI bus: */ |
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void bus_pci_add(struct machine *machine, struct pci_data *pci_data, |
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struct memory *mem, int bus, int device, int function, |
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const char *name); |
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|
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|
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#endif /* BUS_PCI_H */ |