/[gxemul]/trunk/src/include/bus_pci.h
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revision 14 by dpavlin, Mon Oct 8 16:18:51 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 1  Line 1 
1  #ifndef PCI_BUS_H  #ifndef BUS_PCI_H
2  #define PCI_BUS_H  #define BUS_PCI_H
3    
4  /*  /*
5   *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: bus_pci.h,v 1.17 2005/10/03 01:07:48 debug Exp $   *  $Id: bus_pci.h,v 1.29 2006/02/18 13:15:21 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
35    #include "pcireg.h"
36    
37  struct machine;  struct machine;
38  struct memory;  struct memory;
39    
40  struct pci_device {  struct pci_device;
         int             bus, device, function;  
   
         void            (*init)(struct machine *, struct memory *mem);  
         uint32_t        (*read_register)(int reg);  
41    
42          struct pci_device *next;  #ifndef BUS_PCI_C
43  };  struct pci_data;
44    #else
45    
46  struct pci_data {  struct pci_data {
47            /*  IRQ nr of the controller itself.  */
48          int             irq_nr;          int             irq_nr;
49          uint32_t        pci_addr;  
50            /*
51             *  Default I/O port, memory, and irq bases for PCI and legacy ISA
52             *  devices, and the base address for actual (emulated) devices:
53             *
54             *  pci_portbase etc are what is stored in the device configuration
55             *  registers. This address + pci_actual_{io,mem}_offset is where the
56             *  emulated device should be registered.
57             */
58            uint64_t        pci_actual_io_offset;
59            uint64_t        pci_actual_mem_offset;
60    
61            uint64_t        pci_portbase;
62            uint64_t        pci_membase;
63            int             pci_irqbase;
64    
65            uint64_t        isa_portbase;
66            uint64_t        isa_membase;
67            int             isa_irqbase;
68    
69            /*  Current base when allocating space for PCI devices:  */
70            uint64_t        cur_pci_portbase;
71            uint64_t        cur_pci_membase;
72    
73            /*  Current register access:  */
74            int             cur_bus, cur_device, cur_func, cur_reg;
75          int             last_was_write_ffffffff;          int             last_was_write_ffffffff;
76    
77          struct pci_device *first_device;          struct pci_device *first_device;
78  };  };
79    
80  #define BUS_PCI_ADDR    0xcf8  #define PCI_CFG_MEM_SIZE        0x100
 #define BUS_PCI_DATA    0xcfc  
81    
82    struct pci_device {
83            struct pci_device       *next;
84            struct pci_data         *pcibus;
85            char                    *name;
86            int                     bus, device, function;
87            unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];
88            unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];
89            int                     cur_mapreg_offset;
90    };
91    
92  #include "pcireg.h"  #define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \
93            struct memory *mem, struct pci_device *pd)
94    
95    /*
96     *  Store little-endian config data in the pci_data struct's cfg_mem[]
97     *  or cfg_mem_size[], respectively.
98     */
99    #define PCI_SET_DATA(ofs,value) {                                       \
100            pd->cfg_mem[(ofs)]     = (value) & 255;                         \
101            pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255;                  \
102            pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255;                 \
103            pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255;                 \
104            }
105    #define PCI_SET_DATA_SIZE(ofs,value)    {                               \
106            pd->cfg_mem_size[(ofs)]     = (value) & 255;                    \
107            pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255;             \
108            pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255;            \
109            pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255;            \
110            }
111    
112    #endif
113    
114  /*  bus_pci.c:  */  #define BUS_PCI_ADDR    0xcf8
115  int bus_pci_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, uint64_t *data, int writeflag, struct pci_data *pci_data);  #define BUS_PCI_DATA    0xcfc
 void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem,  
         int bus, int device, int function,  
         void (*init)(struct machine *, struct memory *),  
         uint32_t (*read_register)(int reg));  
 struct pci_data *bus_pci_init(int irq_nr);  
116    
117    
118  /*  /*
119   *  Individual devices:   *  bus_pci.c:
120   */   */
121    
122  /*  ali_m1543:  */  /*  Run-time access:  */
123  uint32_t pci_ali_m1543_rr(int reg);  void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg);
124  void pci_ali_m1543_init(struct machine *, struct memory *mem);  void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
125  uint32_t pci_ali_m5229_rr(int reg);          int bus, int device, int function, int reg);
126  void pci_ali_m5229_init(struct machine *, struct memory *mem);  void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
127            uint64_t *data, int len, int writeflag);
128  /*  ahc:  */  
129  uint32_t pci_ahc_rr(int reg);  /*  Initialization:  */
130  void pci_ahc_init(struct machine *, struct memory *mem);  struct pci_data *bus_pci_init(struct machine *machine, int irq_nr,
131            uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
132  /*  dec21030:  */          uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase,
133  uint32_t pci_dec21030_rr(int reg);          uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase);
134  void pci_dec21030_init(struct machine *, struct memory *mem);  void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
135            struct memory *mem, int bus, int device, int function,
136  /*  dec21143:  */          const char *name);
 uint32_t pci_dec21143_rr(int reg);  
 void pci_dec21143_init(struct machine *, struct memory *mem);  
   
 /*  igsfb:  */  
 uint32_t pci_igsfb_rr(int reg);  
 void pci_igsfb_init(struct machine *, struct memory *mem);  
   
 /*  s3_virge:  */  
 uint32_t pci_s3_virge_rr(int reg);  
 void pci_s3_virge_init(struct machine *, struct memory *mem);  
   
 /*  symphony_83c553:  */  
 uint32_t pci_symphony_82c105_rr(int reg);  
 void pci_symphony_82c105_init(struct machine *, struct memory *mem);  
 uint32_t pci_symphony_83c553_rr(int reg);  
 void pci_symphony_83c553_init(struct machine *, struct memory *mem);  
   
 /*  vt82c586:  */  
 uint32_t pci_vt82c586_isa_rr(int reg);  
 void pci_vt82c586_isa_init(struct machine *, struct memory *mem);  
 uint32_t pci_vt82c586_ide_rr(int reg);  
 void pci_vt82c586_ide_init(struct machine *, struct memory *mem);  
137    
138    
139  #endif  /*  PCI_BUS_H  */  #endif  /*  BUS_PCI_H  */
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