/[gxemul]/trunk/src/include/bus_pci.h
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revision 4 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 30 by dpavlin, Mon Oct 8 16:20:40 2007 UTC
# Line 1  Line 1 
1  #ifndef PCI_BUS_H  #ifndef BUS_PCI_H
2  #define PCI_BUS_H  #define BUS_PCI_H
3    
4  /*  /*
5   *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: bus_pci.h,v 1.12 2005/03/18 23:20:52 debug Exp $   *  $Id: bus_pci.h,v 1.30 2006/08/12 19:32:20 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
35    #include "pcireg.h"
36    
37  struct machine;  struct machine;
38  struct memory;  struct memory;
39    
40  struct pci_device {  struct pci_device;
         int             bus, device, function;  
41    
         void            (*init)(struct machine *, struct memory *mem);  
         uint32_t        (*read_register)(int reg);  
42    
43          struct pci_device *next;  #ifndef BUS_PCI_C
44  };  
45    struct pci_data;
46    
47    #else
48    
49  struct pci_data {  struct pci_data {
50            /*  IRQ nr of the controller itself.  */
51          int             irq_nr;          int             irq_nr;
52          uint32_t        pci_addr;  
53            /*
54             *  Default I/O port, memory, and irq bases for PCI and legacy ISA
55             *  devices, and the base address for actual (emulated) devices:
56             *
57             *  pci_portbase etc are what is stored in the device configuration
58             *  registers. This address + pci_actual_{io,mem}_offset is where the
59             *  emulated device should be registered.
60             */
61            uint64_t        pci_actual_io_offset;
62            uint64_t        pci_actual_mem_offset;
63    
64            uint64_t        pci_portbase;
65            uint64_t        pci_membase;
66            int             pci_irqbase;
67    
68            uint64_t        isa_portbase;
69            uint64_t        isa_membase;
70            int             isa_irqbase;
71    
72            /*  Current base when allocating space for PCI devices:  */
73            uint64_t        cur_pci_portbase;
74            uint64_t        cur_pci_membase;
75    
76            /*  Current register access:  */
77            int             cur_bus, cur_device, cur_func, cur_reg;
78          int             last_was_write_ffffffff;          int             last_was_write_ffffffff;
79    
80          struct pci_device *first_device;          struct pci_device *first_device;
81  };  };
82    
83  #define BUS_PCI_ADDR    0xcf8  #define PCI_CFG_MEM_SIZE        0x100
 #define BUS_PCI_DATA    0xcfc  
84    
85    struct pci_device {
86            /*  Pointer to the next PCI device on this bus:  */
87            struct pci_device       *next;
88    
89  #include "pcireg.h"          /*  Pointer back to the bus this device is connected to:  */
90            struct pci_data         *pcibus;
91    
92            /*  Short device name, and bus/device/function value:  */
93            char                    *name;
94            int                     bus, device, function;
95    
96            /*  Configuration memory:  */
97            unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];
98            unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];
99    
100            /*  Used when setting up the configuration registers:  */
101            int                     cur_mapreg_offset;
102    
103            /*  Function to handle device-specific cfg register writes:  */
104            int                     (*cfg_reg_write)(struct pci_device *pd,
105                                        int reg, uint32_t value);
106            void                    *extra;
107    };
108    
109    #define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \
110            struct memory *mem, struct pci_device *pd)
111    
112  /*  bus_pci.c:  */  /*
113  int bus_pci_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, uint64_t *data, int writeflag, struct pci_data *pci_data);   *  Store little-endian config data in the pci_data struct's cfg_mem[]
114  void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem,   *  or cfg_mem_size[], respectively.
115          int bus, int device, int function,   */
116          void (*init)(struct machine *, struct memory *),  #define PCI_SET_DATA(ofs,value) {                                       \
117          uint32_t (*read_register)(int reg));          pd->cfg_mem[(ofs)]     = (value) & 255;                         \
118  struct pci_data *bus_pci_init(int irq_nr);          pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255;                  \
119            pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255;                 \
120            pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255;                 \
121            }
122    #define PCI_SET_DATA_SIZE(ofs,value)    {                               \
123            pd->cfg_mem_size[(ofs)]     = (value) & 255;                    \
124            pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255;             \
125            pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255;            \
126            pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255;            \
127            }
128    
129    #endif
130    
131    #define BUS_PCI_ADDR    0xcf8
132    #define BUS_PCI_DATA    0xcfc
133    
134    
135  /*  /*
136   *  Individual devices:   *  bus_pci.c:
137   */   */
138    
139  /*  ahc:  */  /*  Run-time access:  */
140  uint32_t pci_ahc_rr(int reg);  void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg);
141  void pci_ahc_init(struct machine *, struct memory *mem);  void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
142            int bus, int device, int function, int reg);
143  /*  dec21030:  */  void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
144  uint32_t pci_dec21030_rr(int reg);          uint64_t *data, int len, int writeflag);
145  void pci_dec21030_init(struct machine *, struct memory *mem);  
146    /*  Initialization:  */
147  /*  dec21143:  */  struct pci_data *bus_pci_init(struct machine *machine, int irq_nr,
148  uint32_t pci_dec21143_rr(int reg);          uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
149  void pci_dec21143_init(struct machine *, struct memory *mem);          uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase,
150            uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase);
151  /*  vt82c586:  */  
152  uint32_t pci_vt82c586_isa_rr(int reg);  /*  Add a PCI device to a PCI bus:  */
153  void pci_vt82c586_isa_init(struct machine *, struct memory *mem);  void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
154  uint32_t pci_vt82c586_ide_rr(int reg);          struct memory *mem, int bus, int device, int function,
155  void pci_vt82c586_ide_init(struct machine *, struct memory *mem);          const char *name);
156    
157    
158  #endif  /*  PCI_BUS_H  */  #endif  /*  BUS_PCI_H  */
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