/[gxemul]/trunk/src/include/bus_pci.h
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revision 4 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 1  Line 1 
1  #ifndef PCI_BUS_H  #ifndef BUS_PCI_H
2  #define PCI_BUS_H  #define BUS_PCI_H
3    
4  /*  /*
5   *  Copyright (C) 2004-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: bus_pci.h,v 1.12 2005/03/18 23:20:52 debug Exp $   *  $Id: bus_pci.h,v 1.33 2006/12/30 13:31:00 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
35    #include "pcireg.h"
36    
37  struct machine;  struct machine;
38  struct memory;  struct memory;
39    
40  struct pci_device {  struct pci_device;
         int             bus, device, function;  
41    
         void            (*init)(struct machine *, struct memory *mem);  
         uint32_t        (*read_register)(int reg);  
42    
43          struct pci_device *next;  #ifndef BUS_PCI_C
44  };  
45    struct pci_data;
46    
47    #else
48    
49  struct pci_data {  struct pci_data {
50          int             irq_nr;          /*
51          uint32_t        pci_addr;           *  IRQ paths:
52             *
53             *  irq_path            Path of the controller itself.
54             *  irq_path_isa        Path base of ISA interrupts.
55             *  irq_path_pci        Path base of PCI interrupts.
56             */
57            char            *irq_path;
58            char            *irq_path_isa;
59            char            *irq_path_pci;
60    
61            /*
62             *  Default I/O port, memory, and irq bases for PCI and legacy ISA
63             *  devices, and the base address for actual (emulated) devices:
64             *
65             *  pci_portbase etc are what is stored in the device configuration
66             *  registers. This address + pci_actual_{io,mem}_offset is where the
67             *  emulated device should be registered.
68             */
69            uint64_t        pci_actual_io_offset;
70            uint64_t        pci_actual_mem_offset;
71    
72            uint64_t        pci_portbase;
73            uint64_t        pci_membase;
74    
75            uint64_t        isa_portbase;
76            uint64_t        isa_membase;
77    
78            /*  Current base when allocating space for PCI devices:  */
79            uint64_t        cur_pci_portbase;
80            uint64_t        cur_pci_membase;
81    
82            /*  Current register access:  */
83            int             cur_bus, cur_device, cur_func, cur_reg;
84          int             last_was_write_ffffffff;          int             last_was_write_ffffffff;
85    
86          struct pci_device *first_device;          struct pci_device *first_device;
87  };  };
88    
89  #define BUS_PCI_ADDR    0xcf8  #define PCI_CFG_MEM_SIZE        0x100
90  #define BUS_PCI_DATA    0xcfc  
91    struct pci_device {
92            /*  Pointer to the next PCI device on this bus:  */
93            struct pci_device       *next;
94    
95            /*  Pointer back to the bus this device is connected to:  */
96            struct pci_data         *pcibus;
97    
98  #include "pcireg.h"          /*  Short device name, and bus/device/function value:  */
99            char                    *name;
100            int                     bus, device, function;
101    
102            /*  Configuration memory:  */
103            unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];
104            unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];
105    
106            /*  Used when setting up the configuration registers:  */
107            int                     cur_mapreg_offset;
108    
109            /*  Function to handle device-specific cfg register writes:  */
110            int                     (*cfg_reg_write)(struct pci_device *pd,
111                                        int reg, uint32_t value);
112            void                    *extra;
113    };
114    
115    #define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \
116            struct memory *mem, struct pci_device *pd)
117    
118  /*  bus_pci.c:  */  /*
119  int bus_pci_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, uint64_t *data, int writeflag, struct pci_data *pci_data);   *  Store little-endian config data in the pci_data struct's cfg_mem[]
120  void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem,   *  or cfg_mem_size[], respectively.
121          int bus, int device, int function,   */
122          void (*init)(struct machine *, struct memory *),  #define PCI_SET_DATA(ofs,value) {                                       \
123          uint32_t (*read_register)(int reg));          pd->cfg_mem[(ofs)]     = (value) & 255;                         \
124  struct pci_data *bus_pci_init(int irq_nr);          pd->cfg_mem[(ofs) + 1] = ((value) >> 8) & 255;                  \
125            pd->cfg_mem[(ofs) + 2] = ((value) >> 16) & 255;                 \
126            pd->cfg_mem[(ofs) + 3] = ((value) >> 24) & 255;                 \
127            }
128    #define PCI_SET_DATA_SIZE(ofs,value)    {                               \
129            pd->cfg_mem_size[(ofs)]     = (value) & 255;                    \
130            pd->cfg_mem_size[(ofs) + 1] = ((value) >> 8) & 255;             \
131            pd->cfg_mem_size[(ofs) + 2] = ((value) >> 16) & 255;            \
132            pd->cfg_mem_size[(ofs) + 3] = ((value) >> 24) & 255;            \
133            }
134    
135    #endif
136    
137    #define BUS_PCI_ADDR    0xcf8
138    #define BUS_PCI_DATA    0xcfc
139    
140    
141  /*  /*
142   *  Individual devices:   *  bus_pci.c:
143   */   */
144    
145  /*  ahc:  */  /*  Run-time access:  */
146  uint32_t pci_ahc_rr(int reg);  void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg);
147  void pci_ahc_init(struct machine *, struct memory *mem);  void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
148            int bus, int device, int function, int reg);
149  /*  dec21030:  */  void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
150  uint32_t pci_dec21030_rr(int reg);          uint64_t *data, int len, int writeflag);
151  void pci_dec21030_init(struct machine *, struct memory *mem);  
152    /*  Initialization:  */
153  /*  dec21143:  */  struct pci_data *bus_pci_init(struct machine *machine, char *irq_path,
154  uint32_t pci_dec21143_rr(int reg);          uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
155  void pci_dec21143_init(struct machine *, struct memory *mem);          uint64_t pci_portbase, uint64_t pci_membase, char *pci_irqbase,
156            uint64_t isa_portbase, uint64_t isa_membase, char *isa_irqbase);
157  /*  vt82c586:  */  
158  uint32_t pci_vt82c586_isa_rr(int reg);  /*  Add a PCI device to a PCI bus:  */
159  void pci_vt82c586_isa_init(struct machine *, struct memory *mem);  void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
160  uint32_t pci_vt82c586_ide_rr(int reg);          struct memory *mem, int bus, int device, int function,
161  void pci_vt82c586_ide_init(struct machine *, struct memory *mem);          const char *name);
162    
163    
164  #endif  /*  PCI_BUS_H  */  #endif  /*  BUS_PCI_H  */
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