/[gxemul]/trunk/src/include/bus_pci.h
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revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 2  Line 2 
2  #define BUS_PCI_H  #define BUS_PCI_H
3    
4  /*  /*
5   *  Copyright (C) 2004-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2004-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: bus_pci.h,v 1.29 2006/02/18 13:15:21 debug Exp $   *  $Id: bus_pci.h,v 1.33 2006/12/30 13:31:00 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 39  struct memory; Line 39  struct memory;
39    
40  struct pci_device;  struct pci_device;
41    
42    
43  #ifndef BUS_PCI_C  #ifndef BUS_PCI_C
44    
45  struct pci_data;  struct pci_data;
46    
47  #else  #else
48    
49  struct pci_data {  struct pci_data {
50          /*  IRQ nr of the controller itself.  */          /*
51          int             irq_nr;           *  IRQ paths:
52             *
53             *  irq_path            Path of the controller itself.
54             *  irq_path_isa        Path base of ISA interrupts.
55             *  irq_path_pci        Path base of PCI interrupts.
56             */
57            char            *irq_path;
58            char            *irq_path_isa;
59            char            *irq_path_pci;
60    
61          /*          /*
62           *  Default I/O port, memory, and irq bases for PCI and legacy ISA           *  Default I/O port, memory, and irq bases for PCI and legacy ISA
# Line 60  struct pci_data { Line 71  struct pci_data {
71    
72          uint64_t        pci_portbase;          uint64_t        pci_portbase;
73          uint64_t        pci_membase;          uint64_t        pci_membase;
         int             pci_irqbase;  
74    
75          uint64_t        isa_portbase;          uint64_t        isa_portbase;
76          uint64_t        isa_membase;          uint64_t        isa_membase;
         int             isa_irqbase;  
77    
78          /*  Current base when allocating space for PCI devices:  */          /*  Current base when allocating space for PCI devices:  */
79          uint64_t        cur_pci_portbase;          uint64_t        cur_pci_portbase;
# Line 80  struct pci_data { Line 89  struct pci_data {
89  #define PCI_CFG_MEM_SIZE        0x100  #define PCI_CFG_MEM_SIZE        0x100
90    
91  struct pci_device {  struct pci_device {
92            /*  Pointer to the next PCI device on this bus:  */
93          struct pci_device       *next;          struct pci_device       *next;
94    
95            /*  Pointer back to the bus this device is connected to:  */
96          struct pci_data         *pcibus;          struct pci_data         *pcibus;
97    
98            /*  Short device name, and bus/device/function value:  */
99          char                    *name;          char                    *name;
100          int                     bus, device, function;          int                     bus, device, function;
101    
102            /*  Configuration memory:  */
103          unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];          unsigned char           cfg_mem[PCI_CFG_MEM_SIZE];
104          unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];          unsigned char           cfg_mem_size[PCI_CFG_MEM_SIZE];
105    
106            /*  Used when setting up the configuration registers:  */
107          int                     cur_mapreg_offset;          int                     cur_mapreg_offset;
108    
109            /*  Function to handle device-specific cfg register writes:  */
110            int                     (*cfg_reg_write)(struct pci_device *pd,
111                                        int reg, uint32_t value);
112            void                    *extra;
113  };  };
114    
115  #define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \  #define PCIINIT(name)   void pciinit_ ## name(struct machine *machine,  \
# Line 127  void bus_pci_data_access(struct cpu *cpu Line 150  void bus_pci_data_access(struct cpu *cpu
150          uint64_t *data, int len, int writeflag);          uint64_t *data, int len, int writeflag);
151    
152  /*  Initialization:  */  /*  Initialization:  */
153  struct pci_data *bus_pci_init(struct machine *machine, int irq_nr,  struct pci_data *bus_pci_init(struct machine *machine, char *irq_path,
154          uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,          uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
155          uint64_t pci_portbase, uint64_t pci_membase, int pci_irqbase,          uint64_t pci_portbase, uint64_t pci_membase, char *pci_irqbase,
156          uint64_t isa_portbase, uint64_t isa_membase, int isa_irqbase);          uint64_t isa_portbase, uint64_t isa_membase, char *isa_irqbase);
157    
158    /*  Add a PCI device to a PCI bus:  */
159  void bus_pci_add(struct machine *machine, struct pci_data *pci_data,  void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
160          struct memory *mem, int bus, int device, int function,          struct memory *mem, int bus, int device, int function,
161          const char *name);          const char *name);
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