/[gxemul]/trunk/src/include/bireg.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Contents of /trunk/src/include/bireg.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 4 - (show annotations)
Mon Oct 8 16:18:00 2007 UTC (16 years, 5 months ago) by dpavlin
File MIME type: text/plain
File size: 11283 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.707 2005/04/27 16:37:33 debug Exp $
20050408	Some minor updates to the wdc. Linux now doesn't complain
		anymore if a disk is non-present.
20050409	Various minor fixes (a bintrans bug, and some other things).
		The wdc seems to work with Playstation2 emulation, but there
		is a _long_ annoying delay when disks are detected.
		Fixing a really important bintrans bug (when devices and RAM
		are mixed within 4KB pages), which was triggered with
		NetBSD/playstation2 kernels.
20050410	Adding a dummy dev_ps2_ether (just so that NetBSD doesn't
		complain as much during bootup).
		Symbols starting with '$' are now ignored.
		Renaming dev_ps2_ohci.c to dev_ohci.c, etc.
20050411	Moving the bintrans-cache-isolation check from cpu_mips.c to
		cpu_mips_coproc.c. (I thought this would give a speedup, but
		it's not noticable.)
		Better playstation2 sbus interrupt code.
		Skip ahead many ticks if the count register is read manually.
		(This increases the speed of delay-loops that simply read
		the count register.)
20050412	Updates to the playstation2 timer/interrupt code.
		Some other minor updates.
20050413	NetBSD/cobalt runs from a disk image :-) including userland;
		updating the documentation on how to install NetBSD/cobalt
		using NetBSD/pmax (!).
		Some minor bintrans updates (no real speed improvement) and
		other minor updates (playstation2 now uses the -o options).
20050414	Adding a dummy x86 (and AMD64) mode.
20050415	Adding some (32-bit and 16-bit) x86 instructions.
		Adding some initial support for non-SCSI, non-IDE floppy
		images. (The x86 mode can boot from these, more or less.)
		Moving the devices/ and include/ directories to src/devices/
		and src/include/, respectively.
20050416	Continuing on the x86 stuff. (Adding pc_bios.c and some simple
		support for software interrupts in 16-bit mode.)
20050417	Ripping out most of the x86 instruction decoding stuff, trying
		to rewrite it in a cleaner way.
		Disabling some of the least working CPU families in the
		configure script (sparc, x86, alpha, hppa), so that they are
		not enabled by default.
20050418	Trying to fix the bug which caused problems when turning on
		and off bintrans interactively, by flushing the bintrans cache
		whenever bintrans is manually (re)enabled.
20050419	Adding the 'lswi' ppc instruction.
		Minor updates to the x86 instruction decoding.
20050420	Renaming x86 register name indices from R_xx to X86_R_xx (this
		makes building on Tru64 nicer).
20050422	Adding a check for duplicate MIPS TLB entries on tlbwr/tlbwi.
20050427	Adding screenshots to guestoses.html.
		Some minor fixes and testing for the next release.

==============  RELEASE 0.3.2  ==============


1 /* gxemul: $Id: bireg.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */
2 /* $NetBSD: bireg.h,v 1.7 2000/07/06 17:47:02 ragge Exp $ */
3
4 #ifndef BIREG_H
5 #define BIREG_H
6 /*
7 * Copyright (c) 1988 Regents of the University of California.
8 * All rights reserved.
9 *
10 * This code is derived from software contributed to Berkeley by
11 * Chris Torek.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. All advertising materials mentioning features or use of this software
22 * must display the following acknowledgement:
23 * This product includes software developed by the University of
24 * California, Berkeley and its contributors.
25 * 4. Neither the name of the University nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * SUCH DAMAGE.
40 *
41 * @(#)bireg.h 7.3 (Berkeley) 6/28/90
42 */
43
44 /*
45 * VAXBI node definitions.
46 */
47
48 /*
49 * BI node addresses
50 */
51 #define BI_NODESIZE 0x2000 /* Size of one BI node */
52 #define BI_NODE(node) (BI_NODESIZE * (node))
53 #define BI_BASE(bi,nod) ((0x20000000 + (bi) * 0x2000000) + BI_NODE(nod))
54 #define MAXNBI 16 /* Spec says there can be 16 anyway */
55 #define NNODEBI 16 /* 16 nodes per BI */
56
57 #define BI_PROBE 0x80000 /* CPU on 8200, NBIA on 8800 */
58 /*
59 * BI nodes all start with BI interface registers (those on the BIIC chip).
60 * These are followed with interface-specific registers.
61 *
62 * NB: This structure does NOT include the four GPRs (not anymore!)
63 *
64 * 990712: The structs not used anymore due to conversion to bus.h.
65 */
66 #ifdef notdef
67 struct biiregs {
68 u_short bi_dtype; /* device type */
69 u_short bi_revs; /* revisions */
70 u_long bi_csr; /* control and status register */
71 u_long bi_ber; /* bus error register */
72 u_long bi_eintrcsr; /* error interrupt control register */
73 u_long bi_intrdes; /* interrupt destination register */
74 /* the rest are not required for all nodes */
75 u_long bi_ipintrmsk; /* IP interrupt mask register */
76 u_long bi_fipsdes; /* Force-Bit IPINTR/STOP destination reg */
77 u_long bi_ipintrsrc; /* IPINTR source register */
78 u_long bi_sadr; /* starting address register */
79 u_long bi_eadr; /* ending address register */
80 u_long bi_bcicsr; /* BCI control and status register */
81 u_long bi_wstat; /* write status register */
82 u_long bi_fipscmd; /* Force-Bit IPINTR/STOP command reg */
83 u_long bi_xxx1[3]; /* unused */
84 u_long bi_uintrcsr; /* user interface interrupt control reg */
85 u_long bi_xxx2[43]; /* unused */
86 /* although these are on the BIIC, their interpretation varies */
87 /* u_long bi_gpr[4]; */ /* general purpose registers */
88 };
89
90 /*
91 * A generic BI node.
92 */
93 struct bi_node {
94 struct biiregs biic; /* interface */
95 u_long bi_xxx[1988]; /* pad to 8K */
96 };
97
98 /*
99 * A cpu node.
100 */
101 struct bi_cpu {
102 struct biiregs biic; /* interface chip */
103 u_long bi_gpr[4]; /* gprs (unused) */
104 u_long bi_sosr; /* slave only status register */
105 u_long bi_xxx[63]; /* pad */
106 u_long bi_rxcd; /* receive console data register */
107 };
108 #endif
109
110 #define BIREG_DTYPE 0x00
111 #define BIREG_VAXBICSR 0x04
112 #define BIREG_BER 0x08
113 #define BIREG_EINTRCSR 0x0c
114 #define BIREG_INTRDES 0x10
115 #define BIREG_IPINTRMSK 0x14
116 #define BIREG_FIPSDES 0x18
117 #define BIREG_IPINTRSRC 0x1c
118 #define BIREG_SADR 0x20
119 #define BIREG_EADR 0x24
120 #define BIREG_BCICSR 0x28
121 #define BIREG_WSTAT 0x2c
122 #define BIREG_FIPSCMD 0x30
123 #define BIREG_UINTRCSR 0x40
124
125 /* device types */
126 #define BIDT_MS820 0x0001 /* MS820 memory board */
127 #define BIDT_DRB32 0x0101 /* DRB32 (MFA) Supercomputer gateway */
128 #define BIDT_DWBUA 0x0102 /* DWBUA Unibus adapter */
129 #define BIDT_KLESI 0x0103 /* KLESI-B (DWBLA) adapter */
130 #define BIDT_HSB70 0x4104 /* HSB70 */
131 #define BIDT_KA820 0x0105 /* KA820 cpu */
132 #define BIDT_DB88 0x0106 /* DB88 (NBI) adapter */
133 #define BIDT_DWMBA 0x2107 /* XMI-BI (XBI) adapter */
134 #define BIDT_DWMBB 0x0107 /* XMI-BI (XBI) adapter */
135 #define BIDT_CIBCA 0x0108 /* Computer Interconnect adapter */
136 #define BIDT_DMB32 0x0109 /* DMB32 (COMB) adapter */
137 #define BIDT_BAA 0x010a /* BAA */
138 #define BIDT_CIBCI 0x010b /* Computer Interconnect adapter (old) */
139 #define BIDT_DEBNT 0x410b /* (AIE_TK70) Ethernet+TK50/TBK70 */
140 #define BIDT_KA800 0x010c /* KA800 (ACP) slave processor */
141 #define BIDT_KFBTA 0x410d /* RD/RX disk controller */
142 #define BIDT_KDB50 0x010e /* KDB50 (BDA) disk controller */
143 #define BIDT_DEBNK 0x410e /* (AIE_TK) BI Ethernet (Lance) + TK50 */
144 #define BIDT_DEBNA 0x410f /* (AIE) BI Ethernet (Lance) adapter */
145 #define BIDT_DEBNI 0x0118 /* (XNA) BI Ethernet adapter */
146
147
148 /* bits in bi_csr */
149 #define BICSR_IREV(x) ((u_char)((x) >> 24)) /* VAXBI interface rev */
150 #define BICSR_TYPE(x) ((u_char)((x) >> 16)) /* BIIC type */
151 #define BICSR_HES 0x8000 /* hard error summary */
152 #define BICSR_SES 0x4000 /* soft error summary */
153 #define BICSR_INIT 0x2000 /* initialise node */
154 #define BICSR_BROKE 0x1000 /* broke */
155 #define BICSR_STS 0x0800 /* self test status */
156 #define BICSR_NRST 0x0400 /* node reset */
157 #define BICSR_UWP 0x0100 /* unlock write pending */
158 #define BICSR_HEIE 0x0080 /* hard error interrupt enable */
159 #define BICSR_SEIE 0x0040 /* soft error interrupt enable */
160 #define BICSR_ARB_MASK 0x0030 /* mask to get arbitration codes */
161 #define BICSR_ARB_NONE 0x0030 /* no arbitration */
162 #define BICSR_ARB_LOG 0x0020 /* low priority */
163 #define BICSR_ARB_HIGH 0x0010 /* high priority */
164 #define BICSR_ARB_RR 0x0000 /* round robin */
165 #define BICSR_NODEMASK 0x000f /* node ID */
166
167 #define BICSR_BITS \
168 "\20\20HES\17SES\16INIT\15BROKE\14STS\13NRST\11UWP\10HEIE\7SEIE"
169
170 /* bits in bi_ber */
171 #define BIBER_MBZ 0x8000fff0
172 #define BIBER_NMR 0x40000000 /* no ack to multi-responder command */
173 #define BIBER_MTCE 0x20000000 /* master transmit check error */
174 #define BIBER_CTE 0x10000000 /* control transmit error */
175 #define BIBER_MPE 0x08000000 /* master parity error */
176 #define BIBER_ISE 0x04000000 /* interlock sequence error */
177 #define BIBER_TDF 0x02000000 /* transmitter during fault */
178 #define BIBER_IVE 0x01000000 /* ident vector error */
179 #define BIBER_CPE 0x00800000 /* command parity error */
180 #define BIBER_SPE 0x00400000 /* slave parity error */
181 #define BIBER_RDS 0x00200000 /* read data substitute */
182 #define BIBER_RTO 0x00100000 /* retry timeout */
183 #define BIBER_STO 0x00080000 /* stall timeout */
184 #define BIBER_BTO 0x00040000 /* bus timeout */
185 #define BIBER_NEX 0x00020000 /* nonexistent address */
186 #define BIBER_ICE 0x00010000 /* illegal confirmation error */
187 #define BIBER_UPEN 0x00000008 /* user parity enable */
188 #define BIBER_IPE 0x00000004 /* ID parity error */
189 #define BIBER_CRD 0x00000002 /* corrected read data */
190 #define BIBER_NPE 0x00000001 /* null bus parity error */
191 #define BIBER_HARD 0x4fff0000
192
193 #define BIBER_BITS \
194 "\20\37NMR\36MTCE\35CTE\34MPE\33ISE\32TDF\31IVE\30CPE\
195 \27SPE\26RDS\25RTO\24STO\23BTO\22NEX\21ICE\4UPEN\3IPE\2CRD\1NPE"
196
197 /* bits in bi_eintrcsr */
198 #define BIEIC_INTRAB 0x01000000 /* interrupt abort */
199 #define BIEIC_INTRC 0x00800000 /* interrupt complete */
200 #define BIEIC_INTRSENT 0x00200000 /* interrupt command sent */
201 #define BIEIC_INTRFORCE 0x00100000 /* interrupt force */
202 #define BIEIC_LEVELMASK 0x000f0000 /* mask for interrupt levels */
203 #define BIEIC_IPL17 0x00080000 /* ipl 0x17 */
204 #define BIEIC_IPL16 0x00040000 /* ipl 0x16 */
205 #define BIEIC_IPL15 0x00020000 /* ipl 0x15 */
206 #define BIEIC_IPL14 0x00010000 /* ipl 0x14 */
207 #define BIEIC_VECMASK 0x00003ffc /* vector mask for error intr */
208
209 /* bits in bi_intrdes */
210 #define BIDEST_MASK 0x0000ffff /* one bit per node to be intr'ed */
211
212 /* bits in bi_ipintrmsk */
213 #define BIIPINTR_MASK 0xffff0000 /* one per node to allow to ipintr */
214
215 /* bits in bi_fipsdes */
216 #define BIFIPSD_MASK 0x0000ffff
217
218 /* bits in bi_ipintrsrc */
219 #define BIIPSRC_MASK 0xffff0000
220
221 /* sadr and eadr are simple addresses */
222
223 /* bits in bi_bcicsr */
224 #define BCI_BURSTEN 0x00020000 /* burst mode enable */
225 #define BCI_IPSTOP_FRC 0x00010000 /* ipintr/stop force */
226 #define BCI_MCASTEN 0x00008000 /* multicast space enable */
227 #define BCI_BCASTEN 0x00004000 /* broadcast enable */
228 #define BCI_STOPEN 0x00002000 /* stop enable */
229 #define BCI_RSRVDEN 0x00001000 /* reserved enable */
230 #define BCI_IDENTEN 0x00000800 /* ident enable */
231 #define BCI_INVALEN 0x00000400 /* inval enable */
232 #define BCI_WINVEN 0x00000200 /* write invalidate enable */
233 #define BCI_UINTEN 0x00000100 /* user interface csr space enable */
234 #define BCI_BIICEN 0x00000080 /* BIIC csr space enable */
235 #define BCI_INTEN 0x00000040 /* interrupt enable */
236 #define BCI_IPINTEN 0x00000020 /* ipintr enable */
237 #define BCI_PIPEEN 0x00000010 /* pipeline NXT enable */
238 #define BCI_RTOEVEN 0x00000008 /* read timeout EV enable */
239
240 #define BCI_BITS \
241 "\20\22BURSTEN\21IPSTOP_FRC\20MCASTEN\
242 \17BCASTEN\16STOPEN\15RSRVDEN\14IDENTEN\13INVALEN\12WINVEN\11UINTEN\
243 \10BIICEN\7INTEN\6IPINTEN\5PIPEEN\4RTOEVEN"
244
245 /* bits in bi_wstat */
246 #define BIW_GPR3 0x80000000 /* gpr 3 was written */
247 #define BIW_GPR2 0x40000000 /* gpr 2 was written */
248 #define BIW_GPR1 0x20000000 /* gpr 1 was written */
249 #define BIW_GPR0 0x10000000 /* gpr 0 was written */
250
251 /* bits in force-bit ipintr/stop command register */
252 #define BIFIPSC_CMDMASK 0x0000f000 /* command */
253 #define BIFIPSC_MIDEN 0x00000800 /* master ID enable */
254
255 /* bits in bi_uintcsr */
256 #define BIUI_INTAB 0xf0000000 /* interrupt abort level */
257 #define BIUI_INTC 0x0f000000 /* interrupt complete bits */
258 #define BIUI_SENT 0x00f00000 /* interrupt sent bits */
259 #define BIUI_FORCE 0x000f0000 /* force interrupt level */
260 #define BIUI_EVECEN 0x00008000 /* external vector enable */
261 #define BIUI_VEC 0x00003ffc /* interrupt vector */
262
263 /* tell if a bi device is a slave (hence has SOSR) */
264 #define BIDT_ISSLAVE(x) (((x) & 0x7f00) == 0)
265
266 /* bits in bi_sosr */
267 #define BISOSR_MEMSIZE 0x1ffc0000 /* memory size */
268 #define BISOSR_BROKE 0x00001000 /* broke */
269
270 /* bits in bi_rxcd */
271 #define BIRXCD_BUSY2 0x80000000 /* busy 2 */
272 #define BIRXCD_NODE2 0x0f000000 /* node id 2 */
273 #define BIRXCD_CHAR2 0x00ff0000 /* character 2 */
274 #define BIRXCD_BUSY1 0x00008000 /* busy 1 */
275 #define BIRXCD_NODE1 0x00000f00 /* node id 1 */
276 #define BIRXCD_CHAR1 0x000000ff /* character 1 */
277
278 #endif

  ViewVC Help
Powered by ViewVC 1.1.26