/[gxemul]/trunk/src/include/armreg.h
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Revision 24 - (show annotations)
Mon Oct 8 16:19:56 2007 UTC (12 years ago) by dpavlin
File MIME type: text/plain
File size: 13624 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1256 2006/06/23 20:43:44 debug Exp $
20060219	Various minor updates. Removing the old MIPS16 skeleton code,
		because it will need to be rewritten for dyntrans anyway.
20060220-22	Removing the non-working dyntrans backend support.
		Continuing on the 64-bit dyntrans virtual memory generalization.
20060223	More work on the 64-bit vm generalization.
20060225	Beginning on MIPS dyntrans load/store instructions.
		Minor PPC updates (64-bit load/store, etc).
		Fixes for the variable-instruction-length framework, some
		minor AVR updates (a simple Hello World program works!).
		Beginning on a skeleton for automatically generating documen-
		tation (for devices etc.).
20060226	PPC updates (adding some more 64-bit instructions, etc).
		AVR updates (more instructions).
		FINALLY found and fixed the zs bug, making NetBSD/macppc
		accept the serial console.
20060301	Adding more AVR instructions.
20060304	Continuing on AVR-related stuff. Beginning on a framework for
		cycle-accurate device emulation. Adding an experimental "PAL
		TV" device (just a dummy so far).
20060305	Adding more AVR instructions.
		Adding a dummy epcom serial controller (for TS7200 emulation).
20060310	Removing the emul() command from configuration files, so only
		net() and machine() are supported.
		Minor progress on the MIPS dyntrans rewrite.
20060311	Continuing on the MIPS dyntrans rewrite (adding more
		instructions, etc).
20060315	Adding more instructions (sllv, srav, srlv, bgtz[l], blez[l],
		beql, bnel, slti[u], various loads and stores).
20060316	Removing the ALWAYS_SIGNEXTEND_32 option, since it was rarely
		used.
		Adding more MIPS dyntrans instructions, and fixing bugs.
20060318	Implementing fast loads/stores for MIPS dyntrans (big/little
		endian, 32-bit and 64-bit modes).
20060320	Making MIPS dyntrans the default configure option; use
		"--enable-oldmips" to use the old bintrans system.
		Adding MIPS dyntrans dmult[u]; minor updates.
20060322	Continuing... adding some more instructions.
		Adding a simple skeleton for demangling C++ "_ZN" symbols.
20060323	Moving src/debugger.c into a new directory (src/debugger/).
20060324	Fixing the hack used to load PPC ELFs (useful for relocated
		Linux/ppc kernels), and adding a dummy G3 machine mode.
20060325-26	Beginning to experiment with GDB remote serial protocol
		connections; adding a -G command line option for selecting
		which TCP port to listen to.
20060330	Beginning a major cleanup to replace things like "0x%016llx"
		with more correct "0x%016"PRIx64, etc.
		Continuing on the GDB remote serial protocol support.
20060331	More cleanup, and some minor GDB remote progress.
20060402	Adding a hack to the configure script, to allow compilation
		on systems that lack PRIx64 etc.
20060406	Removing the temporary FreeBSD/arm hack in dev_ns16550.c and
		replacing it with a better fix from Olivier Houchard.
20060407	A remote debugger (gdb or ddd) can now start and stop the
		emulator using the GDB remote serial protocol, and registers
		and memory can be read. MIPS only for now.
20060408	More GDB progress: single-stepping also works, and also adding
		support for ARM, PowerPC, and Alpha targets.
		Continuing on the delay-slot-across-page-boundary issue.
20060412	Minor update: beginning to add support for the SPARC target
		to the remote GDB functionality.
20060414	Various MIPS updates: adding more instructions for dyntrans
		(eret, add), and making some exceptions work. Fixing a bug
		in dmult[u].
		Implementing the first SPARC instructions (sethi, or).
20060415	Adding "magic trap" instructions so that PROM calls can be
		software emulated in MIPS dyntrans.
		Adding more MIPS dyntrans instructions (ddiv, dadd) and
		fixing another bug in dmult.
20060416	More MIPS dyntrans progress: adding [d]addi, movn, movz, dsllv,
		rfi, an ugly hack for supporting R2000/R3000 style faked caches,
		preliminary interrupt support, and various other updates and
		bugfixes.
20060417	Adding more SPARC instructions (add, sub, sll[x], sra[x],
		srl[x]), and useful SPARC header definitions.
		Adding the first (trivial) x86/AMD64 dyntrans instructions (nop,
		cli/sti, stc/clc, std/cld, simple mov, inc ax). Various other
		x86 updates related to variable instruction length stuff.
		Adding unaligned loads/stores to the MIPS dyntrans mode (but
		still using the pre-dyntrans (slow) imlementation).
20060419	Fixing a MIPS dyntrans exception-in-delay-slot bug.
		Removing the old "show opcode statistics" functionality, since
		it wasn't really useful and isn't implemented for dyntrans.
		Single-stepping (or running with instruction trace) now looks
		ok with dyntrans with delay-slot architectures.
20060420	Minor hacks (removing the -B command line option when compiled
		for non-bintrans, and some other very minor updates).
		Adding (slow) MIPS dyntrans load-linked/store-conditional.
20060422	Applying fixes for bugs discovered by Nils Weller's nwcc
		(static DEC memmap => now per machine, and adding an extern
		keyword in cpu_arm_instr.c).
		Finally found one of the MIPS dyntrans bugs that I've been
		looking for (copy/paste spelling error BIG vs LITTLE endian in
		cpu_mips_instr_loadstore.c for 16-bit fast stores).
		FINALLY found the major MIPS dyntrans bug: slti vs sltiu
		signed/unsigned code in cpu_mips_instr.c. :-)
		Adding more MIPS dyntrans instructions (lwc1, swc1, bgezal[l],
		ctc1, tlt[u], tge[u], tne, beginning on rdhwr).
		NetBSD/hpcmips can now reach userland when using dyntrans :-)
		Adding some more x86 dyntrans instructions.
		Finally removed the old Alpha-specific virtual memory code,
		and replaced it with the generic 64-bit version.
		Beginning to add disassembly support for SPECIAL3 MIPS opcodes.
20060423	Continuing on the delay-slot-across-page-boundary issue;
		adding an end_of_page2 ic slot (like I had planned before, but
		had removed for some reason).
		Adding a quick-and-dirty fallback to legacy coprocessor 1
		code (i.e. skipping dyntrans implementation for now).
		NetBSD/hpcmips and NetBSD/pmax (when running on an emulated
		R4400) can now be installed and run. :-)  (Many bugs left
		to fix, though.)
		Adding more MIPS dyntrans instructions: madd[u], msub[u].
		Cleaning up the SPECIAL2 vs R5900/TX79/C790 "MMI" opcode
		maps somewhat (disassembly and dyntrans instruction decoding).
20060424	Adding an isa_revision field to mips_cpu_types.h, and making
		sure that SPECIAL3 opcodes cause Reserved Instruction
		exceptions on MIPS32/64 revisions lower than 2.
		Adding the SPARC 'ba', 'call', 'jmpl/retl', 'and', and 'xor'
		instructions.
20060425	Removing the -m command line option ("run at most x 
		instructions") and -T ("single_step_on_bad_addr"), because
		they never worked correctly with dyntrans anyway.
		Freshening up the man page.
20060428	Adding more MIPS dyntrans instructions: bltzal[l], idle.
		Enabling MIPS dyntrans compare interrupts.
20060429	FINALLY found the weird dyntrans bug, causing NetBSD etc. to
		behave strangely: some floating point code (conditional
		coprocessor branches) could not be reused from the old
		non-dyntrans code. The "quick-and-dirty fallback" only appeared
		to work. Fixing by implementing bc1* for MIPS dyntrans.
		More MIPS instructions: [d]sub, sdc1, ldc1, dmtc1, dmfc1, cfc0.
		Freshening up MIPS floating point disassembly appearance.
20060430	Continuing on C790/R5900/TX79 disassembly; implementing 128-bit
		"por" and "pextlw".
20060504	Disabling -u (userland emulation) unless compiled as unstable
		development version.
		Beginning on freshening up the testmachine include files,
		to make it easier to reuse those files (placing them in
		src/include/testmachine/), and beginning on a set of "demos"
		or "tutorials" for the testmachine functionality.
		Minor updates to the MIPS GDB remote protocol stub.
		Refreshing doc/experiments.html and gdb_remote.html.
		Enabling Alpha emulation in the stable release configuration,
		even though no guest OSes for Alpha can run yet.
20060505	Adding a generic 'settings' object, which will contain
		references to settable variables (which will later be possible
		to access using the debugger).
20060506	Updating dev_disk and corresponding demo/documentation (and
		switching from SCSI to IDE disk types, so it actually works
		with current test machines :-).
20060510	Adding a -D_LARGEFILE_SOURCE hack for 64-bit Linux hosts,
		so that fseeko() doesn't give a warning.
		Updating the section about how dyntrans works (the "runnable
		IR") in doc/intro.html.
		Instruction updates (some x64=1 checks, some more R5900
		dyntrans stuff: better mul/mult separation from MIPS32/64,
		adding ei and di).
		Updating MIPS cpuregs.h to a newer one (from NetBSD).
		Adding more MIPS dyntrans instructions: deret, ehb.
20060514	Adding disassembly and beginning implementation of SPARC wr
		and wrpr instructions.
20060515	Adding a SUN SPARC machine mode, with dummy SS20 and Ultra1
		machines. Adding the 32-bit "rd psr" instruction.
20060517	Disassembly support for the general SPARC rd instruction.
		Partial implementation of the cmp (subcc) instruction.
		Some other minor updates (making sure that R5900 processors
		start up with the EIE bit enabled, otherwise Linux/playstation2
		receives no interrupts).
20060519	Minor MIPS updates/cleanups.
20060521	Moving the MeshCube machine into evbmips; this seems to work
		reasonably well with a snapshot of a NetBSD MeshCube kernel.
		Cleanup/fix of MIPS config0 register initialization.
20060529	Minor MIPS fixes, including a sign-extension fix to the
		unaligned load/store code, which makes NetBSD/pmax on R3000
		work better with dyntrans. (Ultrix and Linux/DECstation still
		don't work, though.)
20060530	Minor updates to the Alpha machine mode: adding an AlphaBook
		mode, an LCA bus (forwarding accesses to an ISA bus), etc.
20060531	Applying a bugfix for the MIPS dyntrans sc[d] instruction from
		Ondrej Palkovsky. (Many thanks.)
20060601	Minifix to allow ARM immediate msr instruction to not give
		an error for some valid values.
		More Alpha updates.
20060602	Some minor Alpha updates.
20060603	Adding the Alpha cmpbge instruction. NetBSD/alpha prints its
		first boot messages :-) on an emulated Alphabook 1.
20060612	Minor updates; adding a dev_ether.h include file for the
		testmachine ether device. Continuing the hunt for the dyntrans
		bug which makes Linux and Ultrix on DECstation behave
		strangely... FINALLY found it! It seems to be related to
		invalidation of the translation cache, on tlbw{r,i}. There
		also seems to be some remaining interrupt-related problems.
20060614	Correcting the implementation of ldc1/sdc1 for MIPS dyntrans
		(so that it uses 16 32-bit registers if the FR bit in the
		status register is not set).
20060616	REMOVING BINTRANS COMPLETELY!
		Removing the old MIPS interpretation mode.
		Removing the MFHILO_DELAY and instruction delay stuff, because
		they wouldn't work with dyntrans anyway.
20060617	Some documentation updates (adding "NetBSD-archive" to some
		URLs, and new Debian/DECstation installation screenshots).
		Removing the "tracenull" and "enable-caches" configure options.
		Improving MIPS dyntrans performance somewhat (only invalidate
		translations if necessary, on writes to the entryhi register,
		instead of doing it for all cop0 writes).
20060618	More cleanup after the removal of the old MIPS emulation.
		Trying to fix the MIPS dyntrans performance bugs/bottlenecks;
		only semi-successful so far (for R3000).
20060620	Minor update to allow clean compilation again on Tru64/Alpha.
20060622	MIPS cleanup and fixes (removing the pc_last stuff, which
		doesn't make sense with dyntrans anyway, and fixing a cross-
		page-delay-slot-with-exception case in end_of_page).
		Removing the old max_random_cycles_per_chunk stuff, and the
		concept of cycles vs instructions for MIPS emulation.
		FINALLY found and fixed the bug which caused NetBSD/pmax
		clocks to behave strangely (it was a load to the zero register,
		which was treated as a NOP; now it is treated as a load to a
		dummy scratch register).
20060623	Increasing the dyntrans chunk size back to
		N_SAFE_DYNTRANS_LIMIT, instead of N_SAFE_DYNTRANS_LIMIT/2.
		Preparing for a quick release, even though there are known
		bugs, and performance for non-R3000 MIPS emulation is very
		poor. :-/
		Reverting to half the dyntrans chunk size again, because
		NetBSD/cats seemed less stable with full size chunks. :(
		NetBSD/sgimips 3.0 can now run :-)  (With release 0.3.8, only
		NetBSD/sgimips 2.1 worked, not 3.0.)

==============  RELEASE 0.4.0  ==============


1 /* GXemul: $Id: armreg.h,v 1.3 2006/02/26 20:11:14 debug Exp $ */
2 /* $NetBSD: armreg.h,v 1.33 2005/07/20 14:38:11 nonaka Exp $ */
3
4 /*
5 * Copyright (c) 1998, 2001 Ben Harris
6 * Copyright (c) 1994-1996 Mark Brinicombe.
7 * Copyright (c) 1994 Brini.
8 * All rights reserved.
9 *
10 * This code is derived from software written for Brini by Mark Brinicombe
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by Brini.
23 * 4. The name of the company nor the name of the author may be used to
24 * endorse or promote products derived from this software without specific
25 * prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 */
39
40 #ifndef _ARM_ARMREG_H
41 #define _ARM_ARMREG_H
42
43 /*
44 * ARM Process Status Register
45 *
46 * The picture in the ARM manuals looks like this:
47 * 3 3 2 2 2 2
48 * 1 0 9 8 7 6 8 7 6 5 4 0
49 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
50 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
51 * | | | | | | | | | |4 3 2 1 0|
52 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
53 */
54
55 #define PSR_FLAGS 0xf0000000 /* flags */
56 #define PSR_N_bit (1 << 31) /* negative */
57 #define PSR_Z_bit (1 << 30) /* zero */
58 #define PSR_C_bit (1 << 29) /* carry */
59 #define PSR_V_bit (1 << 28) /* overflow */
60
61 #define PSR_Q_bit (1 << 27) /* saturation */
62
63 #define I32_bit (1 << 7) /* IRQ disable */
64 #define F32_bit (1 << 6) /* FIQ disable */
65
66 #define PSR_T_bit (1 << 5) /* Thumb state */
67 #define PSR_J_bit (1 << 24) /* Java mode */
68
69 #define PSR_MODE 0x0000001f /* mode mask */
70 #define PSR_USR26_MODE 0x00000000
71 #define PSR_FIQ26_MODE 0x00000001
72 #define PSR_IRQ26_MODE 0x00000002
73 #define PSR_SVC26_MODE 0x00000003
74 #define PSR_USR32_MODE 0x00000010
75 #define PSR_FIQ32_MODE 0x00000011
76 #define PSR_IRQ32_MODE 0x00000012
77 #define PSR_SVC32_MODE 0x00000013
78 #define PSR_ABT32_MODE 0x00000017
79 #define PSR_UND32_MODE 0x0000001b
80 #define PSR_SYS32_MODE 0x0000001f
81 #define PSR_32_MODE 0x00000010
82
83 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
84 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE)
85
86 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */
87
88 #define R15_MODE 0x00000003
89 #define R15_MODE_USR 0x00000000
90 #define R15_MODE_FIQ 0x00000001
91 #define R15_MODE_IRQ 0x00000002
92 #define R15_MODE_SVC 0x00000003
93
94 #define R15_PC 0x03fffffc
95
96 #define R15_FIQ_DISABLE 0x04000000
97 #define R15_IRQ_DISABLE 0x08000000
98
99 #define R15_FLAGS 0xf0000000
100 #define R15_FLAG_N 0x80000000
101 #define R15_FLAG_Z 0x40000000
102 #define R15_FLAG_C 0x20000000
103 #define R15_FLAG_V 0x10000000
104
105 /*
106 * Co-processor 15: The system control co-processor.
107 */
108
109 #define ARM_CP15_CPU_ID 0
110
111 /*
112 * The CPU ID register is theoretically structured, but the definitions of
113 * the fields keep changing.
114 */
115
116 /* The high-order byte is always the implementor */
117 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000
118 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
119 #define CPU_ID_DEC 0x44000000 /* 'D' */
120 #define CPU_ID_INTEL 0x69000000 /* 'i' */
121 #define CPU_ID_TI 0x54000000 /* 'T' */
122
123 /* How to decide what format the CPUID is in. */
124 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
125 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
126 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
127
128 /* On ARM3 and ARM6, this byte holds the foundry ID. */
129 #define CPU_ID_FOUNDRY_MASK 0x00ff0000
130 #define CPU_ID_FOUNDRY_VLSI 0x00560000
131
132 /* On ARM7 it holds the architecture and variant (sub-model) */
133 #define CPU_ID_7ARCH_MASK 0x00800000
134 #define CPU_ID_7ARCH_V3 0x00000000
135 #define CPU_ID_7ARCH_V4T 0x00800000
136 #define CPU_ID_7VARIANT_MASK 0x007f0000
137
138 /* On more recent ARMs, it does the same, but in a different format */
139 #define CPU_ID_ARCH_MASK 0x000f0000
140 #define CPU_ID_ARCH_V3 0x00000000
141 #define CPU_ID_ARCH_V4 0x00010000
142 #define CPU_ID_ARCH_V4T 0x00020000
143 #define CPU_ID_ARCH_V5 0x00030000
144 #define CPU_ID_ARCH_V5T 0x00040000
145 #define CPU_ID_ARCH_V5TE 0x00050000
146 #define CPU_ID_ARCH_V5TEJ 0x00060000
147 #define CPU_ID_ARCH_V6 0x00070000
148 #define CPU_ID_VARIANT_MASK 0x00f00000
149
150 /* Next three nybbles are part number */
151 #define CPU_ID_PARTNO_MASK 0x0000fff0
152
153 /* Intel XScale has sub fields in part number */
154 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
155 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
156 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
157
158 /* And finally, the revision number. */
159 #define CPU_ID_REVISION_MASK 0x0000000f
160
161 /* Individual CPUs are probably best IDed by everything but the revision. */
162 #define CPU_ID_CPU_MASK 0xfffffff0
163
164 /* Fake CPU IDs for ARMs without CP15 */
165 #define CPU_ID_ARM2 0x41560200
166 #define CPU_ID_ARM250 0x41560250
167
168 /* Pre-ARM7 CPUs -- [15:12] == 0 */
169 #define CPU_ID_ARM3 0x41560300
170 #define CPU_ID_ARM600 0x41560600
171 #define CPU_ID_ARM610 0x41560610
172 #define CPU_ID_ARM620 0x41560620
173
174 /* ARM7 CPUs -- [15:12] == 7 */
175 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */
176 #define CPU_ID_ARM710 0x41007100
177 #define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */
178 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */
179 #define CPU_ID_ARM7500FE 0x41077100
180 #define CPU_ID_ARM710T 0x41807100
181 #define CPU_ID_ARM720T 0x41807200
182 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */
183 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
184
185 /* Post-ARM7 CPUs */
186 #define CPU_ID_ARM810 0x41018100
187 #define CPU_ID_ARM920T 0x41129200
188 #define CPU_ID_ARM922T 0x41029220
189 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
190 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
191 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
192 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
193 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
194 #define CPU_ID_ARM1022ES 0x4105a220
195 #define CPU_ID_ARM1026EJS 0x4106a260
196 #define CPU_ID_ARM1136JS 0x4107b360
197 #define CPU_ID_ARM1136JSR1 0x4117b360
198 #define CPU_ID_SA110 0x4401a100
199 #define CPU_ID_SA1100 0x4401a110
200 #define CPU_ID_TI925T 0x54029250
201 #define CPU_ID_SA1110 0x6901b110
202 #define CPU_ID_IXP1200 0x6901c120
203 #define CPU_ID_80200 0x69052000
204 #define CPU_ID_PXA250 0x69052100 /* sans core revision */
205 #define CPU_ID_PXA210 0x69052120
206 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
207 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
208 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
209 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
210 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
211 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
212 #define CPU_ID_PXA27X 0x69054110
213 #define CPU_ID_80321_400 0x69052420
214 #define CPU_ID_80321_600 0x69052430
215 #define CPU_ID_80321_400_B0 0x69052c20
216 #define CPU_ID_80321_600_B0 0x69052c30
217 #define CPU_ID_80321_600_2 0x69052c32
218 #define CPU_ID_80219_400 0x69052e20
219 #define CPU_ID_80219_600 0x69052e30
220 #define CPU_ID_IXP425_533 0x690541c0
221 #define CPU_ID_IXP425_400 0x690541d0
222 #define CPU_ID_IXP425_266 0x690541f0
223
224 /* ARM3-specific coprocessor 15 registers */
225 #define ARM3_CP15_FLUSH 1
226 #define ARM3_CP15_CONTROL 2
227 #define ARM3_CP15_CACHEABLE 3
228 #define ARM3_CP15_UPDATEABLE 4
229 #define ARM3_CP15_DISRUPTIVE 5
230
231 /* ARM3 Control register bits */
232 #define ARM3_CTL_CACHE_ON 0x00000001
233 #define ARM3_CTL_SHARED 0x00000002
234 #define ARM3_CTL_MONITOR 0x00000004
235
236 /*
237 * Post-ARM3 CP15 registers:
238 *
239 * 1 Control register
240 *
241 * 2 Translation Table Base
242 *
243 * 3 Domain Access Control
244 *
245 * 4 Reserved
246 *
247 * 5 Fault Status
248 *
249 * 6 Fault Address
250 *
251 * 7 Cache/write-buffer Control
252 *
253 * 8 TLB Control
254 *
255 * 9 Cache Lockdown
256 *
257 * 10 TLB Lockdown
258 *
259 * 11 Reserved
260 *
261 * 12 Reserved
262 *
263 * 13 Process ID (for FCSE)
264 *
265 * 14 Reserved
266 *
267 * 15 Implementation Dependent
268 */
269
270 /* Some of the definitions below need cleaning up for V3/V4 architectures */
271
272 /* CPU control register (CP15 register 1) */
273 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
274 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
275 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
276 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
277 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
278 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
279 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
280 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
281 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
282 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
283 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
284 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
285 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
286 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
287 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
288 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
289
290 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
291
292 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
293 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
294 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
295 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
296 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
297 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
298 #define XSCALE_AUXCTL_MD_MASK 0x00000030
299
300 /* Cache type register definitions */
301 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
302 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
303 #define CPU_CT_S (1U << 24) /* split cache */
304 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
305
306 #define CPU_CT_CTYPE_WT 0 /* write-through */
307 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
308 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
309 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
310 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
311
312 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
313 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
314 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
315 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
316
317 /* Fault status register definitions */
318
319 #define FAULT_TYPE_MASK 0x0f
320 #define FAULT_USER 0x10
321
322 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */
323 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
324 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
325 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
326 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
327 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
328 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
329 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
330 #define FAULT_ALIGN_0 0x01 /* Alignment */
331 #define FAULT_ALIGN_1 0x03 /* Alignment */
332 #define FAULT_TRANS_S 0x05 /* Translation -- Section */
333 #define FAULT_TRANS_P 0x07 /* Translation -- Page */
334 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
335 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
336 #define FAULT_PERM_S 0x0d /* Permission -- Section */
337 #define FAULT_PERM_P 0x0f /* Permission -- Page */
338
339 #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
340
341 /*
342 * Address of the vector page, low and high versions.
343 */
344 #define ARM_VECTORS_LOW 0x00000000U
345 #define ARM_VECTORS_HIGH 0xffff0000U
346
347 /*
348 * ARM Instructions
349 *
350 * 3 3 2 2 2
351 * 1 0 9 8 7 0
352 * +-------+-------------------------------------------------------+
353 * | cond | instruction dependent |
354 * |c c c c| |
355 * +-------+-------------------------------------------------------+
356 */
357
358 #define INSN_SIZE 4 /* Always 4 bytes */
359 #define INSN_COND_MASK 0xf0000000 /* Condition mask */
360 #define INSN_COND_AL 0xe0000000 /* Always condition */
361
362 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
363
364 #endif

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