/[gxemul]/trunk/src/include/armreg.h
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Contents of /trunk/src/include/armreg.h

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Revision 22 - (show annotations)
Mon Oct 8 16:19:37 2007 UTC (16 years, 7 months ago) by dpavlin
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++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1121 2006/02/18 21:03:08 debug Exp $
20051126	Cobalt and PReP now work with the 21143 NIC.
		Continuing on Alpha dyntrans things.
		Fixing some more left-shift-by-24 to unsigned.
20051127	Working on OpenFirmware emulation; major cleanup/redesign.
		Progress on MacPPC emulation: NetBSD detects two CPUs (when
		running with -n 2), framebuffer output (for text) works.
		Adding quick-hack Bandit PCI controller and "gc" interrupt
		controller for MacPPC.
20051128	Changing from a Bandit to a Uni-North controller for macppc.
		Continuing on OpenFirmware and MacPPC emulation in general
		(obio controller, and wdc attached to the obio seems to work).
20051129	More work on MacPPC emulation (adding a dummy ADB controller).
		Continuing the PCI bus cleanup (endianness and tag composition)
		and rewriting all PCI controllers' access functions.
20051130	Various minor PPC dyntrans optimizations.
		Manually inlining some parts of the framebuffer redraw routine.
		Slowly beginning the conversion of the old MIPS emulation into
		dyntrans (but this will take quite some time to get right).
		Generalizing quick_pc_to_pointers.
20051201	Documentation update (David Muse has made available a kernel
		which simplifies Debian/DECstation installation).
		Continuing on the ADB bus controller.
20051202	Beginning a rewrite of the Zilog serial controller (dev_zs).
20051203	Continuing on the zs rewrite (now called dev_z8530); conversion
		to devinit style.
		Reworking some of the input-only vs output-only vs input-output
		details of src/console.c, better warning messages, and adding
		a debug dump.
		Removing the concept of "device state"; it wasn't really used.
		Changing some debug output (-vv should now be used to show all
		details about devices and busses; not shown during normal
		startup anymore).
		Beginning on some SPARC instruction disassembly support.
20051204	Minor PPC updates (WALNUT skeleton stuff).
		Continuing on the MIPS dyntrans rewrite.
		More progress on the ADB controller (a keyboard is "detected"
		by NetBSD and OpenBSD).
		Downgrading OpenBSD/arc as a guest OS from "working" to
		"almost working" in the documentation.
		Progress on Algor emulation ("v3" PCI controller).
20051205	Minor updates.
20051207	Sorting devices according to address; this reduces complexity
		of device lookups from O(n) to O(log n) in memory_rw (but no
		real performance increase (yet) in experiments).
20051210	Beginning the work on native dyntrans backends (by making a
		simple skeleton; so far only for Alpha hosts).
20051211	Some very minor SPARC updates.
20051215	Fixing a bug in the MIPS mul (note: not mult) instruction,
		so it also works with non-64-bit emulation. (Thanks to Alec
		Voropay for noticing the problem.)
20051216	More work on the fake/empty/simple/skeleton/whatever backend;
		performance doesn't increase, so this isn't really worth it,
		but it was probably worth it to prepare for a real backend
		later.
20051219	More instr call statistics gathering and analysis stuff.
20051220	Another fix for MIPS 'mul'. Also converting mul and {d,}cl{o,z}
		to dyntrans.
		memory_ppc.c syntax error fix (noticed by Peter Valchev).
		Beginning to move out machines from src/machine.c into
		individual files in src/machines (in a way similar to the
		autodev system for devices).
20051222	Updating the documentation regarding NetBSD/pmax 3.0.
20051223	- " - NetBSD/cats 3.0.
20051225	- " - NetBSD/hpcmips 3.0.
20051226	Continuing on the machine registry redesign.
		Adding support for ARM rrx (33-bit rotate).
		Fixing some signed/unsigned issues (exposed by gcc -W).
20051227	Fixing the bug which prevented a NetBSD/prep 3.0 install kernel
		from starting (triggered when an mtmsr was the last instruction
		on a page). Unfortunately not enough to get the kernel to run
		as well as the 2.1 kernels did.
20051230	Some dyntrans refactoring.
20051231	Continuing on the machine registry redesign.
20060101-10	Continuing... moving more machines. Moving MD interrupt stuff
		from machine.c into a new src/machines/interrupts.c.
20060114	Adding various mvmeppc machine skeletons.
20060115	Continuing on mvme* stuff. NetBSD/mvmeppc prints boot messages
		(for MVME1600) and reaches the root device prompt, but no
		specific hardware devices are emulated yet.
20060116	Minor updates to the mvme1600 emulation mode; the Eagle PCI bus
		seems to work without much modification, and a 21143 can be
		detected, interrupts might work (but untested so far).
		Adding a fake MK48Txx (mkclock) device, for NetBSD/mvmeppc.
20060121	Adding an aux control register for ARM. (A BIG thank you to
		Olivier Houchard for tracking down this bug.)
20060122	Adding more ARM instructions (smulXY), and dev_iq80321_7seg.
20060124	Adding disassembly of more ARM instructions (mia*, mra/mar),
		and some semi-bogus XScale and i80321 registers.
20060201-02	Various minor updates. Moving the last machines out of
		machine.c.
20060204	Adding a -c command line option, for running debugger commands
		before the simulation starts, but after all files have been
		loaded.
		Minor iq80321-related updates.
20060209	Minor hacks (DEVINIT macro, etc).
		Preparing for the generalization of the 64-bit dyntrans address
		translation subsystem.
20060216	Adding ARM ldrd (double-register load).
20060217	Continuing on various ARM-related stuff.
20060218	More progress on the ATA/wdc emulation for NetBSD/iq80321.
		NetBSD/evbarm can now be installed :-)  Updating the docs, etc.
		Continuing on Algor emulation.

==============  RELEASE 0.3.8  ==============
1 /* GXemul: $Id: armreg.h,v 1.2 2006/02/05 10:26:36 debug Exp $ */
2 /* $NetBSD: armreg.h,v 1.33 2005/07/20 14:38:11 nonaka Exp $ */
3
4 /*
5 * Copyright (c) 1998, 2001 Ben Harris
6 * Copyright (c) 1994-1996 Mark Brinicombe.
7 * Copyright (c) 1994 Brini.
8 * All rights reserved.
9 *
10 * This code is derived from software written for Brini by Mark Brinicombe
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by Brini.
23 * 4. The name of the company nor the name of the author may be used to
24 * endorse or promote products derived from this software without specific
25 * prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 */
39
40 #ifndef _ARM_ARMREG_H
41 #define _ARM_ARMREG_H
42
43 /*
44 * ARM Process Status Register
45 *
46 * The picture in the ARM manuals looks like this:
47 * 3 3 2 2 2 2
48 * 1 0 9 8 7 6 8 7 6 5 4 0
49 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
50 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M|
51 * | | | | | | | | | |4 3 2 1 0|
52 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+
53 */
54
55 #define PSR_FLAGS 0xf0000000 /* flags */
56 #define PSR_N_bit (1 << 31) /* negative */
57 #define PSR_Z_bit (1 << 30) /* zero */
58 #define PSR_C_bit (1 << 29) /* carry */
59 #define PSR_V_bit (1 << 28) /* overflow */
60
61 #define PSR_Q_bit (1 << 27) /* saturation */
62
63 #define I32_bit (1 << 7) /* IRQ disable */
64 #define F32_bit (1 << 6) /* FIQ disable */
65
66 #define PSR_T_bit (1 << 5) /* Thumb state */
67 #define PSR_J_bit (1 << 24) /* Java mode */
68
69 #define PSR_MODE 0x0000001f /* mode mask */
70 #define PSR_USR26_MODE 0x00000000
71 #define PSR_FIQ26_MODE 0x00000001
72 #define PSR_IRQ26_MODE 0x00000002
73 #define PSR_SVC26_MODE 0x00000003
74 #define PSR_USR32_MODE 0x00000010
75 #define PSR_FIQ32_MODE 0x00000011
76 #define PSR_IRQ32_MODE 0x00000012
77 #define PSR_SVC32_MODE 0x00000013
78 #define PSR_ABT32_MODE 0x00000017
79 #define PSR_UND32_MODE 0x0000001b
80 #define PSR_SYS32_MODE 0x0000001f
81 #define PSR_32_MODE 0x00000010
82
83 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */
84 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE)
85
86 /* In 26-bit modes, the PSR is stuffed into R15 along with the PC. */
87
88 #define R15_MODE 0x00000003
89 #define R15_MODE_USR 0x00000000
90 #define R15_MODE_FIQ 0x00000001
91 #define R15_MODE_IRQ 0x00000002
92 #define R15_MODE_SVC 0x00000003
93
94 #define R15_PC 0x03fffffc
95
96 #define R15_FIQ_DISABLE 0x04000000
97 #define R15_IRQ_DISABLE 0x08000000
98
99 #define R15_FLAGS 0xf0000000
100 #define R15_FLAG_N 0x80000000
101 #define R15_FLAG_Z 0x40000000
102 #define R15_FLAG_C 0x20000000
103 #define R15_FLAG_V 0x10000000
104
105 /*
106 * Co-processor 15: The system control co-processor.
107 */
108
109 #define ARM_CP15_CPU_ID 0
110
111 /*
112 * The CPU ID register is theoretically structured, but the definitions of
113 * the fields keep changing.
114 */
115
116 /* The high-order byte is always the implementor */
117 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000
118 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
119 #define CPU_ID_DEC 0x44000000 /* 'D' */
120 #define CPU_ID_INTEL 0x69000000 /* 'i' */
121 #define CPU_ID_TI 0x54000000 /* 'T' */
122
123 /* How to decide what format the CPUID is in. */
124 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
125 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
126 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
127
128 /* On ARM3 and ARM6, this byte holds the foundry ID. */
129 #define CPU_ID_FOUNDRY_MASK 0x00ff0000
130 #define CPU_ID_FOUNDRY_VLSI 0x00560000
131
132 /* On ARM7 it holds the architecture and variant (sub-model) */
133 #define CPU_ID_7ARCH_MASK 0x00800000
134 #define CPU_ID_7ARCH_V3 0x00000000
135 #define CPU_ID_7ARCH_V4T 0x00800000
136 #define CPU_ID_7VARIANT_MASK 0x007f0000
137
138 /* On more recent ARMs, it does the same, but in a different format */
139 #define CPU_ID_ARCH_MASK 0x000f0000
140 #define CPU_ID_ARCH_V3 0x00000000
141 #define CPU_ID_ARCH_V4 0x00010000
142 #define CPU_ID_ARCH_V4T 0x00020000
143 #define CPU_ID_ARCH_V5 0x00030000
144 #define CPU_ID_ARCH_V5T 0x00040000
145 #define CPU_ID_ARCH_V5TE 0x00050000
146 #define CPU_ID_ARCH_V5TEJ 0x00060000
147 #define CPU_ID_ARCH_V6 0x00070000
148 #define CPU_ID_VARIANT_MASK 0x00f00000
149
150 /* Next three nybbles are part number */
151 #define CPU_ID_PARTNO_MASK 0x0000fff0
152
153 /* Intel XScale has sub fields in part number */
154 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
155 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
156 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
157
158 /* And finally, the revision number. */
159 #define CPU_ID_REVISION_MASK 0x0000000f
160
161 /* Individual CPUs are probably best IDed by everything but the revision. */
162 #define CPU_ID_CPU_MASK 0xfffffff0
163
164 /* Fake CPU IDs for ARMs without CP15 */
165 #define CPU_ID_ARM2 0x41560200
166 #define CPU_ID_ARM250 0x41560250
167
168 /* Pre-ARM7 CPUs -- [15:12] == 0 */
169 #define CPU_ID_ARM3 0x41560300
170 #define CPU_ID_ARM600 0x41560600
171 #define CPU_ID_ARM610 0x41560610
172 #define CPU_ID_ARM620 0x41560620
173
174 /* ARM7 CPUs -- [15:12] == 7 */
175 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */
176 #define CPU_ID_ARM710 0x41007100
177 #define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */
178 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */
179 #define CPU_ID_ARM7500FE 0x41077100
180 #define CPU_ID_ARM710T 0x41807100
181 #define CPU_ID_ARM720T 0x41807200
182 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */
183 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
184
185 /* Post-ARM7 CPUs */
186 #define CPU_ID_ARM810 0x41018100
187 #define CPU_ID_ARM920T 0x41129200
188 #define CPU_ID_ARM922T 0x41029220
189 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
190 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
191 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
192 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
193 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
194 #define CPU_ID_ARM1022ES 0x4105a220
195 #define CPU_ID_ARM1026EJS 0x4106a260
196 #define CPU_ID_ARM1136JS 0x4107b360
197 #define CPU_ID_ARM1136JSR1 0x4117b360
198 #define CPU_ID_SA110 0x4401a100
199 #define CPU_ID_SA1100 0x4401a110
200 #define CPU_ID_TI925T 0x54029250
201 #define CPU_ID_SA1110 0x6901b110
202 #define CPU_ID_IXP1200 0x6901c120
203 #define CPU_ID_80200 0x69052000
204 #define CPU_ID_PXA250 0x69052100 /* sans core revision */
205 #define CPU_ID_PXA210 0x69052120
206 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
207 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
208 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
209 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
210 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
211 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
212 #define CPU_ID_PXA27X 0x69054110
213 #define CPU_ID_80321_400 0x69052420
214 #define CPU_ID_80321_600 0x69052430
215 #define CPU_ID_80321_400_B0 0x69052c20
216 #define CPU_ID_80321_600_B0 0x69052c30
217 #define CPU_ID_80219_400 0x69052e20
218 #define CPU_ID_80219_600 0x69052e30
219 #define CPU_ID_IXP425_533 0x690541c0
220 #define CPU_ID_IXP425_400 0x690541d0
221 #define CPU_ID_IXP425_266 0x690541f0
222
223 /* ARM3-specific coprocessor 15 registers */
224 #define ARM3_CP15_FLUSH 1
225 #define ARM3_CP15_CONTROL 2
226 #define ARM3_CP15_CACHEABLE 3
227 #define ARM3_CP15_UPDATEABLE 4
228 #define ARM3_CP15_DISRUPTIVE 5
229
230 /* ARM3 Control register bits */
231 #define ARM3_CTL_CACHE_ON 0x00000001
232 #define ARM3_CTL_SHARED 0x00000002
233 #define ARM3_CTL_MONITOR 0x00000004
234
235 /*
236 * Post-ARM3 CP15 registers:
237 *
238 * 1 Control register
239 *
240 * 2 Translation Table Base
241 *
242 * 3 Domain Access Control
243 *
244 * 4 Reserved
245 *
246 * 5 Fault Status
247 *
248 * 6 Fault Address
249 *
250 * 7 Cache/write-buffer Control
251 *
252 * 8 TLB Control
253 *
254 * 9 Cache Lockdown
255 *
256 * 10 TLB Lockdown
257 *
258 * 11 Reserved
259 *
260 * 12 Reserved
261 *
262 * 13 Process ID (for FCSE)
263 *
264 * 14 Reserved
265 *
266 * 15 Implementation Dependent
267 */
268
269 /* Some of the definitions below need cleaning up for V3/V4 architectures */
270
271 /* CPU control register (CP15 register 1) */
272 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
273 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
274 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
275 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
276 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
277 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
278 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
279 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
280 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
281 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
282 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
283 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
284 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
285 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
286 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
287 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
288
289 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
290
291 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
292 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
293 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
294 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
295 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
296 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
297 #define XSCALE_AUXCTL_MD_MASK 0x00000030
298
299 /* Cache type register definitions */
300 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
301 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
302 #define CPU_CT_S (1U << 24) /* split cache */
303 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
304
305 #define CPU_CT_CTYPE_WT 0 /* write-through */
306 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
307 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */
308 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */
309 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */
310
311 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
312 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */
313 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
314 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
315
316 /* Fault status register definitions */
317
318 #define FAULT_TYPE_MASK 0x0f
319 #define FAULT_USER 0x10
320
321 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */
322 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */
323 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */
324 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */
325 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */
326 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */
327 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */
328 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */
329 #define FAULT_ALIGN_0 0x01 /* Alignment */
330 #define FAULT_ALIGN_1 0x03 /* Alignment */
331 #define FAULT_TRANS_S 0x05 /* Translation -- Section */
332 #define FAULT_TRANS_P 0x07 /* Translation -- Page */
333 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */
334 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */
335 #define FAULT_PERM_S 0x0d /* Permission -- Section */
336 #define FAULT_PERM_P 0x0f /* Permission -- Page */
337
338 #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */
339
340 /*
341 * Address of the vector page, low and high versions.
342 */
343 #define ARM_VECTORS_LOW 0x00000000U
344 #define ARM_VECTORS_HIGH 0xffff0000U
345
346 /*
347 * ARM Instructions
348 *
349 * 3 3 2 2 2
350 * 1 0 9 8 7 0
351 * +-------+-------------------------------------------------------+
352 * | cond | instruction dependent |
353 * |c c c c| |
354 * +-------+-------------------------------------------------------+
355 */
356
357 #define INSN_SIZE 4 /* Always 4 bytes */
358 #define INSN_COND_MASK 0xf0000000 /* Condition mask */
359 #define INSN_COND_AL 0xe0000000 /* Always condition */
360
361 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */
362
363 #endif
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