--- trunk/src/include/arm_cpu_types.h	2007/10/08 16:19:28	21
+++ trunk/src/include/arm_cpu_types.h	2007/10/08 16:19:37	22
@@ -2,7 +2,7 @@
 #define	ARM_CPU_TYPES_H
 
 /*
- *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
+ *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions are met:
@@ -28,15 +28,18 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: arm_cpu_types.h,v 1.4 2005/09/20 21:05:23 debug Exp $
+ *  $Id: arm_cpu_types.h,v 1.8 2006/01/25 05:51:13 debug Exp $
  */
 
 /*  See cpu_arm.h for struct arm_cpu_type_def.  */
 /*  See armreg.h for CPU_ID_xxx defines.  */
 
+/*  TODO: Refactor these flags  */
+
 /*  Flags:  */
 #define	ARM_NO_MMU		1
 #define	ARM_DUAL_ENDIAN		2
+#define	ARM_XSCALE		4
 
 #include "armreg.h"
 
@@ -82,26 +85,26 @@
 	{ "IXP1200",	CPU_ID_IXP1200,	0,		14, 1, 14, 1 }, \
 	{ "80200",	CPU_ID_80200,	0,		14, 1, 14, 1 }, \
 	\
-	{ "PXA210",	CPU_ID_PXA210,	0,		16, 1,  0, 1 }, \
-	{ "PXA210A",	CPU_ID_PXA210A,	0,		16, 1,  0, 1 }, \
-	{ "PXA210B",	CPU_ID_PXA210B,	0,		16, 1,  0, 1 }, \
-	{ "PXA210C",	CPU_ID_PXA210C,	0,		16, 1,  0, 1 }, \
-	{ "PXA250",	CPU_ID_PXA250,	0,		16, 1,  0, 1 }, \
-	{ "PXA250A",	CPU_ID_PXA250A,	0,		16, 1,  0, 1 }, \
-	{ "PXA250B",	CPU_ID_PXA250B,	0,		16, 1,  0, 1 }, \
-	{ "PXA250C",	CPU_ID_PXA250C,	0,		16, 1,  0, 1 }, \
-	{ "PXA27X",	CPU_ID_PXA27X,	0,		16, 1,  0, 1 }, \
-	\
-	{ "IXP425_255",	CPU_ID_IXP425_266,	0,	14, 1, 14, 1 }, \
-	{ "IXP425_400",	CPU_ID_IXP425_400,	0,	14, 1, 14, 1 }, \
-	{ "IXP425_533",	CPU_ID_IXP425_533,	0,	14, 1, 14, 1 }, \
-	\
-	{ "80219_400",	CPU_ID_80219_400,0,		14, 1, 14, 1 }, \
-	{ "80219_600",	CPU_ID_80219_600,0,		14, 1, 14, 1 }, \
-	{ "80321_400",	CPU_ID_80321_400,0,		14, 1, 14, 1 }, \
-	{ "80321_400_B0",CPU_ID_80321_400_B0,0,		14, 1, 14, 1 }, \
-	{ "80321_600",	CPU_ID_80321_600,0,		14, 1, 14, 1 }, \
-	{ "80321_600_B0",CPU_ID_80321_600_B0,0,		14, 1, 14, 1 }, \
+	{ "PXA210",	CPU_ID_PXA210,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA210A",	CPU_ID_PXA210A,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA210B",	CPU_ID_PXA210B,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA210C",	CPU_ID_PXA210C,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA250",	CPU_ID_PXA250,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA250A",	CPU_ID_PXA250A,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA250B",	CPU_ID_PXA250B,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA250C",	CPU_ID_PXA250C,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	{ "PXA27X",	CPU_ID_PXA27X,	ARM_XSCALE,	16, 1,  0, 1 }, \
+	\
+	{ "IXP425_255",	CPU_ID_IXP425_266,ARM_XSCALE,	15, 1, 15, 1 }, \
+	{ "IXP425_400",	CPU_ID_IXP425_400,ARM_XSCALE,	15, 1, 15, 1 }, \
+	{ "IXP425_533",	CPU_ID_IXP425_533,ARM_XSCALE,	15, 1, 15, 1 }, \
+	\
+	{ "80219_400",	CPU_ID_80219_400,ARM_XSCALE,	15, 1, 15, 1 }, \
+	{ "80219_600",	CPU_ID_80219_600,ARM_XSCALE,	15, 1, 15, 1 }, \
+	{ "80321_400",	CPU_ID_80321_400,ARM_XSCALE,	15, 1, 15, 1 }, \
+	{ "80321_400_B0",CPU_ID_80321_400_B0,ARM_XSCALE,15, 1, 15, 1 }, \
+	{ "80321_600",	CPU_ID_80321_600,ARM_XSCALE,	15, 1, 15, 1 }, \
+	{ "80321_600_B0",CPU_ID_80321_600_B0,ARM_XSCALE,15, 1, 15, 1 }, \
 	\
 	{ NULL, 0, 0, 0,0, 0,0 } }