/[gxemul]/trunk/src/include/arm_cpu_types.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 21 by dpavlin, Mon Oct 8 16:18:51 2007 UTC revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC
# Line 2  Line 2 
2  #define ARM_CPU_TYPES_H  #define ARM_CPU_TYPES_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: arm_cpu_types.h,v 1.4 2005/09/20 21:05:23 debug Exp $   *  $Id: arm_cpu_types.h,v 1.8 2006/01/25 05:51:13 debug Exp $
32   */   */
33    
34  /*  See cpu_arm.h for struct arm_cpu_type_def.  */  /*  See cpu_arm.h for struct arm_cpu_type_def.  */
35  /*  See armreg.h for CPU_ID_xxx defines.  */  /*  See armreg.h for CPU_ID_xxx defines.  */
36    
37    /*  TODO: Refactor these flags  */
38    
39  /*  Flags:  */  /*  Flags:  */
40  #define ARM_NO_MMU              1  #define ARM_NO_MMU              1
41  #define ARM_DUAL_ENDIAN         2  #define ARM_DUAL_ENDIAN         2
42    #define ARM_XSCALE              4
43    
44  #include "armreg.h"  #include "armreg.h"
45    
# Line 82  Line 85 
85          { "IXP1200",    CPU_ID_IXP1200, 0,              14, 1, 14, 1 }, \          { "IXP1200",    CPU_ID_IXP1200, 0,              14, 1, 14, 1 }, \
86          { "80200",      CPU_ID_80200,   0,              14, 1, 14, 1 }, \          { "80200",      CPU_ID_80200,   0,              14, 1, 14, 1 }, \
87          \          \
88          { "PXA210",     CPU_ID_PXA210,  0,              16, 1,  0, 1 }, \          { "PXA210",     CPU_ID_PXA210,  ARM_XSCALE,     16, 1,  0, 1 }, \
89          { "PXA210A",    CPU_ID_PXA210A, 0,              16, 1,  0, 1 }, \          { "PXA210A",    CPU_ID_PXA210A, ARM_XSCALE,     16, 1,  0, 1 }, \
90          { "PXA210B",    CPU_ID_PXA210B, 0,              16, 1,  0, 1 }, \          { "PXA210B",    CPU_ID_PXA210B, ARM_XSCALE,     16, 1,  0, 1 }, \
91          { "PXA210C",    CPU_ID_PXA210C, 0,              16, 1,  0, 1 }, \          { "PXA210C",    CPU_ID_PXA210C, ARM_XSCALE,     16, 1,  0, 1 }, \
92          { "PXA250",     CPU_ID_PXA250,  0,              16, 1,  0, 1 }, \          { "PXA250",     CPU_ID_PXA250,  ARM_XSCALE,     16, 1,  0, 1 }, \
93          { "PXA250A",    CPU_ID_PXA250A, 0,              16, 1,  0, 1 }, \          { "PXA250A",    CPU_ID_PXA250A, ARM_XSCALE,     16, 1,  0, 1 }, \
94          { "PXA250B",    CPU_ID_PXA250B, 0,              16, 1,  0, 1 }, \          { "PXA250B",    CPU_ID_PXA250B, ARM_XSCALE,     16, 1,  0, 1 }, \
95          { "PXA250C",    CPU_ID_PXA250C, 0,              16, 1,  0, 1 }, \          { "PXA250C",    CPU_ID_PXA250C, ARM_XSCALE,     16, 1,  0, 1 }, \
96          { "PXA27X",     CPU_ID_PXA27X,  0,              16, 1,  0, 1 }, \          { "PXA27X",     CPU_ID_PXA27X,  ARM_XSCALE,     16, 1,  0, 1 }, \
97          \          \
98          { "IXP425_255", CPU_ID_IXP425_266,      0,      14, 1, 14, 1 }, \          { "IXP425_255", CPU_ID_IXP425_266,ARM_XSCALE,   15, 1, 15, 1 }, \
99          { "IXP425_400", CPU_ID_IXP425_400,      0,      14, 1, 14, 1 }, \          { "IXP425_400", CPU_ID_IXP425_400,ARM_XSCALE,   15, 1, 15, 1 }, \
100          { "IXP425_533", CPU_ID_IXP425_533,      0,      14, 1, 14, 1 }, \          { "IXP425_533", CPU_ID_IXP425_533,ARM_XSCALE,   15, 1, 15, 1 }, \
101          \          \
102          { "80219_400",  CPU_ID_80219_400,0,             14, 1, 14, 1 }, \          { "80219_400",  CPU_ID_80219_400,ARM_XSCALE,    15, 1, 15, 1 }, \
103          { "80219_600",  CPU_ID_80219_600,0,             14, 1, 14, 1 }, \          { "80219_600",  CPU_ID_80219_600,ARM_XSCALE,    15, 1, 15, 1 }, \
104          { "80321_400",  CPU_ID_80321_400,0,             14, 1, 14, 1 }, \          { "80321_400",  CPU_ID_80321_400,ARM_XSCALE,    15, 1, 15, 1 }, \
105          { "80321_400_B0",CPU_ID_80321_400_B0,0,         14, 1, 14, 1 }, \          { "80321_400_B0",CPU_ID_80321_400_B0,ARM_XSCALE,15, 1, 15, 1 }, \
106          { "80321_600",  CPU_ID_80321_600,0,             14, 1, 14, 1 }, \          { "80321_600",  CPU_ID_80321_600,ARM_XSCALE,    15, 1, 15, 1 }, \
107          { "80321_600_B0",CPU_ID_80321_600_B0,0,         14, 1, 14, 1 }, \          { "80321_600_B0",CPU_ID_80321_600_B0,ARM_XSCALE,15, 1, 15, 1 }, \
108          \          \
109          { NULL, 0, 0, 0,0, 0,0 } }          { NULL, 0, 0, 0,0, 0,0 } }
110    
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