/[gxemul]/trunk/src/include/alpha_rpb.h
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Contents of /trunk/src/include/alpha_rpb.h

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Revision 12 - (show annotations)
Mon Oct 8 16:18:38 2007 UTC (12 years, 2 months ago) by dpavlin
File MIME type: text/plain
File size: 18718 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628	Continuing the work on the ARM translation engine. end_of_page
		works. Experimenting with load/store translation caches
		(virtual -> physical -> host).
20050629	More ARM stuff (memory access translation cache, mostly). This
		might break a lot of stuff elsewhere, probably some MIPS-
		related translation things.
20050630	Many load/stores are now automatically generated and included
		into cpu_arm_instr.c; 1024 functions in total (!).
		Fixes based on feedback from Alec Voropay: only print 8 hex
		digits instead of 16 in some cases when emulating 32-bit
		machines; similar 8 vs 16 digit fix for breakpoint addresses;
		4Kc has 16 TLB entries, not 48; the MIPS config select1
		register is now printed with "reg ,0".
		Also changing many other occurances of 16 vs 8 digit output.
		Adding cache associativity fields to mips_cpu_types.h; updating
		some other cache fields; making the output of
		mips_cpu_dumpinfo() look nicer.
		Generalizing the bintrans stuff for device accesses to also
		work with the new translation system. (This might also break
		some MIPS things.)
		Adding multi-load/store instructions to the ARM disassembler
		and the translator, and some optimizations of various kinds.
20050701	Adding a simple dev_disk (it can read/write sectors from
		disk images).
20050712	Adding dev_ether (a simple ethernet send/receive device).
		Debugger command "ninstrs" for toggling show_nr_of_instructions
		during runtime.
		Removing the framebuffer logo.
20050713	Continuing on dev_ether.
		Adding a dummy cpu_alpha (again).
20050714	More work on cpu_alpha.
20050715	More work on cpu_alpha. Many instructions work, enough to run
		a simple framebuffer fill test (similar to the ARM test).
20050716	More Alpha stuff.
20050717	Minor updates (Alpha stuff).
20050718	Minor updates (Alpha stuff).
20050719	Generalizing some Alpha instructions.
20050720	More Alpha-related updates.
20050721	Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722	Alpha-related updates: userland stuff (Hello World using
		write() compiled statically for FreeBSD/Alpha runs fine), and
		more instructions are now implemented.
20050723	Fixing ldq_u and stq_u.
		Adding more instructions (conditional moves, masks, extracts,
		shifts).
20050724	More FreeBSD/Alpha userland stuff, and adding some more
		instructions (inserts).
20050725	Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
		Adding a -A command line option to turn off alignment checks
		in some cases (for translated code).
		Trying to remove the old bintrans code which updated the pc
		and nr_of_executed_instructions for every instruction.
20050726	Making another attempt att removing the pc/nr of instructions
		code. This time it worked, huge performance increase for
		artificial test code, but performance loss for real-world
		code :-( so I'm scrapping that code for now.
		Tiny performance increase on Alpha (by using ret instead of
		jmp, to play nice with the Alpha's branch prediction) for the
		old MIPS bintrans backend.
20050727	Various minor fixes and cleanups.
20050728	Switching from a 2-level virtual to host/physical translation
		system for ARM emulation, to a 1-level translation.
		Trying to switch from 2-level to 1-level for the MIPS bintrans
		system as well (Alpha only, so far), but there is at least one
		problem: caches and/or how they work with device mappings.
20050730	Doing the 2-level to 1-level conversion for the i386 backend.
		The cache/device bug is still there for R2K/3K :(
		Various other minor updates (Malta etc).
		The mc146818 clock now updates the UIP bit in a way which works
		better with Linux for at least sgimips and Malta emulation.
		Beginning the work on refactoring the dyntrans system.
20050731	Continuing the dyntrans refactoring.
		Fixing a small but serious host alignment bug in memory_rw.
		Adding support for big-endian load/stores to the i386 bintrans
		backend.
		Another minor i386 bintrans backend update: stores from the
		zero register are now one (or two) loads shorter.
		The slt and sltu instructions were incorrectly implemented for
		the i386 backend; only using them for 32-bit mode for now.
20050801	Continuing the dyntrans refactoring.
		Cleanup of the ns16550 serial controller (removing unnecessary
		code).
		Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
		Alec Voropay for Linux/Malta.
20050802	More cleanup/refactoring of the dyntrans subsystem: adding
		phys_page pointers to the lookup tables, for quick jumps
		between translated pages.
		Better fix for the ns16550 device (but still no real FIFO
		functionality).
		Converting cpu_ppc to the new dyntrans system. This means that
		I will have to start from scratch with implementing each
		instruction, and figure out how to implement dual 64/32-bit
		modes etc.
		Removing the URISC CPU family, because it was useless.
20050803	When selecting a machine type, the main type can now be omitted
		if the subtype name is unique. (I.e. -E can be omitted.)
		Fixing a dyntrans/device update bug. (Writes to offset 0 of
		a device could sometimes go unnoticed.)
		Adding an experimental "instruction combination" hack for
		ARM for memset-like byte fill loops.
20050804	Minor progress on cpu_alpha and related things.
		Finally fixing the MIPS dmult/dmultu bugs.
		Fixing some minor TODOs.
20050805	Generalizing the 8259 PIC. It now also works with Cobalt
		and evbmips emulation, in addition to the x86 hack.
		Finally converting the ns16550 device to use devinit.
		Continuing the work on the dyntrans system. Thinking about
		how to add breakpoints.
20050806	More dyntrans updates. Breakpoints seem to work now.
20050807	Minor updates: cpu_alpha and related things; removing
		dev_malta (as it isn't used any more).
		Dyntrans: working on general "show trace tree" support.
		The trace tree stuff now works with both the old MIPS code and
		with newer dyntrans modes. :)
		Continuing on Alpha-related stuff (trying to get *BSD to boot
		a bit further, adding more instructions, etc).
20050808	Adding a dummy IA64 cpu family, and continuing the refactoring
		of the dyntrans system.
		Removing the regression test stuff, because it was more or
		less useless.
		Adding loadlinked/storeconditional type instructions to the
		Alpha emulation. (Needed for Linux/alpha. Not very well tested
		yet.)
20050809	The function call trace tree now prints a per-function nr of
		arguments. (Semi-meaningless, since that data isn't read yet
		from the ELFs; some hardcoded symbols such as memcpy() and
		strlen() work fine, though.)
		More dyntrans refactoring; taking out more of the things that
		are common to all cpu families.
20050810	Working on adding support for "dual mode" for PPC dyntrans
		(i.e. both 64-bit and 32-bit modes).
		(Re)adding some simple PPC instructions.
20050811	Adding a dummy M68K cpu family. The dyntrans system isn't ready
		for variable-length ISAs yet, so it's completely bogus so far.
		Re-adding more PPC instructions.
		Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
		kernels to be loaded.
		Beginning to add PPC loads/stores. So far they only work in
		32-bit mode.
20050812	The configure file option "add_remote" now accepts symbolic
		host names, in addition to numeric IPv4 addresses.
		Re-adding more PPC instructions.
20050814	Continuing to port back more PPC instructions.
		Found and fixed the cache/device write-update bug for 32-bit
		MIPS bintrans. :-)
		Triggered a really weird and annoying bug in Compaq's C
		compiler; ccc sometimes outputs code which loads from an
		address _before_ checking whether the pointer was NULL or not.
		(I'm not sure how to handle this problem.)
20050815	Removing all of the old x86 instruction execution code; adding
		a new (dummy) dyntrans module for x86.
		Taking the first steps to extend the dyntrans system to support
		variable-length instructions.
		Slowly preparing for the next release.
20050816	Adding a dummy SPARC cpu module.
		Minor updates (documentation etc) for the release.

==============  RELEASE 0.3.5  ==============


1 /* $NetBSD: rpb.h,v 1.39.18.1 2002/07/29 14:45:46 lukem Exp $ */
2
3 /*
4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Keith Bostic, Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
22 * School of Computer Science
23 * Carnegie Mellon University
24 * Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30 /*
31 * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual,
32 * EK-D3SYS-PM.B01.
33 */
34
35 /*
36 * HWRPB (Hardware Restart Parameter Block).
37 */
38 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */
39
40 /* GXemul: */
41 #define CTB_ADDR (HWRPB_ADDR + 0x1000)
42 #define CRB_ADDR (HWRPB_ADDR + 0x1400)
43
44 #ifndef ASSEMBLER
45 struct rpb {
46 u_int64_t rpb_phys; /* 0: HWRPB phys. address. */
47 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */
48 u_int64_t rpb_version; /* 10 */
49 u_int64_t rpb_size; /* 18: HWRPB size in bytes */
50 u_int64_t rpb_primary_cpu_id; /* 20 */
51 u_int64_t rpb_page_size; /* 28: (8192) */
52 u_int32_t rpb_phys_addr_size; /* 30: physical address size */
53 u_int32_t rpb_extended_va_size; /* 34: extended VA size (4L) */
54 u_int64_t rpb_max_asn; /* 38: (16) */
55 char rpb_ssn[16]; /* 40: only first 10 valid */
56
57 #define ST_ADU 1 /* Alpha Demo. Unit (?) */
58 #define ST_DEC_4000 2 /* "Cobra" */
59 #define ST_DEC_7000 3 /* "Ruby" */
60 #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */
61 #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */
62 #define ST_DEC_3000_300 7 /* "Pelican" (TC) */
63 #define ST_AVALON_A12 8 /* XXX Avalon Multicomputer */
64 #define ST_DEC_2100_A500 9 /* "Sable" */
65 #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME) */
66 #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */
67 #define ST_DEC_21000 12 /* "TurboLaser" (PCI/EISA) */
68 #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */
69 #define ST_DEC_MUSTANG 14 /* "Mustang" */
70 #define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */
71 #define ST_DEC_1000 17 /* "Mikasa" (PCI/EISA) */
72 #define ST_EB66 19 /* EB66 (PCI/ISA?) */
73 #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */
74 #define ST_ALPHABOOK1 21 /* Alphabook1 */
75 #define ST_DEC_4100 22 /* "Rawhide" (PCI/EISA) */
76 #define ST_DEC_EV45_PBP 23 /* "Lego" K2 Passive SBC */
77 #define ST_DEC_2100A_A500 24 /* "Lynx" */
78 #define ST_EB164 26 /* EB164 (PCI/ISA) */
79 #define ST_DEC_1000A 27 /* "Noritake" (PCI/EISA)*/
80 #define ST_DEC_ALPHAVME_224 28 /* "Cortex" */
81 #define ST_DEC_550 30 /* "Miata" (PCI/ISA) */
82 #define ST_DEC_EV56_PBP 32 /* "Takara" */
83 #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME) */
84 #define ST_DEC_6600 34 /* EV6-Tsunami based systems */
85 #define ST_DEC_WILDFIRE 35 /* "Wildfire" */
86 #define ST_DEC_CUSCO 36 /* "CUSCO" */
87 #define ST_DEC_EIGER 37 /* "Eiger" */
88 #define ST_DEC_TITAN 38 /* "Titan" */
89
90 /* Alpha Processor, Inc. systypes */
91 #define ST_API_NAUTILUS 201 /* EV6-AMD 751 UP1000 */
92
93 u_int64_t rpb_type; /* 50: */
94
95 #define SV_MPCAP 0x00000001 /* multiprocessor capable */
96
97 #define SV_CONSOLE 0x0000001e /* console hardware mask */
98 #define SV_CONSOLE_DETACHED 0x00000002
99 #define SV_CONSOLE_EMBEDDED 0x00000004
100
101 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */
102 #define SV_PF_UNITED 0x00000020
103 #define SV_PF_SEPARATE 0x00000040
104 #define SV_PF_BBACKUP 0x00000060
105 #define SV_PF_ACTION 0x00000100 /* powerfail restart */
106
107 #define SV_GRAPHICS 0x00000200 /* graphic engine present */
108
109 #define SV_ST_MASK 0x0000fc00 /* system type mask */
110 #define SV_ST_RESERVED 0x00000000 /* RESERVED */
111
112 /*
113 * System types for the DEC 3000/500 (Flamingo) Family
114 */
115 #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */
116 #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */
117 #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */
118 #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */
119 #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */
120 #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */
121 #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */
122 #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */
123
124 /*
125 * System types for ???
126 */
127 #define SV_ST_SABLE 0x00000400 /* Sable (???) */
128
129 /*
130 * System types for the DEC 3000/300 (Pelican) Family
131 */
132 #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */
133 #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */
134 #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */
135 #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */
136
137 /*
138 * System types for the AlphaStation Family
139 */
140 #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */
141 #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */
142 #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */
143 #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */
144 #define SV_ST_AVANTI_4_266 0x00002000
145 #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */
146 #define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */
147
148 #define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */
149
150 /*
151 * System types for the AXPvme Family
152 */
153 #define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */
154 #define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */
155 #define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */
156 #define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */
157 #define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */
158 #define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */
159 #define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */
160
161 /*
162 * System types for the EB164 Family
163 */
164 #define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */
165 #define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */
166 #define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */
167 #define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */
168 #define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */
169 #define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */
170 #define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */
171 #define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */
172 #define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */
173 #define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */
174 #define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */
175 #define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */
176 #define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */
177 #define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */
178 #define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */
179
180 /*
181 * System types for the Digital Personal Workstation (Miata) Family
182 * XXX These are not very complete!
183 */
184 #define SV_ST_MIATA_1_5 0x00004c00 /* Miata 1.5 */
185
186 u_int64_t rpb_variation; /* 58 */
187
188 char rpb_revision[8]; /* 60; only first 4 valid */
189 u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */
190 u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */
191 u_int64_t rpb_vptb; /* 78: */
192 u_int64_t rpb_reserved_arch; /* 80: */
193 u_int64_t rpb_tbhint_off; /* 88: */
194 u_int64_t rpb_pcs_cnt; /* 90: */
195 u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */
196 u_int64_t rpb_pcs_off; /* A0: offset to pcs info */
197 u_int64_t rpb_ctb_cnt; /* A8: console terminal */
198 u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */
199 u_int64_t rpb_ctb_off; /* B8: offset to ctb */
200 u_int64_t rpb_crb_off; /* C0: offset to crb */
201 u_int64_t rpb_memdat_off; /* C8: memory data offset */
202 u_int64_t rpb_condat_off; /* D0: config data offset */
203 u_int64_t rpb_fru_off; /* D8: FRU table offset */
204 u_int64_t rpb_save_term; /* E0: terminal save */
205 u_int64_t rpb_save_term_val; /* E8: */
206 u_int64_t rpb_rest_term; /* F0: terminal restore */
207 u_int64_t rpb_rest_term_val; /* F8: */
208 u_int64_t rpb_restart; /* 100: restart */
209 u_int64_t rpb_restart_val; /* 108: */
210 u_int64_t rpb_reserve_os; /* 110: */
211 u_int64_t rpb_reserve_hw; /* 118: */
212 u_int64_t rpb_checksum; /* 120: HWRPB checksum */
213 u_int64_t rpb_rxrdy; /* 128: receive ready */
214 u_int64_t rpb_txrdy; /* 130: transmit ready */
215 u_int64_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */
216 u_int64_t rpb_tbhint[8]; /* 140: TB hint block */
217 };
218
219 #define LOCATE_PCS(h,cpunumber) ((struct pcs *) \
220 ((char *)(h) + (h)->rpb_pcs_off + ((cpunumber) * (h)->rpb_pcs_size)))
221
222 /*
223 * PCS: Per-CPU information.
224 */
225 struct pcs {
226 u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */
227
228 #define PCS_BIP 0x000001 /* boot in progress */
229 #define PCS_RC 0x000002 /* restart possible */
230 #define PCS_PA 0x000004 /* processor available */
231 #define PCS_PP 0x000008 /* processor present */
232 #define PCS_OH 0x000010 /* user halted */
233 #define PCS_CV 0x000020 /* context valid */
234 #define PCS_PV 0x000040 /* PALcode valid */
235 #define PCS_PMV 0x000080 /* PALcode memory valid */
236 #define PCS_PL 0x000100 /* PALcode loaded */
237
238 #define PCS_HALT_REQ 0xff0000 /* halt request mask */
239 #define PCS_HALT_DEFAULT 0x000000
240 #define PCS_HALT_SAVE_EXIT 0x010000
241 #define PCS_HALT_COLD_BOOT 0x020000
242 #define PCS_HALT_WARM_BOOT 0x030000
243 #define PCS_HALT_STAY_HALTED 0x040000
244 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */
245 u_int64_t pcs_flags; /* 80: */
246
247 u_int64_t pcs_pal_memsize; /* 88: PAL memory size */
248 u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */
249 u_int64_t pcs_pal_memaddr; /* 98: PAL memory addr */
250 u_int64_t pcs_pal_scraddr; /* A0: PAL scratch addr */
251 struct {
252 int /* TODO/NOTE: should be uint64_t */
253 minorrev : 8, /* alphabetic char 'a' - 'z' */
254 majorrev : 8, /* alphabetic char 'a' - 'z' */
255 #define PAL_TYPE_STANDARD 0
256 #define PAL_TYPE_VMS 1
257 #define PAL_TYPE_OSF1 2
258 pal_type : 8, /* PALcode type:
259 * 0 == standard
260 * 1 == OpenVMS
261 * 2 == OSF/1
262 * 3-127 DIGITAL reserv.
263 * 128-255 non-DIGITAL reserv.
264 */
265 sbz1 : 8,
266 compatibility : 16, /* Compatibility revision */
267 proc_cnt : 16; /* Processor count */
268 } pcs_pal_rev; /* A8: */
269 #define pcs_minorrev pcs_pal_rev.minorrev
270 #define pcs_majorrev pcs_pal_rev.majorrev
271 #define pcs_pal_type pcs_pal_rev.pal_type
272 #define pcs_compatibility pcs_pal_rev.compatibility
273 #define pcs_proc_cnt pcs_pal_rev.proc_cnt
274
275 u_int64_t pcs_proc_type; /* B0: processor type */
276
277 #define PCS_PROC_EV3 1 /* EV3 */
278 #define PCS_PROC_EV4 2 /* EV4: 21064 */
279 #define PCS_PROC_SIMULATION 3 /* Simulation */
280 #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */
281 #define PCS_PROC_EV5 5 /* EV5: 21164 */
282 #define PCS_PROC_EV45 6 /* EV45: 21064A */
283 #define PCS_PROC_EV56 7 /* EV56: 21164A */
284 #define PCS_PROC_EV6 8 /* EV6: 21264 */
285 #define PCS_PROC_PCA56 9 /* PCA56: 21164PC */
286 #define PCS_PROC_PCA57 10 /* PCA57: 21164?? */
287 #define PCS_PROC_EV67 11 /* EV67: 21246A */
288 #define PCS_PROC_EV68CB 12 /* EV68CB: 21264C */
289 #define PCS_PROC_EV68AL 13 /* EV68AL: 21264B */
290 #define PCS_PROC_EV68CX 14 /* EV68CX: 21264D */
291
292 #define PCS_CPU_MAJORTYPE(p) ((p)->pcs_proc_type & 0xffffffff)
293 #define PCS_CPU_MINORTYPE(p) ((p)->pcs_proc_type >> 32)
294
295 /* Minor number interpretation is processor specific. See cpu.c. */
296
297 u_int64_t pcs_proc_var; /* B8: processor variation. */
298
299 #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */
300 #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */
301 #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */
302 #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */
303
304 char pcs_proc_revision[8]; /* C0: only first 4 valid */
305 char pcs_proc_sn[16]; /* C8: only first 10 valid */
306 u_int64_t pcs_machcheck; /* D8: mach chk phys addr. */
307 u_int64_t pcs_machcheck_len; /* E0: length in bytes */
308 u_int64_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */
309 u_int64_t pcs_halt_pc; /* F0: halt PC */
310 u_int64_t pcs_halt_ps; /* F8: halt PS */
311 u_int64_t pcs_halt_r25; /* 100: halt argument list */
312 u_int64_t pcs_halt_r26; /* 108: halt return addr list */
313 u_int64_t pcs_halt_r27; /* 110: halt procedure value */
314
315 #define PCS_HALT_RESERVED 0
316 #define PCS_HALT_POWERUP 1
317 #define PCS_HALT_CONSOLE_HALT 2
318 #define PCS_HALT_CONSOLE_CRASH 3
319 #define PCS_HALT_KERNEL_MODE 4
320 #define PCS_HALT_KERNEL_STACK_INVALID 5
321 #define PCS_HALT_DOUBLE_ERROR_ABORT 6
322 #define PCS_HALT_SCBB 7
323 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */
324 u_int64_t pcs_halt_reason; /* 118: */
325
326 u_int64_t pcs_reserved_soft; /* 120: preserved software */
327
328 struct { /* 128: inter-console buffers */
329 u_int iccb_rxlen;
330 u_int iccb_txlen;
331 char iccb_rxbuf[80];
332 char iccb_txbuf[80];
333 } pcs_iccb;
334
335 #define PALvar_reserved 0
336 #define PALvar_OpenVMS 1
337 #define PALvar_OSF1 2
338 u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */
339
340 u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */
341 };
342
343 /*
344 * CTB: Console Terminal Block
345 */
346 struct ctb {
347 u_int64_t ctb_type; /* 0: CTB type */
348 u_int64_t ctb_unit; /* 8: */
349 u_int64_t ctb_reserved; /* 16: */
350 u_int64_t ctb_len; /* 24: bytes of info */
351 u_int64_t ctb_ipl; /* 32: console ipl level */
352 u_int64_t ctb_tintr_vec; /* 40: transmit vec (0x800) */
353 u_int64_t ctb_rintr_vec; /* 48: receive vec (0x800) */
354
355 #define CTB_NONE 0x00 /* no console present */
356 #define CTB_SERVICE 0x01 /* service processor */
357 #define CTB_PRINTERPORT 0x02 /* printer port on the SCC */
358 #define CTB_GRAPHICS 0x03 /* graphics device */
359 #define CTB_TYPE4 0x04 /* type 4 CTB */
360 #define CTB_NETWORK 0xC0 /* network device */
361 u_int64_t ctb_term_type; /* 56: terminal type */
362
363 u_int64_t ctb_keybd_type; /* 64: keyboard nationality */
364 u_int64_t ctb_keybd_trans; /* 72: trans. table addr */
365 u_int64_t ctb_keybd_map; /* 80: map table addr */
366 u_int64_t ctb_keybd_state; /* 88: keyboard flags */
367 u_int64_t ctb_keybd_last; /* 96: last key entered */
368 u_int64_t ctb_font_us; /* 104: US font table addr */
369 u_int64_t ctb_font_mcs; /* 112: MCS font table addr */
370 u_int64_t ctb_font_width; /* 120: font width, height */
371 u_int64_t ctb_font_height; /* 128: in pixels */
372 u_int64_t ctb_mon_width; /* 136: monitor width, height */
373 u_int64_t ctb_mon_height; /* 144: in pixels */
374 u_int64_t ctb_dpi; /* 152: monitor dots per inch */
375 u_int64_t ctb_planes; /* 160: # of planes */
376 u_int64_t ctb_cur_width; /* 168: cursor width, height */
377 u_int64_t ctb_cur_height; /* 176: in pixels */
378 u_int64_t ctb_head_cnt; /* 184: # of heads */
379 u_int64_t ctb_opwindow; /* 192: opwindow on screen */
380 u_int64_t ctb_head_offset; /* 200: offset to head info */
381 u_int64_t ctb_putchar; /* 208: output char to TURBO */
382 u_int64_t ctb_io_state; /* 216: I/O flags */
383 u_int64_t ctb_listen_state; /* 224: listener flags */
384 u_int64_t ctb_xaddr; /* 232: extended info addr */
385 u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */
386 u_int64_t ctb_server_off; /* 256: offset to server info */
387 u_int64_t ctb_line_off; /* 264: line parameter offset */
388 u_int8_t ctb_csd; /* 272: console specific data */
389 };
390
391 struct ctb_tt {
392 u_int64_t ctb_type; /* 0: CTB type */
393 u_int64_t ctb_unit; /* 8: console unit */
394 u_int64_t ctb_reserved; /* 16: reserved */
395 u_int64_t ctb_length; /* 24: length */
396 u_int64_t ctb_csr; /* 32: address */
397 u_int64_t ctb_tivec; /* 40: Tx intr vector */
398 u_int64_t ctb_rivec; /* 48: Rx intr vector */
399 u_int64_t ctb_baud; /* 56: baud rate */
400 u_int64_t ctb_put_sts; /* 64: PUTS status */
401 u_int64_t ctb_get_sts; /* 72: GETS status */
402 u_int64_t ctb_reserved0; /* 80: reserved */
403 };
404
405 /*
406 * Format of the Console Terminal Block Type 4 `turboslot' field:
407 *
408 * 63 40 39 32 31 24 23 16 15 8 7 0
409 * | reserved | channel | hose | bus type | bus | slot|
410 */
411 #define CTB_TURBOSLOT_CHANNEL(x) (((x) >> 32) & 0xff)
412 #define CTB_TURBOSLOT_HOSE(x) (((x) >> 24) & 0xff)
413 #define CTB_TURBOSLOT_TYPE(x) (((x) >> 16) & 0xff)
414 #define CTB_TURBOSLOT_BUS(x) (((x) >> 8) & 0xff)
415 #define CTB_TURBOSLOT_SLOT(x) ((x) & 0xff)
416
417 #define CTB_TURBOSLOT_TYPE_TC 0 /* TURBOchannel */
418 #define CTB_TURBOSLOT_TYPE_ISA 1 /* ISA */
419 #define CTB_TURBOSLOT_TYPE_EISA 2 /* EISA */
420 #define CTB_TURBOSLOT_TYPE_PCI 3 /* PCI */
421
422 /*
423 * CRD: Console Routine Descriptor
424 */
425 struct crd {
426 int64_t descriptor;
427 u_int64_t entry_va;
428 };
429
430 /*
431 * CRB: Console Routine Block
432 */
433 struct crb {
434 /* struct crd * */
435 u_int64_t crb_v_dispatch; /* 0: virtual dispatch addr */
436 u_int64_t crb_p_dispatch; /* 8: phys dispatch addr */
437 /* struct crd * */
438 u_int64_t crb_v_fixup; /* 10: virtual fixup addr */
439 u_int64_t crb_p_fixup; /* 18: phys fixup addr */
440 u_int64_t crb_map_cnt; /* 20: phys/virt map entries */
441 u_int64_t crb_page_cnt; /* 28: pages to be mapped */
442 };
443
444 /*
445 * MDDT: Memory Data Descriptor Table
446 */
447 struct mddt {
448 int64_t mddt_cksum; /* 0: 7-N checksum */
449 u_int64_t mddt_physaddr; /* 8: bank config addr
450 * IMPLEMENTATION SPECIFIC
451 */
452 u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */
453 struct mddt_cluster {
454 u_int64_t mddt_pfn; /* 0: starting PFN */
455 u_int64_t mddt_pg_cnt; /* 8: 8KB page count */
456 u_int64_t mddt_pg_test; /* 10: tested page count */
457 u_int64_t mddt_v_bitaddr; /* 18: bitmap virt addr */
458 u_int64_t mddt_p_bitaddr; /* 20: bitmap phys addr */
459 int64_t mddt_bit_cksum; /* 28: bitmap checksum */
460
461 #define MDDT_NONVOLATILE 0x10 /* cluster is non-volatile */
462 #define MDDT_PALCODE 0x01 /* console and PAL only */
463 #define MDDT_SYSTEM 0x00 /* system software only */
464 #define MDDT_mbz 0xfffffffffffffffc /* 2:63 -- must be zero */
465 int64_t mddt_usage; /* 30: bitmap permissions */
466 } mddt_clusters[1]; /* variable length array */
467 };
468
469 /*
470 * DSR: Dynamic System Recognition. We're interested in the sysname
471 * offset. The data pointed to by sysname is:
472 *
473 * [8 bytes: length of system name][N bytes: system name string]
474 *
475 * The system name string is NUL-terminated.
476 */
477 struct dsrdb {
478 int64_t dsr_smm; /* 0: SMM number */
479 u_int64_t dsr_lurt_off; /* 8: LURT table offset */
480 u_int64_t dsr_sysname_off; /* 16: offset to sysname */
481 };
482
483 /*
484 * The DSR appeared in version 5 of the HWRPB.
485 */
486 #define HWRPB_DSRDB_MINVERS 5
487
488 #ifdef _KERNEL
489 extern int cputype;
490 extern struct rpb *hwrpb;
491 #endif
492
493 #endif /* ASSEMBLER */

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