/[gxemul]/trunk/src/include/alpha_rpb.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Annotation of /trunk/src/include/alpha_rpb.h

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Revision 32 - (hide annotations)
Mon Oct 8 16:20:58 2007 UTC (13 years ago) by dpavlin
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File size: 18939 byte(s)
++ trunk/HISTORY	(local)
$Id: HISTORY,v 1.1421 2006/11/06 05:32:37 debug Exp $
20060816	Adding a framework for emulated/virtual timers (src/timer.c),
		using only setitimer().
		Rewriting the mc146818 to use the new timer framework.
20060817	Adding a call to gettimeofday() every now and then (once every
		second, at the moment) to resynch the timer if it drifts.
		Beginning to convert the ISA timer interrupt mechanism (8253
		and 8259) to use the new timer framework.
		Removing the -I command line option.
20060819	Adding the -I command line option again, with new semantics.
		Working on Footbridge timer interrupts; NetBSD/NetWinder and
		NetBSD/CATS now run at correct speed, but unfortunately with
		HUGE delays during bootup.
20060821	Some minor m68k updates. Adding the first instruction: nop. :)
		Minor Alpha emulation updates.
20060822	Adding a FreeBSD development specific YAMON environment
		variable ("khz") (as suggested by Bruce M. Simpson).
		Moving YAMON environment variable initialization from
		machine_evbmips.c into promemul/yamon.c, and adding some more
		variables.
		Continuing on the LCA PCI bus controller (for Alpha machines).
20060823	Continuing on the timer stuff: experimenting with MIPS count/
		compare interrupts connected to the timer framework.
20060825	Adding bogus SCSI commands 0x51 (SCSICDROM_READ_DISCINFO) and
		0x52 (SCSICDROM_READ_TRACKINFO) to the SCSI emulation layer,
		to allow NetBSD/pmax 4.0_BETA to be installed from CDROM.
		Minor updates to the LCA PCI controller.
20060827	Implementing a CHIP8 cpu mode, and a corresponding CHIP8
		machine, for fun. Disassembly support for all instructions,
		and most of the common instructions have been implemented: mvi,
		mov_imm, add_imm, jmp, rand, cls, sprite, skeq_imm, jsr,
		skne_imm, bcd, rts, ldr, str, mov, or, and, xor, add, sub,
		font, ssound, sdelay, gdelay, bogus skup/skpr, skeq, skne.
20060828	Beginning to convert the CHIP8 cpu in the CHIP8 machine to a
		(more correct) RCA 180x cpu. (Disassembly for all 1802
		instructions has been implemented, but no execution yet, and
		no 1805 extended instructions.)
20060829	Minor Alpha emulation updates.
20060830	Beginning to experiment a little with PCI IDE for SGI O2.
		Fixing the cursor key mappings for MobilePro 770 emulation.
		Fixing the LK201 warning caused by recent NetBSD/pmax.
		The MIPS R41xx standby, suspend, and hibernate instructions now
		behave like the RM52xx/MIPS32/MIPS64 wait instruction.
		Fixing dev_wdc so it calculates correct (64-bit) offsets before
		giving them to diskimage_access().
20060831	Continuing on Alpha emulation (OSF1 PALcode).
20060901	Minor Alpha updates; beginning on virtual memory pagetables.
		Removed the limit for max nr of devices (in preparation for
		allowing devices' base addresses to be changed during runtime).
		Adding a hack for MIPS [d]mfc0 select 0 (except the count
		register), so that the coproc register is simply copied.
		The MIPS suspend instruction now exits the emulator, instead
		of being treated as a wait instruction (this causes NetBSD/
		hpcmips to get correct 'halt' behavior).
		The VR41xx RTC now returns correct time.
		Connecting the VR41xx timer to the timer framework (fixed at
		128 Hz, for now).
		Continuing on SPARC emulation, adding more instructions:
		restore, ba_xcc, ble. The rectangle drawing demo works :)
		Removing the last traces of the old ENABLE_CACHE_EMULATION
		MIPS stuff (not usable with dyntrans anyway).
20060902	Splitting up src/net.c into several smaller files in its own
		subdirectory (src/net/).
20060903	Cleanup of the files in src/net/, to make them less ugly.
20060904	Continuing on the 'settings' subsystem.
		Minor progress on the SPARC emulation mode.
20060905	Cleanup of various things, and connecting the settings
		infrastructure to various subsystems (emul, machine, cpu, etc).
		Changing the lk201 mouse update routine to not rely on any
		emulated hardware framebuffer cursor coordinates, but instead
		always do (semi-usable) relative movements.
20060906	Continuing on the lk201 mouse stuff. Mouse behaviour with
		multiple framebuffers (which was working in Ultrix) is now
		semi-broken (but it still works, in a way).
		Moving the documentation about networking into its own file
		(networking.html), and refreshing it a bit. Adding an example
		of how to use ethernet frame direct-access (udp_snoop).
20060907	Continuing on the settings infrastructure.
20060908	Minor updates to SH emulation: for 32-bit emulation: delay
		slots and the 'jsr @Rn' instruction. I'm putting 64-bit SH5 on
		ice, for now.
20060909-10	Implementing some more 32-bit SH instructions. Removing the
		64-bit mode completely. Enough has now been implemented to run
		the rectangle drawing demo. :-)
20060912	Adding more SH instructions.
20060916	Continuing on SH emulation (some more instructions: div0u,
		div1, rotcl/rotcr, more mov instructions, dt, braf, sets, sett,
		tst_imm, dmuls.l, subc, ldc_rm_vbr, movt, clrt, clrs, clrmac).
		Continuing on the settings subsystem (beginning on reading/
		writing settings, removing bugs, and connecting more cpus to
		the framework).
20060919	More work on SH emulation; adding an ldc banked instruction,
		and attaching a 640x480 framebuffer to the Dreamcast machine
		mode (NetBSD/dreamcast prints the NetBSD copyright banner :-),
		and then panics).
20060920	Continuing on the settings subsystem.
20060921	Fixing the Footbridge timer stuff so that NetBSD/cats and
		NetBSD/netwinder boot up without the delays.
20060922	Temporarily hardcoding MIPS timer interrupt to 100 Hz. With
		'wait' support disabled, NetBSD/malta and Linux/malta run at
		correct speed.
20060923	Connecting dev_gt to the timer framework, so that NetBSD/cobalt
		runs at correct speed.
		Moving SH4-specific memory mapped registers into its own
		device (dev_sh4.c).
		Running with -N now prints "idling" instead of bogus nr of
		instrs/second (which isn't valid anyway) while idling.
20060924	Algor emulation should now run at correct speed.
		Adding disassembly support for some MIPS64 revision 2
		instructions: ext, dext, dextm, dextu.
20060926	The timer framework now works also when the MIPS wait
		instruction is used.
20060928	Re-implementing checks for coprocessor availability for MIPS
		cop0 instructions. (Thanks to Carl van Schaik for noticing the
		lack of cop0 availability checks.)
20060929	Implementing an instruction combination hack which treats
		NetBSD/pmax' idle loop as a wait-like instruction.
20060930	The ENTRYHI_R_MASK was missing in (at least) memory_mips_v2p.c,
		causing TLB lookups to sometimes succeed when they should have
		failed. (A big thank you to Juli Mallett for noticing the
		problem.)
		Adding disassembly support for more MIPS64 revision 2 opcodes
		(seb, seh, wsbh, jalr.hb, jr.hb, synci, ins, dins, dinsu,
		dinsm, dsbh, dshd, ror, dror, rorv, drorv, dror32). Also
		implementing seb, seh, dsbh, dshd, and wsbh.
		Implementing an instruction combination hack for Linux/pmax'
		idle loop, similar to the NetBSD/pmax case.
20061001	Changing the NetBSD/sgimips install instructions to extract
		files from an iso image, instead of downloading them via ftp.
20061002	More-than-31-bit userland addresses in memory_mips_v2p.c were
		not actually working; applying a fix from Carl van Schaik to
		enable them to work + making some other updates (adding kuseg
		support).
		Fixing hpcmips (vr41xx) timer initialization.
		Experimenting with O(n)->O(1) reduction in the MIPS TLB lookup
		loop. Seems to work both for R3000 and non-R3000.
20061003	Continuing a little on SH emulation (adding more control
		registers; mini-cleanup of memory_sh.c).
20061004	Beginning on a dev_rtc, a clock/timer device for the test
		machines; also adding a demo, and some documentation.
		Fixing a bug in SH "mov.w @(disp,pc),Rn" (the result wasn't
		sign-extended), and adding the addc and ldtlb instructions.
20061005	Contining on SH emulation: virtual to physical address
		translation, and a skeleton exception mechanism.
20061006	Adding more SH instructions (various loads and stores, rte,
		negc, muls.w, various privileged register-move instructions).
20061007	More SH instructions: various move instructions, trapa, div0s,
		float, fdiv, ftrc.
		Continuing on dev_rtc; removing the rtc demo.
20061008	Adding a dummy Dreamcast PROM module. (Homebrew Dreamcast
		programs using KOS libs need this.)
		Adding more SH instructions: "stc vbr,rn", rotl, rotr, fsca,
		fmul, fadd, various floating-point moves, etc. A 256-byte
		demo for Dreamcast runs :-)
20061012	Adding the SH "lds Rm,pr" and bsr instructions.
20061013	More SH instructions: "sts fpscr,rn", tas.b, and some more
		floating point instructions, cmp/str, and more moves.
		Adding a dummy dev_pvr (Dreamcast graphics controller).
20061014	Generalizing the expression evaluator (used in the built-in
		debugger) to support parentheses and +-*/%^&|.
20061015	Removing the experimental tlb index hint code in
		mips_memory_v2p.c, since it didn't really have any effect.
20061017	Minor SH updates; adding the "sts pr,Rn", fcmp/gt, fneg,
		frchg, and some other instructions. Fixing missing sign-
		extension in an 8-bit load instruction.
20061019	Adding a simple dev_dreamcast_rtc.
		Implementing memory-mapped access to the SH ITLB/UTLB arrays.
20061021	Continuing on various SH and Dreamcast things: sh4 timers,
		debug messages for dev_pvr, fixing some virtual address
		translation bugs, adding the bsrf instruction.
		The NetBSD/dreamcast GENERIC_MD kernel now reaches userland :)
		Adding a dummy dev_dreamcast_asic.c (not really useful yet).
		Implementing simple support for Store Queues.
		Beginning on the PVR Tile Accelerator.
20061022	Generalizing the PVR framebuffer to support off-screen drawing,
		multiple bit-depths, etc. (A small speed penalty, but most
		likely worth it.)
		Adding more SH instructions (mulu.w, fcmp/eq, fsub, fmac,
		fschg, and some more); correcting bugs in "fsca" and "float".
20061024	Adding the SH ftrv (matrix * vector) instruction. Marcus
		Comstedt's "tatest" example runs :) (wireframe only).
		Correcting disassembly for SH floating point instructions that
		use the xd* registers.
		Adding the SH fsts instruction.
		In memory_device_dyntrans_access(), only the currently used
		range is now invalidated, and not the entire device range.
20061025	Adding a dummy AVR32 cpu mode skeleton.
20061026	Various Dreamcast updates; beginning on a Maple bus controller.
20061027	Continuing on the Maple bus. A bogus Controller, Keyboard, and
		Mouse can now be detected by NetBSD and KOS homebrew programs.
		Cleaning up the SH4 Timer Management Unit, and beginning on
		SH4 interrupts.
		Implementing the Dreamcast SYSASIC.
20061028	Continuing on the SYSASIC.
		Adding the SH fsqrt instruction.
		memory_sh.c now actually scans the ITLB.
		Fixing a bug in dev_sh4.c, related to associative writes into
		the memory-mapped UTLB array. NetBSD/dreamcast now reaches
		userland stably, and prints the "Terminal type?" message :-]
		Implementing enough of the Dreamcast keyboard to make NetBSD
		accept it for input.
		Enabling SuperH for stable (non-development) builds.
		Adding NetBSD/dreamcast to the documentation, although it
		doesn't support root-on-nfs yet.
20061029	Changing usleep(1) calls in the debugger to to usleep(10000)
		(according to Brian Foley, this makes GXemul run better on
		MacOS X).
		Making the Maple "Controller" do something (enough to barely
		interact with dcircus.elf).
20061030-31	Some progress on the PVR. More test programs start running (but
		with strange output).
		Various other SH4-related updates.
20061102	Various Dreamcast and SH4 updates; more KOS demos run now.
20061104	Adding a skeleton dev_mb8696x.c (the Dreamcast's LAN adapter).
20061105	Continuing on the MB8696x; NetBSD/dreamcast detects it as mbe0.
		Testing for the release.

==============  RELEASE 0.4.3  ==============


1 dpavlin 12 /* $NetBSD: rpb.h,v 1.39.18.1 2002/07/29 14:45:46 lukem Exp $ */
2    
3 dpavlin 14 #include <sys/types.h>
4     #include "misc.h"
5    
6 dpavlin 12 /*
7     * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
8     * All rights reserved.
9     *
10     * Author: Keith Bostic, Chris G. Demetriou
11     *
12     * Permission to use, copy, modify and distribute this software and
13     * its documentation is hereby granted, provided that both the copyright
14     * notice and this permission notice appear in all copies of the
15     * software, derivative works or modified versions, and any portions
16     * thereof, and that both notices appear in supporting documentation.
17     *
18     * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
19     * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
20     * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
21     *
22     * Carnegie Mellon requests users of this software to return to
23     *
24     * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
25     * School of Computer Science
26     * Carnegie Mellon University
27     * Pittsburgh PA 15213-3890
28     *
29     * any improvements or extensions that they make and grant Carnegie the
30     * rights to redistribute these changes.
31     */
32    
33     /*
34     * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual,
35     * EK-D3SYS-PM.B01.
36     */
37    
38     /*
39     * HWRPB (Hardware Restart Parameter Block).
40     */
41     #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */
42    
43     /* GXemul: */
44 dpavlin 32 #define PROM_ENTRY_PADDR 0x10000
45     #define PROM_ARGSPACE_PADDR 0x12000
46     #define HWRPB_PADDR 0x14000
47 dpavlin 12 #define CTB_ADDR (HWRPB_ADDR + 0x1000)
48     #define CRB_ADDR (HWRPB_ADDR + 0x1400)
49 dpavlin 24 #define MEMDAT_ADDR (HWRPB_ADDR + 0x1800)
50 dpavlin 32 #define PCS_ADDR (HWRPB_ADDR + 0x1c00)
51 dpavlin 12
52     #ifndef ASSEMBLER
53     struct rpb {
54     u_int64_t rpb_phys; /* 0: HWRPB phys. address. */
55     char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */
56     u_int64_t rpb_version; /* 10 */
57     u_int64_t rpb_size; /* 18: HWRPB size in bytes */
58     u_int64_t rpb_primary_cpu_id; /* 20 */
59     u_int64_t rpb_page_size; /* 28: (8192) */
60     u_int32_t rpb_phys_addr_size; /* 30: physical address size */
61     u_int32_t rpb_extended_va_size; /* 34: extended VA size (4L) */
62     u_int64_t rpb_max_asn; /* 38: (16) */
63     char rpb_ssn[16]; /* 40: only first 10 valid */
64    
65     #define ST_ADU 1 /* Alpha Demo. Unit (?) */
66     #define ST_DEC_4000 2 /* "Cobra" */
67     #define ST_DEC_7000 3 /* "Ruby" */
68     #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */
69     #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */
70     #define ST_DEC_3000_300 7 /* "Pelican" (TC) */
71     #define ST_AVALON_A12 8 /* XXX Avalon Multicomputer */
72     #define ST_DEC_2100_A500 9 /* "Sable" */
73     #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME) */
74     #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */
75     #define ST_DEC_21000 12 /* "TurboLaser" (PCI/EISA) */
76     #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */
77     #define ST_DEC_MUSTANG 14 /* "Mustang" */
78     #define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */
79     #define ST_DEC_1000 17 /* "Mikasa" (PCI/EISA) */
80     #define ST_EB66 19 /* EB66 (PCI/ISA?) */
81     #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */
82     #define ST_ALPHABOOK1 21 /* Alphabook1 */
83     #define ST_DEC_4100 22 /* "Rawhide" (PCI/EISA) */
84     #define ST_DEC_EV45_PBP 23 /* "Lego" K2 Passive SBC */
85     #define ST_DEC_2100A_A500 24 /* "Lynx" */
86     #define ST_EB164 26 /* EB164 (PCI/ISA) */
87     #define ST_DEC_1000A 27 /* "Noritake" (PCI/EISA)*/
88     #define ST_DEC_ALPHAVME_224 28 /* "Cortex" */
89     #define ST_DEC_550 30 /* "Miata" (PCI/ISA) */
90     #define ST_DEC_EV56_PBP 32 /* "Takara" */
91     #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME) */
92     #define ST_DEC_6600 34 /* EV6-Tsunami based systems */
93     #define ST_DEC_WILDFIRE 35 /* "Wildfire" */
94     #define ST_DEC_CUSCO 36 /* "CUSCO" */
95     #define ST_DEC_EIGER 37 /* "Eiger" */
96     #define ST_DEC_TITAN 38 /* "Titan" */
97    
98     /* Alpha Processor, Inc. systypes */
99     #define ST_API_NAUTILUS 201 /* EV6-AMD 751 UP1000 */
100    
101     u_int64_t rpb_type; /* 50: */
102    
103     #define SV_MPCAP 0x00000001 /* multiprocessor capable */
104    
105     #define SV_CONSOLE 0x0000001e /* console hardware mask */
106     #define SV_CONSOLE_DETACHED 0x00000002
107     #define SV_CONSOLE_EMBEDDED 0x00000004
108    
109     #define SV_POWERFAIL 0x000000e0 /* powerfail mask */
110     #define SV_PF_UNITED 0x00000020
111     #define SV_PF_SEPARATE 0x00000040
112     #define SV_PF_BBACKUP 0x00000060
113     #define SV_PF_ACTION 0x00000100 /* powerfail restart */
114    
115     #define SV_GRAPHICS 0x00000200 /* graphic engine present */
116    
117     #define SV_ST_MASK 0x0000fc00 /* system type mask */
118     #define SV_ST_RESERVED 0x00000000 /* RESERVED */
119    
120     /*
121     * System types for the DEC 3000/500 (Flamingo) Family
122     */
123     #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */
124     #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */
125     #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */
126     #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */
127     #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */
128     #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */
129     #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */
130     #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */
131    
132     /*
133     * System types for ???
134     */
135     #define SV_ST_SABLE 0x00000400 /* Sable (???) */
136    
137     /*
138     * System types for the DEC 3000/300 (Pelican) Family
139     */
140     #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */
141     #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */
142     #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */
143     #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */
144    
145     /*
146     * System types for the AlphaStation Family
147     */
148     #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */
149     #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */
150     #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */
151     #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */
152     #define SV_ST_AVANTI_4_266 0x00002000
153     #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */
154     #define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */
155    
156     #define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */
157    
158     /*
159     * System types for the AXPvme Family
160     */
161     #define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */
162     #define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */
163     #define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */
164     #define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */
165     #define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */
166     #define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */
167     #define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */
168    
169     /*
170     * System types for the EB164 Family
171     */
172     #define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */
173     #define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */
174     #define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */
175     #define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */
176     #define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */
177     #define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */
178     #define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */
179     #define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */
180     #define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */
181     #define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */
182     #define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */
183     #define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */
184     #define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */
185     #define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */
186     #define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */
187    
188     /*
189     * System types for the Digital Personal Workstation (Miata) Family
190     * XXX These are not very complete!
191     */
192     #define SV_ST_MIATA_1_5 0x00004c00 /* Miata 1.5 */
193    
194     u_int64_t rpb_variation; /* 58 */
195    
196     char rpb_revision[8]; /* 60; only first 4 valid */
197     u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */
198     u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */
199     u_int64_t rpb_vptb; /* 78: */
200     u_int64_t rpb_reserved_arch; /* 80: */
201     u_int64_t rpb_tbhint_off; /* 88: */
202     u_int64_t rpb_pcs_cnt; /* 90: */
203     u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */
204     u_int64_t rpb_pcs_off; /* A0: offset to pcs info */
205     u_int64_t rpb_ctb_cnt; /* A8: console terminal */
206     u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */
207     u_int64_t rpb_ctb_off; /* B8: offset to ctb */
208     u_int64_t rpb_crb_off; /* C0: offset to crb */
209     u_int64_t rpb_memdat_off; /* C8: memory data offset */
210     u_int64_t rpb_condat_off; /* D0: config data offset */
211     u_int64_t rpb_fru_off; /* D8: FRU table offset */
212     u_int64_t rpb_save_term; /* E0: terminal save */
213     u_int64_t rpb_save_term_val; /* E8: */
214     u_int64_t rpb_rest_term; /* F0: terminal restore */
215     u_int64_t rpb_rest_term_val; /* F8: */
216     u_int64_t rpb_restart; /* 100: restart */
217     u_int64_t rpb_restart_val; /* 108: */
218     u_int64_t rpb_reserve_os; /* 110: */
219     u_int64_t rpb_reserve_hw; /* 118: */
220     u_int64_t rpb_checksum; /* 120: HWRPB checksum */
221     u_int64_t rpb_rxrdy; /* 128: receive ready */
222     u_int64_t rpb_txrdy; /* 130: transmit ready */
223     u_int64_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */
224     u_int64_t rpb_tbhint[8]; /* 140: TB hint block */
225     };
226    
227     #define LOCATE_PCS(h,cpunumber) ((struct pcs *) \
228     ((char *)(h) + (h)->rpb_pcs_off + ((cpunumber) * (h)->rpb_pcs_size)))
229    
230     /*
231     * PCS: Per-CPU information.
232     */
233     struct pcs {
234     u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */
235    
236     #define PCS_BIP 0x000001 /* boot in progress */
237     #define PCS_RC 0x000002 /* restart possible */
238     #define PCS_PA 0x000004 /* processor available */
239     #define PCS_PP 0x000008 /* processor present */
240     #define PCS_OH 0x000010 /* user halted */
241     #define PCS_CV 0x000020 /* context valid */
242     #define PCS_PV 0x000040 /* PALcode valid */
243     #define PCS_PMV 0x000080 /* PALcode memory valid */
244     #define PCS_PL 0x000100 /* PALcode loaded */
245    
246     #define PCS_HALT_REQ 0xff0000 /* halt request mask */
247     #define PCS_HALT_DEFAULT 0x000000
248     #define PCS_HALT_SAVE_EXIT 0x010000
249     #define PCS_HALT_COLD_BOOT 0x020000
250     #define PCS_HALT_WARM_BOOT 0x030000
251     #define PCS_HALT_STAY_HALTED 0x040000
252     #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */
253     u_int64_t pcs_flags; /* 80: */
254    
255     u_int64_t pcs_pal_memsize; /* 88: PAL memory size */
256     u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */
257     u_int64_t pcs_pal_memaddr; /* 98: PAL memory addr */
258     u_int64_t pcs_pal_scraddr; /* A0: PAL scratch addr */
259     struct {
260     int /* TODO/NOTE: should be uint64_t */
261     minorrev : 8, /* alphabetic char 'a' - 'z' */
262     majorrev : 8, /* alphabetic char 'a' - 'z' */
263     #define PAL_TYPE_STANDARD 0
264     #define PAL_TYPE_VMS 1
265     #define PAL_TYPE_OSF1 2
266     pal_type : 8, /* PALcode type:
267     * 0 == standard
268     * 1 == OpenVMS
269     * 2 == OSF/1
270     * 3-127 DIGITAL reserv.
271     * 128-255 non-DIGITAL reserv.
272     */
273     sbz1 : 8,
274     compatibility : 16, /* Compatibility revision */
275     proc_cnt : 16; /* Processor count */
276     } pcs_pal_rev; /* A8: */
277     #define pcs_minorrev pcs_pal_rev.minorrev
278     #define pcs_majorrev pcs_pal_rev.majorrev
279     #define pcs_pal_type pcs_pal_rev.pal_type
280     #define pcs_compatibility pcs_pal_rev.compatibility
281     #define pcs_proc_cnt pcs_pal_rev.proc_cnt
282    
283     u_int64_t pcs_proc_type; /* B0: processor type */
284    
285     #define PCS_PROC_EV3 1 /* EV3 */
286     #define PCS_PROC_EV4 2 /* EV4: 21064 */
287     #define PCS_PROC_SIMULATION 3 /* Simulation */
288     #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */
289     #define PCS_PROC_EV5 5 /* EV5: 21164 */
290     #define PCS_PROC_EV45 6 /* EV45: 21064A */
291     #define PCS_PROC_EV56 7 /* EV56: 21164A */
292     #define PCS_PROC_EV6 8 /* EV6: 21264 */
293     #define PCS_PROC_PCA56 9 /* PCA56: 21164PC */
294     #define PCS_PROC_PCA57 10 /* PCA57: 21164?? */
295     #define PCS_PROC_EV67 11 /* EV67: 21246A */
296     #define PCS_PROC_EV68CB 12 /* EV68CB: 21264C */
297     #define PCS_PROC_EV68AL 13 /* EV68AL: 21264B */
298     #define PCS_PROC_EV68CX 14 /* EV68CX: 21264D */
299    
300     #define PCS_CPU_MAJORTYPE(p) ((p)->pcs_proc_type & 0xffffffff)
301     #define PCS_CPU_MINORTYPE(p) ((p)->pcs_proc_type >> 32)
302    
303     /* Minor number interpretation is processor specific. See cpu.c. */
304    
305     u_int64_t pcs_proc_var; /* B8: processor variation. */
306    
307     #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */
308     #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */
309     #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */
310     #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */
311    
312     char pcs_proc_revision[8]; /* C0: only first 4 valid */
313     char pcs_proc_sn[16]; /* C8: only first 10 valid */
314     u_int64_t pcs_machcheck; /* D8: mach chk phys addr. */
315     u_int64_t pcs_machcheck_len; /* E0: length in bytes */
316     u_int64_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */
317     u_int64_t pcs_halt_pc; /* F0: halt PC */
318     u_int64_t pcs_halt_ps; /* F8: halt PS */
319     u_int64_t pcs_halt_r25; /* 100: halt argument list */
320     u_int64_t pcs_halt_r26; /* 108: halt return addr list */
321     u_int64_t pcs_halt_r27; /* 110: halt procedure value */
322    
323     #define PCS_HALT_RESERVED 0
324     #define PCS_HALT_POWERUP 1
325     #define PCS_HALT_CONSOLE_HALT 2
326     #define PCS_HALT_CONSOLE_CRASH 3
327     #define PCS_HALT_KERNEL_MODE 4
328     #define PCS_HALT_KERNEL_STACK_INVALID 5
329     #define PCS_HALT_DOUBLE_ERROR_ABORT 6
330     #define PCS_HALT_SCBB 7
331     #define PCS_HALT_PTBR 8 /* 9-FF: reserved */
332     u_int64_t pcs_halt_reason; /* 118: */
333    
334     u_int64_t pcs_reserved_soft; /* 120: preserved software */
335    
336     struct { /* 128: inter-console buffers */
337     u_int iccb_rxlen;
338     u_int iccb_txlen;
339     char iccb_rxbuf[80];
340     char iccb_txbuf[80];
341     } pcs_iccb;
342    
343     #define PALvar_reserved 0
344     #define PALvar_OpenVMS 1
345     #define PALvar_OSF1 2
346     u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */
347    
348     u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */
349     };
350    
351     /*
352     * CTB: Console Terminal Block
353     */
354     struct ctb {
355     u_int64_t ctb_type; /* 0: CTB type */
356     u_int64_t ctb_unit; /* 8: */
357     u_int64_t ctb_reserved; /* 16: */
358     u_int64_t ctb_len; /* 24: bytes of info */
359     u_int64_t ctb_ipl; /* 32: console ipl level */
360     u_int64_t ctb_tintr_vec; /* 40: transmit vec (0x800) */
361     u_int64_t ctb_rintr_vec; /* 48: receive vec (0x800) */
362    
363     #define CTB_NONE 0x00 /* no console present */
364     #define CTB_SERVICE 0x01 /* service processor */
365     #define CTB_PRINTERPORT 0x02 /* printer port on the SCC */
366     #define CTB_GRAPHICS 0x03 /* graphics device */
367     #define CTB_TYPE4 0x04 /* type 4 CTB */
368     #define CTB_NETWORK 0xC0 /* network device */
369     u_int64_t ctb_term_type; /* 56: terminal type */
370    
371     u_int64_t ctb_keybd_type; /* 64: keyboard nationality */
372     u_int64_t ctb_keybd_trans; /* 72: trans. table addr */
373     u_int64_t ctb_keybd_map; /* 80: map table addr */
374     u_int64_t ctb_keybd_state; /* 88: keyboard flags */
375     u_int64_t ctb_keybd_last; /* 96: last key entered */
376     u_int64_t ctb_font_us; /* 104: US font table addr */
377     u_int64_t ctb_font_mcs; /* 112: MCS font table addr */
378     u_int64_t ctb_font_width; /* 120: font width, height */
379     u_int64_t ctb_font_height; /* 128: in pixels */
380     u_int64_t ctb_mon_width; /* 136: monitor width, height */
381     u_int64_t ctb_mon_height; /* 144: in pixels */
382     u_int64_t ctb_dpi; /* 152: monitor dots per inch */
383     u_int64_t ctb_planes; /* 160: # of planes */
384     u_int64_t ctb_cur_width; /* 168: cursor width, height */
385     u_int64_t ctb_cur_height; /* 176: in pixels */
386     u_int64_t ctb_head_cnt; /* 184: # of heads */
387     u_int64_t ctb_opwindow; /* 192: opwindow on screen */
388     u_int64_t ctb_head_offset; /* 200: offset to head info */
389     u_int64_t ctb_putchar; /* 208: output char to TURBO */
390     u_int64_t ctb_io_state; /* 216: I/O flags */
391     u_int64_t ctb_listen_state; /* 224: listener flags */
392     u_int64_t ctb_xaddr; /* 232: extended info addr */
393     u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */
394     u_int64_t ctb_server_off; /* 256: offset to server info */
395     u_int64_t ctb_line_off; /* 264: line parameter offset */
396     u_int8_t ctb_csd; /* 272: console specific data */
397     };
398    
399     struct ctb_tt {
400     u_int64_t ctb_type; /* 0: CTB type */
401     u_int64_t ctb_unit; /* 8: console unit */
402     u_int64_t ctb_reserved; /* 16: reserved */
403     u_int64_t ctb_length; /* 24: length */
404     u_int64_t ctb_csr; /* 32: address */
405     u_int64_t ctb_tivec; /* 40: Tx intr vector */
406     u_int64_t ctb_rivec; /* 48: Rx intr vector */
407     u_int64_t ctb_baud; /* 56: baud rate */
408     u_int64_t ctb_put_sts; /* 64: PUTS status */
409     u_int64_t ctb_get_sts; /* 72: GETS status */
410     u_int64_t ctb_reserved0; /* 80: reserved */
411     };
412    
413     /*
414     * Format of the Console Terminal Block Type 4 `turboslot' field:
415     *
416     * 63 40 39 32 31 24 23 16 15 8 7 0
417     * | reserved | channel | hose | bus type | bus | slot|
418     */
419     #define CTB_TURBOSLOT_CHANNEL(x) (((x) >> 32) & 0xff)
420     #define CTB_TURBOSLOT_HOSE(x) (((x) >> 24) & 0xff)
421     #define CTB_TURBOSLOT_TYPE(x) (((x) >> 16) & 0xff)
422     #define CTB_TURBOSLOT_BUS(x) (((x) >> 8) & 0xff)
423     #define CTB_TURBOSLOT_SLOT(x) ((x) & 0xff)
424    
425     #define CTB_TURBOSLOT_TYPE_TC 0 /* TURBOchannel */
426     #define CTB_TURBOSLOT_TYPE_ISA 1 /* ISA */
427     #define CTB_TURBOSLOT_TYPE_EISA 2 /* EISA */
428     #define CTB_TURBOSLOT_TYPE_PCI 3 /* PCI */
429    
430     /*
431     * CRD: Console Routine Descriptor
432     */
433     struct crd {
434     int64_t descriptor;
435     u_int64_t entry_va;
436     };
437    
438     /*
439     * CRB: Console Routine Block
440     */
441     struct crb {
442     /* struct crd * */
443     u_int64_t crb_v_dispatch; /* 0: virtual dispatch addr */
444     u_int64_t crb_p_dispatch; /* 8: phys dispatch addr */
445     /* struct crd * */
446     u_int64_t crb_v_fixup; /* 10: virtual fixup addr */
447     u_int64_t crb_p_fixup; /* 18: phys fixup addr */
448     u_int64_t crb_map_cnt; /* 20: phys/virt map entries */
449     u_int64_t crb_page_cnt; /* 28: pages to be mapped */
450     };
451    
452     /*
453     * MDDT: Memory Data Descriptor Table
454     */
455     struct mddt {
456     int64_t mddt_cksum; /* 0: 7-N checksum */
457     u_int64_t mddt_physaddr; /* 8: bank config addr
458     * IMPLEMENTATION SPECIFIC
459     */
460     u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */
461     struct mddt_cluster {
462     u_int64_t mddt_pfn; /* 0: starting PFN */
463     u_int64_t mddt_pg_cnt; /* 8: 8KB page count */
464     u_int64_t mddt_pg_test; /* 10: tested page count */
465     u_int64_t mddt_v_bitaddr; /* 18: bitmap virt addr */
466     u_int64_t mddt_p_bitaddr; /* 20: bitmap phys addr */
467     int64_t mddt_bit_cksum; /* 28: bitmap checksum */
468    
469     #define MDDT_NONVOLATILE 0x10 /* cluster is non-volatile */
470     #define MDDT_PALCODE 0x01 /* console and PAL only */
471     #define MDDT_SYSTEM 0x00 /* system software only */
472     #define MDDT_mbz 0xfffffffffffffffc /* 2:63 -- must be zero */
473     int64_t mddt_usage; /* 30: bitmap permissions */
474 dpavlin 24 } mddt_clusters[2]; /* variable length array */
475 dpavlin 12 };
476    
477     /*
478     * DSR: Dynamic System Recognition. We're interested in the sysname
479     * offset. The data pointed to by sysname is:
480     *
481     * [8 bytes: length of system name][N bytes: system name string]
482     *
483     * The system name string is NUL-terminated.
484     */
485     struct dsrdb {
486     int64_t dsr_smm; /* 0: SMM number */
487     u_int64_t dsr_lurt_off; /* 8: LURT table offset */
488     u_int64_t dsr_sysname_off; /* 16: offset to sysname */
489     };
490    
491     /*
492     * The DSR appeared in version 5 of the HWRPB.
493     */
494     #define HWRPB_DSRDB_MINVERS 5
495    
496     #ifdef _KERNEL
497     extern int cputype;
498     extern struct rpb *hwrpb;
499     #endif
500    
501     #endif /* ASSEMBLER */

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