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/* $NetBSD: rpb.h,v 1.39.18.1 2002/07/29 14:45:46 lukem Exp $ */ |
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|
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#include <sys/types.h> |
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#include "misc.h" |
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|
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/* |
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* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. |
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* All rights reserved. |
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* |
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* Author: Keith Bostic, Chris G. Demetriou |
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* |
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* Permission to use, copy, modify and distribute this software and |
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* its documentation is hereby granted, provided that both the copyright |
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* notice and this permission notice appear in all copies of the |
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* software, derivative works or modified versions, and any portions |
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* thereof, and that both notices appear in supporting documentation. |
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* |
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" |
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND |
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. |
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* |
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* Carnegie Mellon requests users of this software to return to |
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* |
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU |
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* School of Computer Science |
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* Carnegie Mellon University |
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* Pittsburgh PA 15213-3890 |
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* |
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* any improvements or extensions that they make and grant Carnegie the |
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* rights to redistribute these changes. |
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*/ |
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|
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/* |
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* From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual, |
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* EK-D3SYS-PM.B01. |
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*/ |
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|
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/* |
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* HWRPB (Hardware Restart Parameter Block). |
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*/ |
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#define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ |
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|
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/* GXemul: */ |
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#define PROM_ENTRY_PADDR 0x10000 |
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#define PROM_ARGSPACE_PADDR 0x12000 |
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#define HWRPB_PADDR 0x14000 |
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#define CTB_ADDR (HWRPB_ADDR + 0x1000) |
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#define CRB_ADDR (HWRPB_ADDR + 0x1400) |
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#define MEMDAT_ADDR (HWRPB_ADDR + 0x1800) |
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#define PCS_ADDR (HWRPB_ADDR + 0x1c00) |
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|
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#ifndef ASSEMBLER |
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struct rpb { |
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u_int64_t rpb_phys; /* 0: HWRPB phys. address. */ |
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char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ |
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u_int64_t rpb_version; /* 10 */ |
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u_int64_t rpb_size; /* 18: HWRPB size in bytes */ |
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u_int64_t rpb_primary_cpu_id; /* 20 */ |
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u_int64_t rpb_page_size; /* 28: (8192) */ |
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u_int32_t rpb_phys_addr_size; /* 30: physical address size */ |
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u_int32_t rpb_extended_va_size; /* 34: extended VA size (4L) */ |
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u_int64_t rpb_max_asn; /* 38: (16) */ |
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char rpb_ssn[16]; /* 40: only first 10 valid */ |
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|
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#define ST_ADU 1 /* Alpha Demo. Unit (?) */ |
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#define ST_DEC_4000 2 /* "Cobra" */ |
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#define ST_DEC_7000 3 /* "Ruby" */ |
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#define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */ |
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#define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */ |
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#define ST_DEC_3000_300 7 /* "Pelican" (TC) */ |
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#define ST_AVALON_A12 8 /* XXX Avalon Multicomputer */ |
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#define ST_DEC_2100_A500 9 /* "Sable" */ |
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#define ST_DEC_APXVME_64 10 /* "AXPvme" (VME) */ |
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#define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */ |
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#define ST_DEC_21000 12 /* "TurboLaser" (PCI/EISA) */ |
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#define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */ |
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#define ST_DEC_MUSTANG 14 /* "Mustang" */ |
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#define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */ |
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#define ST_DEC_1000 17 /* "Mikasa" (PCI/EISA) */ |
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#define ST_EB66 19 /* EB66 (PCI/ISA?) */ |
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#define ST_EB64P 20 /* EB64+ (PCI/ISA?) */ |
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#define ST_ALPHABOOK1 21 /* Alphabook1 */ |
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#define ST_DEC_4100 22 /* "Rawhide" (PCI/EISA) */ |
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#define ST_DEC_EV45_PBP 23 /* "Lego" K2 Passive SBC */ |
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#define ST_DEC_2100A_A500 24 /* "Lynx" */ |
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#define ST_EB164 26 /* EB164 (PCI/ISA) */ |
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#define ST_DEC_1000A 27 /* "Noritake" (PCI/EISA)*/ |
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#define ST_DEC_ALPHAVME_224 28 /* "Cortex" */ |
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#define ST_DEC_550 30 /* "Miata" (PCI/ISA) */ |
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#define ST_DEC_EV56_PBP 32 /* "Takara" */ |
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#define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME) */ |
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#define ST_DEC_6600 34 /* EV6-Tsunami based systems */ |
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#define ST_DEC_WILDFIRE 35 /* "Wildfire" */ |
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#define ST_DEC_CUSCO 36 /* "CUSCO" */ |
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#define ST_DEC_EIGER 37 /* "Eiger" */ |
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#define ST_DEC_TITAN 38 /* "Titan" */ |
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|
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/* Alpha Processor, Inc. systypes */ |
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#define ST_API_NAUTILUS 201 /* EV6-AMD 751 UP1000 */ |
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|
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u_int64_t rpb_type; /* 50: */ |
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|
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#define SV_MPCAP 0x00000001 /* multiprocessor capable */ |
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|
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#define SV_CONSOLE 0x0000001e /* console hardware mask */ |
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#define SV_CONSOLE_DETACHED 0x00000002 |
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#define SV_CONSOLE_EMBEDDED 0x00000004 |
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|
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#define SV_POWERFAIL 0x000000e0 /* powerfail mask */ |
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#define SV_PF_UNITED 0x00000020 |
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#define SV_PF_SEPARATE 0x00000040 |
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#define SV_PF_BBACKUP 0x00000060 |
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#define SV_PF_ACTION 0x00000100 /* powerfail restart */ |
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|
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#define SV_GRAPHICS 0x00000200 /* graphic engine present */ |
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|
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#define SV_ST_MASK 0x0000fc00 /* system type mask */ |
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#define SV_ST_RESERVED 0x00000000 /* RESERVED */ |
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|
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/* |
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* System types for the DEC 3000/500 (Flamingo) Family |
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*/ |
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#define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */ |
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#define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */ |
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#define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */ |
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#define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */ |
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#define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */ |
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#define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */ |
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#define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */ |
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#define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */ |
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|
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/* |
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* System types for ??? |
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*/ |
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#define SV_ST_SABLE 0x00000400 /* Sable (???) */ |
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|
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/* |
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* System types for the DEC 3000/300 (Pelican) Family |
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*/ |
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#define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */ |
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#define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */ |
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#define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */ |
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#define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */ |
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|
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/* |
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* System types for the AlphaStation Family |
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*/ |
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#define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */ |
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#define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */ |
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#define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */ |
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#define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */ |
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#define SV_ST_AVANTI_4_266 0x00002000 |
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#define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */ |
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#define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */ |
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|
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#define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */ |
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|
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/* |
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* System types for the AXPvme Family |
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*/ |
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#define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */ |
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#define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */ |
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#define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */ |
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#define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */ |
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#define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */ |
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#define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */ |
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#define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */ |
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|
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/* |
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* System types for the EB164 Family |
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*/ |
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#define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */ |
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#define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */ |
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#define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */ |
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#define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */ |
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#define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */ |
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#define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */ |
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#define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */ |
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#define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */ |
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#define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */ |
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#define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */ |
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#define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */ |
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#define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */ |
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#define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */ |
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#define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */ |
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#define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */ |
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|
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/* |
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* System types for the Digital Personal Workstation (Miata) Family |
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* XXX These are not very complete! |
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*/ |
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#define SV_ST_MIATA_1_5 0x00004c00 /* Miata 1.5 */ |
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|
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u_int64_t rpb_variation; /* 58 */ |
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|
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char rpb_revision[8]; /* 60; only first 4 valid */ |
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u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */ |
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u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */ |
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u_int64_t rpb_vptb; /* 78: */ |
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u_int64_t rpb_reserved_arch; /* 80: */ |
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u_int64_t rpb_tbhint_off; /* 88: */ |
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u_int64_t rpb_pcs_cnt; /* 90: */ |
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u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */ |
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u_int64_t rpb_pcs_off; /* A0: offset to pcs info */ |
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u_int64_t rpb_ctb_cnt; /* A8: console terminal */ |
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u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */ |
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u_int64_t rpb_ctb_off; /* B8: offset to ctb */ |
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u_int64_t rpb_crb_off; /* C0: offset to crb */ |
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u_int64_t rpb_memdat_off; /* C8: memory data offset */ |
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u_int64_t rpb_condat_off; /* D0: config data offset */ |
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u_int64_t rpb_fru_off; /* D8: FRU table offset */ |
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u_int64_t rpb_save_term; /* E0: terminal save */ |
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u_int64_t rpb_save_term_val; /* E8: */ |
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u_int64_t rpb_rest_term; /* F0: terminal restore */ |
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u_int64_t rpb_rest_term_val; /* F8: */ |
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u_int64_t rpb_restart; /* 100: restart */ |
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u_int64_t rpb_restart_val; /* 108: */ |
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u_int64_t rpb_reserve_os; /* 110: */ |
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u_int64_t rpb_reserve_hw; /* 118: */ |
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u_int64_t rpb_checksum; /* 120: HWRPB checksum */ |
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u_int64_t rpb_rxrdy; /* 128: receive ready */ |
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u_int64_t rpb_txrdy; /* 130: transmit ready */ |
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u_int64_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ |
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u_int64_t rpb_tbhint[8]; /* 140: TB hint block */ |
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}; |
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|
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#define LOCATE_PCS(h,cpunumber) ((struct pcs *) \ |
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((char *)(h) + (h)->rpb_pcs_off + ((cpunumber) * (h)->rpb_pcs_size))) |
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|
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/* |
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* PCS: Per-CPU information. |
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*/ |
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struct pcs { |
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u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */ |
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|
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#define PCS_BIP 0x000001 /* boot in progress */ |
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#define PCS_RC 0x000002 /* restart possible */ |
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#define PCS_PA 0x000004 /* processor available */ |
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#define PCS_PP 0x000008 /* processor present */ |
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#define PCS_OH 0x000010 /* user halted */ |
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#define PCS_CV 0x000020 /* context valid */ |
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#define PCS_PV 0x000040 /* PALcode valid */ |
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#define PCS_PMV 0x000080 /* PALcode memory valid */ |
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#define PCS_PL 0x000100 /* PALcode loaded */ |
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|
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#define PCS_HALT_REQ 0xff0000 /* halt request mask */ |
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#define PCS_HALT_DEFAULT 0x000000 |
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#define PCS_HALT_SAVE_EXIT 0x010000 |
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#define PCS_HALT_COLD_BOOT 0x020000 |
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#define PCS_HALT_WARM_BOOT 0x030000 |
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#define PCS_HALT_STAY_HALTED 0x040000 |
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#define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ |
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u_int64_t pcs_flags; /* 80: */ |
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|
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u_int64_t pcs_pal_memsize; /* 88: PAL memory size */ |
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u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */ |
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u_int64_t pcs_pal_memaddr; /* 98: PAL memory addr */ |
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u_int64_t pcs_pal_scraddr; /* A0: PAL scratch addr */ |
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struct { |
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int /* TODO/NOTE: should be uint64_t */ |
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minorrev : 8, /* alphabetic char 'a' - 'z' */ |
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majorrev : 8, /* alphabetic char 'a' - 'z' */ |
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#define PAL_TYPE_STANDARD 0 |
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#define PAL_TYPE_VMS 1 |
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#define PAL_TYPE_OSF1 2 |
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pal_type : 8, /* PALcode type: |
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* 0 == standard |
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* 1 == OpenVMS |
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* 2 == OSF/1 |
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* 3-127 DIGITAL reserv. |
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* 128-255 non-DIGITAL reserv. |
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*/ |
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sbz1 : 8, |
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compatibility : 16, /* Compatibility revision */ |
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proc_cnt : 16; /* Processor count */ |
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} pcs_pal_rev; /* A8: */ |
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#define pcs_minorrev pcs_pal_rev.minorrev |
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#define pcs_majorrev pcs_pal_rev.majorrev |
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#define pcs_pal_type pcs_pal_rev.pal_type |
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#define pcs_compatibility pcs_pal_rev.compatibility |
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#define pcs_proc_cnt pcs_pal_rev.proc_cnt |
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|
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u_int64_t pcs_proc_type; /* B0: processor type */ |
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|
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#define PCS_PROC_EV3 1 /* EV3 */ |
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#define PCS_PROC_EV4 2 /* EV4: 21064 */ |
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#define PCS_PROC_SIMULATION 3 /* Simulation */ |
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#define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */ |
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#define PCS_PROC_EV5 5 /* EV5: 21164 */ |
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#define PCS_PROC_EV45 6 /* EV45: 21064A */ |
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#define PCS_PROC_EV56 7 /* EV56: 21164A */ |
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#define PCS_PROC_EV6 8 /* EV6: 21264 */ |
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#define PCS_PROC_PCA56 9 /* PCA56: 21164PC */ |
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#define PCS_PROC_PCA57 10 /* PCA57: 21164?? */ |
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#define PCS_PROC_EV67 11 /* EV67: 21246A */ |
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#define PCS_PROC_EV68CB 12 /* EV68CB: 21264C */ |
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#define PCS_PROC_EV68AL 13 /* EV68AL: 21264B */ |
| 298 |
#define PCS_PROC_EV68CX 14 /* EV68CX: 21264D */ |
| 299 |
|
| 300 |
#define PCS_CPU_MAJORTYPE(p) ((p)->pcs_proc_type & 0xffffffff) |
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#define PCS_CPU_MINORTYPE(p) ((p)->pcs_proc_type >> 32) |
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|
| 303 |
/* Minor number interpretation is processor specific. See cpu.c. */ |
| 304 |
|
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u_int64_t pcs_proc_var; /* B8: processor variation. */ |
| 306 |
|
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#define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */ |
| 308 |
#define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */ |
| 309 |
#define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */ |
| 310 |
#define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */ |
| 311 |
|
| 312 |
char pcs_proc_revision[8]; /* C0: only first 4 valid */ |
| 313 |
char pcs_proc_sn[16]; /* C8: only first 10 valid */ |
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u_int64_t pcs_machcheck; /* D8: mach chk phys addr. */ |
| 315 |
u_int64_t pcs_machcheck_len; /* E0: length in bytes */ |
| 316 |
u_int64_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */ |
| 317 |
u_int64_t pcs_halt_pc; /* F0: halt PC */ |
| 318 |
u_int64_t pcs_halt_ps; /* F8: halt PS */ |
| 319 |
u_int64_t pcs_halt_r25; /* 100: halt argument list */ |
| 320 |
u_int64_t pcs_halt_r26; /* 108: halt return addr list */ |
| 321 |
u_int64_t pcs_halt_r27; /* 110: halt procedure value */ |
| 322 |
|
| 323 |
#define PCS_HALT_RESERVED 0 |
| 324 |
#define PCS_HALT_POWERUP 1 |
| 325 |
#define PCS_HALT_CONSOLE_HALT 2 |
| 326 |
#define PCS_HALT_CONSOLE_CRASH 3 |
| 327 |
#define PCS_HALT_KERNEL_MODE 4 |
| 328 |
#define PCS_HALT_KERNEL_STACK_INVALID 5 |
| 329 |
#define PCS_HALT_DOUBLE_ERROR_ABORT 6 |
| 330 |
#define PCS_HALT_SCBB 7 |
| 331 |
#define PCS_HALT_PTBR 8 /* 9-FF: reserved */ |
| 332 |
u_int64_t pcs_halt_reason; /* 118: */ |
| 333 |
|
| 334 |
u_int64_t pcs_reserved_soft; /* 120: preserved software */ |
| 335 |
|
| 336 |
struct { /* 128: inter-console buffers */ |
| 337 |
u_int iccb_rxlen; |
| 338 |
u_int iccb_txlen; |
| 339 |
char iccb_rxbuf[80]; |
| 340 |
char iccb_txbuf[80]; |
| 341 |
} pcs_iccb; |
| 342 |
|
| 343 |
#define PALvar_reserved 0 |
| 344 |
#define PALvar_OpenVMS 1 |
| 345 |
#define PALvar_OSF1 2 |
| 346 |
u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ |
| 347 |
|
| 348 |
u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */ |
| 349 |
}; |
| 350 |
|
| 351 |
/* |
| 352 |
* CTB: Console Terminal Block |
| 353 |
*/ |
| 354 |
struct ctb { |
| 355 |
u_int64_t ctb_type; /* 0: CTB type */ |
| 356 |
u_int64_t ctb_unit; /* 8: */ |
| 357 |
u_int64_t ctb_reserved; /* 16: */ |
| 358 |
u_int64_t ctb_len; /* 24: bytes of info */ |
| 359 |
u_int64_t ctb_ipl; /* 32: console ipl level */ |
| 360 |
u_int64_t ctb_tintr_vec; /* 40: transmit vec (0x800) */ |
| 361 |
u_int64_t ctb_rintr_vec; /* 48: receive vec (0x800) */ |
| 362 |
|
| 363 |
#define CTB_NONE 0x00 /* no console present */ |
| 364 |
#define CTB_SERVICE 0x01 /* service processor */ |
| 365 |
#define CTB_PRINTERPORT 0x02 /* printer port on the SCC */ |
| 366 |
#define CTB_GRAPHICS 0x03 /* graphics device */ |
| 367 |
#define CTB_TYPE4 0x04 /* type 4 CTB */ |
| 368 |
#define CTB_NETWORK 0xC0 /* network device */ |
| 369 |
u_int64_t ctb_term_type; /* 56: terminal type */ |
| 370 |
|
| 371 |
u_int64_t ctb_keybd_type; /* 64: keyboard nationality */ |
| 372 |
u_int64_t ctb_keybd_trans; /* 72: trans. table addr */ |
| 373 |
u_int64_t ctb_keybd_map; /* 80: map table addr */ |
| 374 |
u_int64_t ctb_keybd_state; /* 88: keyboard flags */ |
| 375 |
u_int64_t ctb_keybd_last; /* 96: last key entered */ |
| 376 |
u_int64_t ctb_font_us; /* 104: US font table addr */ |
| 377 |
u_int64_t ctb_font_mcs; /* 112: MCS font table addr */ |
| 378 |
u_int64_t ctb_font_width; /* 120: font width, height */ |
| 379 |
u_int64_t ctb_font_height; /* 128: in pixels */ |
| 380 |
u_int64_t ctb_mon_width; /* 136: monitor width, height */ |
| 381 |
u_int64_t ctb_mon_height; /* 144: in pixels */ |
| 382 |
u_int64_t ctb_dpi; /* 152: monitor dots per inch */ |
| 383 |
u_int64_t ctb_planes; /* 160: # of planes */ |
| 384 |
u_int64_t ctb_cur_width; /* 168: cursor width, height */ |
| 385 |
u_int64_t ctb_cur_height; /* 176: in pixels */ |
| 386 |
u_int64_t ctb_head_cnt; /* 184: # of heads */ |
| 387 |
u_int64_t ctb_opwindow; /* 192: opwindow on screen */ |
| 388 |
u_int64_t ctb_head_offset; /* 200: offset to head info */ |
| 389 |
u_int64_t ctb_putchar; /* 208: output char to TURBO */ |
| 390 |
u_int64_t ctb_io_state; /* 216: I/O flags */ |
| 391 |
u_int64_t ctb_listen_state; /* 224: listener flags */ |
| 392 |
u_int64_t ctb_xaddr; /* 232: extended info addr */ |
| 393 |
u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */ |
| 394 |
u_int64_t ctb_server_off; /* 256: offset to server info */ |
| 395 |
u_int64_t ctb_line_off; /* 264: line parameter offset */ |
| 396 |
u_int8_t ctb_csd; /* 272: console specific data */ |
| 397 |
}; |
| 398 |
|
| 399 |
struct ctb_tt { |
| 400 |
u_int64_t ctb_type; /* 0: CTB type */ |
| 401 |
u_int64_t ctb_unit; /* 8: console unit */ |
| 402 |
u_int64_t ctb_reserved; /* 16: reserved */ |
| 403 |
u_int64_t ctb_length; /* 24: length */ |
| 404 |
u_int64_t ctb_csr; /* 32: address */ |
| 405 |
u_int64_t ctb_tivec; /* 40: Tx intr vector */ |
| 406 |
u_int64_t ctb_rivec; /* 48: Rx intr vector */ |
| 407 |
u_int64_t ctb_baud; /* 56: baud rate */ |
| 408 |
u_int64_t ctb_put_sts; /* 64: PUTS status */ |
| 409 |
u_int64_t ctb_get_sts; /* 72: GETS status */ |
| 410 |
u_int64_t ctb_reserved0; /* 80: reserved */ |
| 411 |
}; |
| 412 |
|
| 413 |
/* |
| 414 |
* Format of the Console Terminal Block Type 4 `turboslot' field: |
| 415 |
* |
| 416 |
* 63 40 39 32 31 24 23 16 15 8 7 0 |
| 417 |
* | reserved | channel | hose | bus type | bus | slot| |
| 418 |
*/ |
| 419 |
#define CTB_TURBOSLOT_CHANNEL(x) (((x) >> 32) & 0xff) |
| 420 |
#define CTB_TURBOSLOT_HOSE(x) (((x) >> 24) & 0xff) |
| 421 |
#define CTB_TURBOSLOT_TYPE(x) (((x) >> 16) & 0xff) |
| 422 |
#define CTB_TURBOSLOT_BUS(x) (((x) >> 8) & 0xff) |
| 423 |
#define CTB_TURBOSLOT_SLOT(x) ((x) & 0xff) |
| 424 |
|
| 425 |
#define CTB_TURBOSLOT_TYPE_TC 0 /* TURBOchannel */ |
| 426 |
#define CTB_TURBOSLOT_TYPE_ISA 1 /* ISA */ |
| 427 |
#define CTB_TURBOSLOT_TYPE_EISA 2 /* EISA */ |
| 428 |
#define CTB_TURBOSLOT_TYPE_PCI 3 /* PCI */ |
| 429 |
|
| 430 |
/* |
| 431 |
* CRD: Console Routine Descriptor |
| 432 |
*/ |
| 433 |
struct crd { |
| 434 |
int64_t descriptor; |
| 435 |
u_int64_t entry_va; |
| 436 |
}; |
| 437 |
|
| 438 |
/* |
| 439 |
* CRB: Console Routine Block |
| 440 |
*/ |
| 441 |
struct crb { |
| 442 |
/* struct crd * */ |
| 443 |
u_int64_t crb_v_dispatch; /* 0: virtual dispatch addr */ |
| 444 |
u_int64_t crb_p_dispatch; /* 8: phys dispatch addr */ |
| 445 |
/* struct crd * */ |
| 446 |
u_int64_t crb_v_fixup; /* 10: virtual fixup addr */ |
| 447 |
u_int64_t crb_p_fixup; /* 18: phys fixup addr */ |
| 448 |
u_int64_t crb_map_cnt; /* 20: phys/virt map entries */ |
| 449 |
u_int64_t crb_page_cnt; /* 28: pages to be mapped */ |
| 450 |
}; |
| 451 |
|
| 452 |
/* |
| 453 |
* MDDT: Memory Data Descriptor Table |
| 454 |
*/ |
| 455 |
struct mddt { |
| 456 |
int64_t mddt_cksum; /* 0: 7-N checksum */ |
| 457 |
u_int64_t mddt_physaddr; /* 8: bank config addr |
| 458 |
* IMPLEMENTATION SPECIFIC |
| 459 |
*/ |
| 460 |
u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */ |
| 461 |
struct mddt_cluster { |
| 462 |
u_int64_t mddt_pfn; /* 0: starting PFN */ |
| 463 |
u_int64_t mddt_pg_cnt; /* 8: 8KB page count */ |
| 464 |
u_int64_t mddt_pg_test; /* 10: tested page count */ |
| 465 |
u_int64_t mddt_v_bitaddr; /* 18: bitmap virt addr */ |
| 466 |
u_int64_t mddt_p_bitaddr; /* 20: bitmap phys addr */ |
| 467 |
int64_t mddt_bit_cksum; /* 28: bitmap checksum */ |
| 468 |
|
| 469 |
#define MDDT_NONVOLATILE 0x10 /* cluster is non-volatile */ |
| 470 |
#define MDDT_PALCODE 0x01 /* console and PAL only */ |
| 471 |
#define MDDT_SYSTEM 0x00 /* system software only */ |
| 472 |
#define MDDT_mbz 0xfffffffffffffffc /* 2:63 -- must be zero */ |
| 473 |
int64_t mddt_usage; /* 30: bitmap permissions */ |
| 474 |
} mddt_clusters[2]; /* variable length array */ |
| 475 |
}; |
| 476 |
|
| 477 |
/* |
| 478 |
* DSR: Dynamic System Recognition. We're interested in the sysname |
| 479 |
* offset. The data pointed to by sysname is: |
| 480 |
* |
| 481 |
* [8 bytes: length of system name][N bytes: system name string] |
| 482 |
* |
| 483 |
* The system name string is NUL-terminated. |
| 484 |
*/ |
| 485 |
struct dsrdb { |
| 486 |
int64_t dsr_smm; /* 0: SMM number */ |
| 487 |
u_int64_t dsr_lurt_off; /* 8: LURT table offset */ |
| 488 |
u_int64_t dsr_sysname_off; /* 16: offset to sysname */ |
| 489 |
}; |
| 490 |
|
| 491 |
/* |
| 492 |
* The DSR appeared in version 5 of the HWRPB. |
| 493 |
*/ |
| 494 |
#define HWRPB_DSRDB_MINVERS 5 |
| 495 |
|
| 496 |
#ifdef _KERNEL |
| 497 |
extern int cputype; |
| 498 |
extern struct rpb *hwrpb; |
| 499 |
#endif |
| 500 |
|
| 501 |
#endif /* ASSEMBLER */ |
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